JP5805261B2 - Solid-state imaging device and driving method of solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device and a driving method of the solid-state imaging device.

  In a solid-state imaging device, an improvement in S / N ratio and an expansion of a dynamic range are required. In response to such a request, Patent Document 1 provides an amplifier circuit for each column of pixels arranged in a matrix and a detection circuit for detecting a signal level for each pixel signal for each column. Thus, signal saturation in the column amplifier circuit is avoided, the gain of the pixel signal is controlled within a range in which the small amplitude signal is not saturated, and the gain is returned to the original circuit in the subsequent stage.

  In Patent Document 2, a low gain signal and a high gain signal are generated from a pixel signal from an image sensor by a column amplification circuit for each column. Then, a signal obtained by returning a high gain signal to the same gain as a low gain signal and a low gain signal are selectively combined to expand the dynamic range while maintaining the S / N ratio.

  Patent Document 3 describes a conversion error correction method during AD conversion.

JP 2004-015701 A JP 2010-16416 A Japanese Patent Laid-Open No. 11-088166

  However, in the technique disclosed in Patent Document 1, since a detection circuit for detecting a pixel signal is provided in each column of pixels and the gain is changed for each column, the control circuit becomes complicated. The area occupied by the solid-state imaging device increases. Furthermore, there is a problem that the S / N ratio is different for each pixel.

  In Patent Documents 1 and 2, AD conversion is performed by changing the gain of the pixel signal in the column amplification unit. However, in the disclosed technique, detection of the gain error and AD conversion error at that time and a correction method thereof are described. Not. The technique disclosed in Patent Document 3 corrects conversion errors before and after AD conversion of the AD converter itself. Further, this is not a method of correcting a gain error between signals amplified by different gains of a plurality of column amplification units and column AD converters.

  An object of the present invention is to provide a solid-state imaging device and a driving method of the solid-state imaging device that can reduce a gain error and an analog-digital conversion error when signals amplified with different gains are obtained.

  The solid-state imaging device of the present invention is arranged in a matrix and is provided in each of the plurality of pixels, a plurality of pixels that generate signals by photoelectric conversion, a reference signal input unit that generates a reference signal, and the plurality of pixels A column amplifying unit that outputs a first signal obtained by amplifying the pixel signal or the reference signal with a first gain and a second signal amplified with a second gain greater than the first gain; The first digital signal and the second digital signal are converted to a first digital signal, and the second digital signal is converted to a second digital signal. And a correction unit that performs correction processing so that a gain error with respect to the signal is reduced.

  According to the present invention, it is possible to reduce the gain error of the column amplification unit and / or the conversion error of the analog-digital conversion unit when signals amplified with different gains are obtained.

It is a signal level diagram for demonstrating embodiment of this invention. 1 is an overall block diagram of a solid-state imaging device according to a first embodiment. It is a figure which shows schematic structure of the bit process part which concerns on the 1st Embodiment of this invention. It is a figure which shows the bit switching of the AD conversion signal of a different gain. It is a figure which shows schematic structure of the solid-state image sensor of the 1st Embodiment of this invention. FIG. 3 is a schematic circuit diagram of two column amplification units according to the embodiment of the present invention. FIG. 7 is a schematic timing diagram of the embodiment of FIG. 6. It is a schematic circuit diagram of one column amplifier according to an embodiment of the present invention. FIG. 9 is a schematic timing diagram of the embodiment of FIG. 8. It is an imaging timing explanatory diagram of the solid-state imaging device according to the first embodiment. It is a figure which shows schematic structure of the reference signal input circuit which concerns on 2nd Embodiment. It is a figure which shows schematic structure of the reference signal input circuit of 3rd Embodiment. It is a figure which shows schematic structure of the solid-state image sensor which concerns on 2nd Embodiment. It is an imaging timing explanatory diagram of the solid-state imaging device according to the second embodiment. It is a figure which shows schematic structure of the solid-state image sensor which concerns on 4th Embodiment. It is a figure which shows schematic structure of the bit process part which concerns on 5th Embodiment. It is a figure which shows schematic structure of the solid-state image sensor of 6th Embodiment. It is a signal level figure explaining a gain error.

(First embodiment)
In order to clarify the characteristics of the first embodiment of the present invention, the problems concerned with the methods described in Patent Documents 1 and 2 will be described in more detail. Consider signal level errors and analog-digital (AD) conversion errors when two different gain designs are used (for example, G1 is a design with a gain of 1 and G8 is a design with a gain of 8).

  FIG. 18 is a signal level diagram for explaining the gain error. In the figure, the horizontal axis represents the amount of light reflected from the subject, and the vertical axis represents the pixel signal level at that time. In G8 #, the gain of G8 is returned to be the same as the gain of G1. In particular, since there is an error in the semiconductor process between the gains of the column amplifier circuit, when the G1 small signal part (low light quantity part) is replaced with G8 # in the subsequent circuit as shown in the figure, the signal level of G1 is obtained. On the other hand, a signal level difference corresponding to the amount of light occurs. Further, if the decision to replace the small signal portion of G1 with G8 # is made in the vicinity of the fully saturated signal level VH (a) of the G8 signal, this is also caused by an error factor due to signal saturation of the column amplification unit of the pixel signal or signal nonlinearity. Become.

Next, the gain error is expressed by a simple formula. The gain errors of G1 and G8 are a and b, respectively, and the conversion error of the AD converter is α. Here, it is assumed that both the gain error and the conversion error are several percent, and the data DA (G1) and DA (G8) after the AD conversion of the gains G1 and G8 are equations (1) and (2) as approximate expressions.
DA (G1) = (1 + a) (1 + α) ≈1 + a + α (1)
DA (G8) = (8 + b) (1 + α) ≈8 (1 + α) + b (2)

Here, when the difference ΔV between the expression (1) and the expression (3) obtained by returning DA (G8) to the original gain of 1 and the expression (3), the expression (4) is obtained.
DA (G8 / 8) = DA (G8) × 1/8 = 1 + α + b / 8 (3)
ΔV = DA (G8 / 8) −DA (G1) = b / 8−a (4)

  Even if ΔV in Expression (4) is several percent, the image is visually recognized as a level difference after image synthesis. However, since the human eye is sensitive to such a level difference, the deterioration of the image quality is remarkably recognized.

Next, the principle of the present invention will be described. FIG. 1 is a signal level diagram for explaining the present embodiment. The complete saturation signal level VH (a) is the signal level of the second signal G8 when the second signal G8 has a light amount a at which the second signal G8 is completely saturated. In order to improve the SN ratio of the pixel signal and expand the dynamic range, signals with two different gains are used. In the present invention, a gain error due to different signal processing such as a column amplification unit and an AD conversion unit is detected and the error is corrected, or offset correction is performed using a difference in signal level as an offset voltage. In FIG. 1, a signal having a gain of 1 is referred to as a first signal G1 (hereinafter referred to as signal G1), and a signal having a gain of 8 is referred to as a second signal G8 (hereinafter referred to as signal G8). A signal obtained by level-shifting the gain of the signal G8 after the signal processing to the gain of the signal G1 is G8 #. The slopes of the signal G8 # and the signal G1 are different. This is a gain error. In the present embodiment, the gain error is detected at the signal level of the light amount b with good signal linearity. The first signal level VH (b) is the signal level of the second signal G8 when the second signal G8 has a light amount b less than the light amount at which saturation starts, and is a signal level less than the saturation start signal level. . The signal level VL (b) is the signal level of the first signal G1 when the light quantity is b. The signal level VH (b) # is the signal level of the signal G8 # when the light amount is b. Since the gain error is (VH (b) # / VL (b)), the correction coefficient K is expressed by the following equation (5) which is the reciprocal of the gain error.
K = VL (b) / VH (b) # (5)
Since the signal level difference is VH (b) # − VL (b), the offset voltage correction value Voffset is expressed by the following equation.
Voffset = − (VH (b) # − VL (b)) (6)

  If the signal G8 # is multiplied by the correction coefficient K, the signal G8 ## having the same signal level as the signal G1 can be obtained. Alternatively, the level difference between signals can be reduced by performing offset correction on the signal level of the signal G1 equal to or higher than V1 (b) by using the offset voltage correction value represented by the equation (6). By returning the signal G8 to the gain of the signal G1 by such signal processing, the noise of the signal processing circuit can be improved to 1 / G8 for the small amplitude signal. In the detection of the gain error, the signal level is detected not at the saturated signal level but at a signal level with good linearity and the correction coefficient is obtained, so that the signal level difference at the time of signal synthesis, that is, the joint of the image can be reduced.

  FIG. 2 is an overall block diagram of the solid-state imaging device according to the first embodiment of the present invention. The solid-state imaging device includes a solid-state imaging device 1 that outputs gain signals of different captured images in parallel, a signal processing unit 2 that processes a signal from the solid-state imaging device 1, and a recording that records an image signal from the signal processing unit 2. Part (media) 3. Furthermore, the solid-state imaging device includes a display unit 4 that displays an image signal from the signal processing unit 2, an image signal from the recording unit 3, and the like, and a CPU 5 that controls the above-described components. The signal processing unit 2 includes an analog-to-digital conversion unit (AD conversion unit) 21 that converts the first signal G1 and the second signal G8 having different gains from the solid-state imaging device 1 from analog to digital, and an AD conversion unit 21 And a bit processing unit 22 that forms a composite signal from the signal. Further, the signal processing unit 2 includes a DSP 23 that processes a signal from the bit processing unit 22 as a camera signal, an AD conversion unit 21, a timing generator (TG) 24 that generates a signal processing timing pulse of the bit processing unit 22 and the DSP 23, and Have The AD conversion unit 21 converts the first signal G1 and the second signal G8 from analog to digital by different AD conversion units.

  FIG. 3 is a diagram showing a schematic configuration of the bit processing unit 22 according to the first embodiment of the present invention. The output signal DATA1 of the AD conversion unit 21 that converts the analog signal from the solid-state imaging device 1 into a digital signal is a signal obtained by AD-converting the first signal G1 having a low gain with 12 bits, and the output signal DATA2 is a first signal having a high gain. 2 is a signal obtained by AD-converting the signal G8 of 12 bits. As described with reference to FIG. 1, the bit shift unit 221 performs gain conversion for replacing the first signal DATA1 (G1) with the second signal DATA2 (G8) with the light amount b or less. Since the gain difference between the two signals in the column amplification unit of the solid-state imaging device 1 is (G1 / G8 = 1/8), the bit shift unit 221 uses the second signal DATA2 (G8) as the first signal DATA1. A third signal G8 # level-shifted to the same gain level as (G1) is output. Specifically, the bit shift unit 221 digitally shifts the second signal DATA2 (G8) by a 3-bit level, thereby multiplying the signal DATA2 (G8) by 1/8 and outputting the signal G8 # To do. In this embodiment, the gain for the high gain signal is set to 8 times, but the high gain may be changed according to the shooting situation. For example, in the case of photographing a relatively dark subject and requiring 16 times the high gain as the imaging sensitivity, the gain difference is 16 times, so the level shift is 4 bits.

  The comparison level determination unit 222 determines whether or not the signal DATA2 (G8) is equal to or lower than the first signal level VH (b) of the light amount b, and outputs a signal indicating the light amount b to the comparison unit 224. . The comparison unit 224 receives the signal from the comparison level determination unit 222, compares the signal DATA1 (G1) at the light amount b with the output signal G8 # of the bit shift unit 221, and compares the difference ΔV between the signals DATA1 (G1) and G8 #. Is output. As shown in FIG. 1, since the signal G8 is not saturated at the light amount b and the signal linearity is good, the comparison unit 224 detects the gain error ΔV at the light amount b to detect the gain error ΔV with high accuracy. The gain error ΔV can be detected. This gain error ΔV is expressed by “b / 8-a” as shown in Expression (4). The gain error ΔV differs depending on whether the column amplification unit and the AD conversion unit, which will be described later, are the same or whether separate AD conversion units are provided, but basically the influence of the gain error a at a low gain. Is big. The gain error here refers to a difference from the design value (target) of the gain of the column amplifier, variation of design circuit elements in the semiconductor process, and the like.

  Since the gain error ΔV detected by the comparator 224 is (VH (b) # / VL (b)) as described in FIG. 1, the inverse of the gain error ΔV is used as the gain error correction coefficient K or The offset voltage correction value is stored in the correction data memory unit 225. The correction unit 226 corrects a gain error or a signal level difference by multiplying the third signal G8 # output from the bit shift unit 221 and the correction coefficient K of the correction data memory unit 225, or by adding / subtracting an offset voltage correction value. The signal DATA21 (G8 ##) is output. The correcting unit 226 corrects the third signal G8 # based on the correction coefficient K. The correcting unit 226 may correct the first signal DATA1 (G1) or the second signal DATA2 (G8) based on the correction coefficient K or the offset voltage correction value.

  The switching flag unit 223 outputs a high-level selection signal φb to the bit switching unit 227 when the second signal DATA2 (G8) is a signal level equal to or lower than the first signal level VH (b) of the light amount b. The switching flag unit 223 outputs a low-level selection signal φb to the bit switching unit 227 when the second signal DATA2 (G8) is greater than the first signal level VH (b) of the light amount b. Alternatively, the switching flag unit 223 outputs the high-level selection signal φb to the bit switching unit 227 if the first signal DATA1 (G1) is equal to or less than the signal level VL (b) of the light amount b, and otherwise the low level. The selection signal φb is output. The bit switching unit 227 selects and outputs the signal DATA1 (G1) when the low level selection signal φb is input from the flag unit 223, and the signal DATA21 (G8 ## when the high level selection signal φb is input from the flag unit 223. ) Is selected and output.

  The above signal switching means the following. When shooting with low sensitivity (low ISO, low gain), it means shooting at high brightness, and a signal G1 is obtained with a high amount of light (amount of light a or more), but the amount of light is greater than the amount of light b. Sometimes the signal DATA1 (G1) having a high signal-to-noise ratio is output without switching the signal. As a result, a signal having a wide dynamic range is obtained. In addition, when shooting is performed with high sensitivity (high ISO, high gain), it means shooting at low luminance, and when the light amount is b or less, the signal DATA21 (G8 having a high S / N ratio obtained by correcting the high gain signal G8). ##) is output. As a result, when the signal G8 is greater than or equal to the light amount b and less than or equal to the light amount a, it is possible to prevent an adverse effect caused by a signal in a saturated or nonlinear region in the column amplifier.

  The range of correction data allowed as correction data for different gains was examined experimentally. As a result, in terms of the amount of light b, when the signal level VH (b) of the signal G8 ## is increased by about 1% with respect to the signal level VL (b) of the signal G1, an image step starts to be noticeable, and the signal G8 # When the signal level VH (b) of # was small, the step started to be noticeable from about several percent. This seems to be tolerant to changes in brightness such that the image gradually becomes brighter at the joints of images as human visual characteristics, and to be more severe when the image becomes darker than changes that become brighter. Therefore, it is effective to further correct the correction coefficient K by, for example, 99%. Alternatively, this step can be made inconspicuous even if offset correction is performed instead of correction by the correction coefficient K. Since the correction using the offset voltage correction value is an addition / subtraction process, there is an advantage that the correction process is simplified.

  FIG. 4 is a diagram illustrating a configuration example of the bit switching unit 227. In FIG. 3, the case where the bit shift unit 221 shifts the signal DATA2 by 3 bits (1/8 times) has been described. In FIG. 4, the signal DATA21 is described as a signal input to the bit switching unit 227 after being shifted by 3 bits from the signal DATA1. The signals DATA1 and DATA21 have a 12-bit resolution. The output terminals Da0 to Da11 and Db0 to Db11 represent output terminals for the respective bits of the data DATA1 and DATA21, and the output terminals Dc0 to Dc14 represent the output terminals of the respective bits of the output signal DATA3 of the bit switching unit 227. Terminals Da8 to Da11 are connected to output terminals Dc11 to Dc14. The selection signal φb is a signal output from the switching flag unit 223. If the selection signal φb is at a low level, the switch connects the fixed data (for example, 0) node CNST and the terminals Da0 to Da8 to the output terminals Dc0 to Dc11. If the selection signal φb is at a high level, the switch connects the terminals Db0 to Db11 to the output terminals Dc0 to Dc11. Switching between the two input signals DATA1 and DATA21 is controlled by a selection signal φb from the switching flag unit 223. Since the signal DATA21 has a gain difference of 8 times that of the signal DATA1, the signal DATA1 is multiplied by 8 by a 3-bit shift. In this way, a 15-bit wide dynamic range signal DATA3 can be obtained from two 12-bit image signals DATA1 and DATA21. By detecting a gain error between different gains with high accuracy and performing gain correction, even if two images are combined, the step of the image can be hardly seen.

  Next, FIG. 5 shows a schematic configuration of the solid-state imaging device 1 according to the first embodiment of the present invention. The solid-state imaging device 1 includes a pixel unit 10 in which a plurality of pixels 101 are arranged in a matrix, a column amplification unit 102, a memory unit 103, and an output unit 104. The pixel 101 includes a photoelectric conversion element (photodiode) that generates a signal (charge) by photoelectric conversion, and selects a pixel output unit that converts the charge generated by the photoelectric conversion element into a voltage signal and outputs the voltage signal, or the pixel 101. For example, a pixel selection unit may be further included. For simplification of the figure, only four pixels 101 are shown, but it is assumed that there are actually pixels 101 of m rows × n columns. The column amplifier 102 is provided corresponding to each column of the plurality of pixels 101, and a first signal G1 and a second gain obtained by amplifying signals of the plurality of pixels 101 with a first gain (for example, gain of 1). A larger second gain (for example, a second signal G8 amplified by a gain of 8 times) is output. In this embodiment, the column amplification unit 102 includes two amplification units each having a different gain for each column. The gain can be set variably, and the memory unit 103 temporarily stores signals having different gains from the column amplification unit 102. The output unit 104 includes, for example, an output amplifier 1042, and solid-state imaging is performed via the output amplifier 1042. A signal is output to the outside of the element 1. Pixels 101 provided in the same column are connected to the column amplifier 102 via the same vertical signal line VL. The vertical signal line VL is a plurality of pixels 10. For each column, a plurality of pixels 101 are connected to the column amplifier 102. Even if there are a plurality of vertical signal lines VL for the columns, the gist of this embodiment does not change. When selected, a signal is output from the pixel 101 to the vertical signal line VL and amplified by the column amplifier 102. The amplified signal is held in the memory 103 and connects the memory 103 and the horizontal signal line HL. When the switch is controlled to be conducted by the horizontal scanning circuit 1041, the signal amplified by the column amplification unit 102 is output to the outside of the solid-state imaging device 1 via the output amplifier 1042. The timing generation unit 106 includes a vertical scanning circuit. 105 and the horizontal scanning circuit 1041 are supplied, and a signal for controlling the column amplification unit 102 and the memory unit 103 may be further supplied. 6 may be provided outside the solid-state imaging device 1.

  In the solid-state imaging device 1 shown in FIG. 5, the signal level output from the solid-state imaging device 1 with respect to the amount of light incident on the pixel 101 when the gain of the column amplification unit 102 is 1 and 8 times. Since the relationship with is described with reference to FIG. When the gain of the column amplification unit 102 is low, the noise of the output amplifier 1042 is larger than the noise from the pixel 101. In order to reduce the noise of the output, a high gain signal is formed, and after AD conversion, the original signal level is restored to improve the SN ratio.

  FIG. 6 shows a schematic circuit diagram of two column amplification units 102-1 and 102-2 in the column amplification unit 102 according to the first embodiment of the present invention. FIG. 6 shows one pixel extracted from a column of pixels. Two column amplification units 102-1 and 102-2 are provided for the vertical signal line VL. Here, it is assumed that the input capacitances C0 of the column amplification units 102-1 and 102-2 have the same capacitance value. The column amplifiers 102-1 and 102-2 differ in the magnitude of the feedback capacitance provided in the feedback path between the inverting input terminal and the output terminal of the operational amplifier Amp. Feedback capacitances C1 and C2 are connected to the column amplification unit 102-1, and feedback capacitances C3 and C4 are connected to the column amplification unit 102-2. Here, the capacitance values of the feedback capacitors C1, C2, C3, and C4 are assumed to be 1, 1/2, 1/8, and 1/16 times the capacitance value of the input capacitor C0, respectively. In other words, in the present embodiment, the column amplification unit 102 includes two column amplifiers 102-1 and 102-2 that can set different gains for each column. The column amplifier 102 amplifies and outputs the first signal G1 and the second signal S8 by different column amplifiers 102-1 and 102-2. As long as different gains can be set, the same gain may be set. The holding capacitors CTS1 and CTS2 are controlled by a signal φCTS, and the holding capacitors CTN1 and CTN2 are controlled by a signal φCTN.

  The operation according to this embodiment will be described with reference to FIG. FIG. 7 is a timing chart for obtaining a signal from the solid-state imaging device for pixels in a certain row among pixels arranged in a matrix. Here, a case is considered where the gain of the column amplifying unit 102-1 is 1 and the gain of the column amplifying unit 102-2 is 8 times.

  First, at time t0, signals other than the signals φTX and φHn transition to a high level. Since the pixel selection unit SEL becomes conductive when the signal φSEL becomes high level, the source terminal of the pixel output unit SF and the constant current source Iconst are electrically connected to form a source follower circuit. Accordingly, a level corresponding to the potential of the gate terminal of the pixel output unit SF appears on the vertical signal line VL as a signal. Since the signal φRES is at the high level at this timing, the reset unit RES is turned on, and a level corresponding to the state in which the gate terminal of the pixel output unit SF is reset appears as a signal on the vertical signal line VL. Further, since the signals φC, φC1, φC2, φC3, and φC4 are each set to a high level, the inverting input terminal and the output terminal of each operational amplifier Amp are short-circuited, and the feedback capacitors C1, C2, C3, and C4 are reset. The Due to the virtual grounding of the operational amplifier Amp, the potentials of both terminals of the feedback capacitors C1 and C3 can be regarded as the same potential as the power supply potential Vref. Since the signals φCTN and φCTS are at a high level, the holding capacitors CTN1, CTS1, CTN2, and CTS2 are reset by the output of the operational amplifier Amp.

  At time t1, the signal φRES transitions to a low level, the reset unit RES is turned off, and the reset state of the gate terminal of the pixel output unit SF is released. A noise component generated with the release of the reset state contributes to the pixel noise n.

  At time t2, signals φC1, φC2, φC3, φC4, φCTN, and φCTS transition to a low level, and the corresponding switches are turned off.

  At time t3, the signal φC transitions to a low level, so that the short circuit state between the input and output terminals of each operational amplifier is released. Thereby, in the input capacitor C0, the level corresponding to the reset of the gate terminal of the pixel output unit SF is clamped by the power supply potential Vref.

  At time t4, the signals φC1 and φCTN become high level, and at time t5, the signal φCTN becomes low level, so that the output of the column amplifying unit 102-1 at this time is stored in the storage capacitor CTN1, and the column amplifying unit 102-2. Is held in the holding capacitor CTN2. The signals held in the holding capacitors CTN1 and CTN2 include an offset component caused by the corresponding column amplification unit 102.

  When the signal φTX transitions to a high level at time t6, the charge accumulated in the photodiode PD is transferred to the gate terminal of the pixel output unit SF. As a result, the potential at the gate terminal of the pixel output unit SF changes, so that the level appearing on the vertical signal line VL also changes. At this time, since the input capacitor C0 is in a floating state, only the variation from the level of the vertical signal line VL clamped at time t1 is input to the inverting input terminal of each operational amplifier Amp. That is, a noise component generated before the clamp capacitor can be reduced by the clamp operation, and a signal based on photoelectric conversion is input to each operational amplifier Amp.

  From time t7, the signal φCTS becomes a high level in a pulse form. When the signal φCTS goes low, the switch is turned off, the signal output from the column amplifier 102-1 is output to the storage capacitor CTS1, and the signal output from the column amplifier 102-2 is output to the storage capacitor CTS2. Retained. The signals held in the holding capacitors CTS1 and CTS2 include an offset component caused by the corresponding column amplification unit 102, similarly to the holding capacitors CTN1 and CTN2.

  Thereafter, after the signals φC1 and φC3 transition to the low level, the signal φSEL becomes the low level at time t8, so that the pixel selection unit SEL becomes non-conductive and the selection state of the pixel 101 is released.

  Since the signal φHn is sequentially set to the high level from time t9, the signal from the pixels 101 for one row is changed to the differential amplifier D.D. Amp1 and D.I. It is output via Amp2. Differential amplifier Amp1 subtracts the offset signal of the storage capacitor CTN1 from the pixel signal of the storage capacitor CTS1, and outputs a pixel signal S1 from which the offset has been removed. Further, the differential amplifier D.I. Amp2 subtracts the offset signal of the storage capacitor CTN2 from the pixel signal of the storage capacitor CTS2, and outputs a pixel signal S2 with a reduced offset. Since the signals held in the holding capacitors CTS1, CTS2, CTN1, and CTN2 include an offset caused by the column amplifier 102, the differential amplifier D.D. Amp1 and D.I. The offset component can be reduced by taking the difference by Amp2. Here, the differential amplifier D.D. A signal S1 amplified by a gain of 1 from Amp1 is supplied to a differential amplifier D.D. Amp2 outputs a signal S2 amplified with a gain of 8 times. The signals S1 and S2 include the output noise N described above.

  In the present embodiment, since the column amplifier 102 is provided in each column, it is possible to perform processing in parallel for pixels for one row. In other words, since it can be driven at a lower speed than the output amplifier 1042, there is an advantage that it is difficult to generate noise.

  According to the present embodiment, the dynamic range of the solid-state imaging device 1 can be expanded and the S / N ratio of the solid-state imaging device can be improved. Furthermore, a suitable image can be obtained by performing processing for multiplying the γ value according to the gain of the column amplification unit 102 by the DSP 23. In particular, according to the present embodiment, since a plurality of column amplifiers 102-1 and 102-2 having different gains are provided for the vertical signal line VL, there is an advantage that processing can be performed in parallel. That is, it is suitable for speeding up.

  In the solid-state imaging device 1 according to the first embodiment of the present invention, an embodiment in which one column amplifier 102 is provided for one pixel 101 in FIG. 5 will be described with reference to FIG. FIG. 8 is a schematic circuit diagram of one column amplification unit 102 according to this embodiment. The pixel 101 includes a photodiode PD that is a photoelectric conversion element and a transfer unit TX that transfers charges accumulated in the photodiode PD to a gate terminal of a MOS transistor that forms the pixel output unit SF. A gate terminal that is an input unit of the pixel output unit SF is connected to the power supply VDD via the reset unit RES. Further, the source terminal of the pixel output unit SF is connected to one terminal of the input capacitor C0 of the column amplification unit 102 via the pixel selection unit SEL, and is also connected to the constant current source Iconst.

  The column amplification unit 102 includes an operational amplifier Amp. The inverting input terminal of the operational amplifier Amp is connected to the other terminal of the input capacitor C0. The inverting input terminal and the output terminal of the operational amplifier Amp are provided so that feedback capacitors C1, C2, and C3 are respectively connected via switches. Further, a switch for short-circuiting the inverting input terminal and the output terminal of the operational amplifier Amp is provided. A power supply potential Vref is applied to a non-inverting input terminal of the operational amplifier Amp. The signal output from the pixel 101 to the vertical signal line VL is determined by the ratio between the capacitance values of the feedback capacitors C1, C2, and C3 connected to the feedback path of the operational amplifier Amp and the capacitance value of the input capacitor C0. Gain is applied and amplified. Here, the capacitance values of the feedback capacitors C1, C2, and C3 are set to 1 times, 1/8 times, and 1/16 times the capacitance value of the input capacitor C0, respectively. That is, in this embodiment, the column amplifier 102 having a variable gain is provided. As will be described later, noise caused by the pixel 101 is reduced by the input capacitor C0. Here, the first CDS circuit includes the input capacitor C0, the operational amplifier Amp, and the switch to which the signal φC is input.

  The signals amplified by the column amplifier 102 are selectively transmitted to and held in the holding capacitors CTS1, CTN1, CTS2, and CTN2. The holding capacitors CTS1 and CTS2 hold a signal based on charges obtained by photoelectric conversion by the photodiode PD, and the holding capacitors CTN1 and CTN2 hold a signal based on resetting the pixel output unit SF. The The holding capacitors CTS1, CTN1, CTS2, and CTN2 are connected to different horizontal signal lines HL1 to HL4, respectively. The signals held in the holding capacitors CTS1 and CTN1 are respectively transferred to the differential amplifiers D.D. Connected to different input terminals of Amp1. The signals held in the holding capacitors CTS2 and CTN2 are respectively sent to the differential amplifier D.P. Connected to different input terminals of Amp2. When signals .phi.H1, .phi.H2,... Are input from the horizontal scanning circuit 1041, the signals held in the holding capacitors CTS1, CTN1, CTS2, and CTN2 are transferred to the corresponding differential amplifiers D.H. Amp1 and D.I. Input to Amp2. Differential amplifier From Amp1, the difference between the signals held by the holding capacitors CTS1 and CTN1 is output. Differential amplifier From Amp2, the difference between the signals held in the holding capacitors CTS2 and CTN2 is output. Here, the holding capacitors CTS1, CTN1, CTS2, and CTN2 and the differential amplifier D.D. Amp1, D. A second CDS circuit including Amp2 is assumed. The offset caused by the column amplification unit 102 is reduced by the second CDS circuit.

  The operation according to the present embodiment will be described with reference to FIG. 9 and the schematic timing chart of the embodiment of FIG. Here, the feedback capacitors C1 and C2 are used, and the respective capacitance values are assumed to be 1 and 1/8 times the capacitance value of the input capacitor C0. That is, a case where one signal is amplified with a gain of 1 and 8 will be described. In FIG. 8, signals input to the switches indicated by TX, RES, and SEL are represented by φTX, φRES, and φSEL, respectively, and the switch conducts when the signal is at a high level. Further, signals given to the switches existing between the feedback capacitors C1, C2, and C3 and the inverting input terminal of the operational amplifier Amp are represented as φC1, φC2, and φC3, respectively, and the switches are turned on when the signals are at a high level. To do. Signals applied to the switches between the holding capacitors CTS1, CTN1, CTS2, and CTN2 and the output terminal of the column amplifier 102 are represented as φCTS1, φCTN1, φCTS2, and φCTN2, respectively, and the switches are turned on when the signals are at a high level. Shall.

  First, at time t0, signals other than the signals φTX and φHn transition to a high level. Since the pixel selection unit SEL becomes conductive when the signal φSEL becomes high level, the source terminal of the pixel output unit SF and the constant current source Iconst are electrically connected to form a source follower circuit. Accordingly, a level corresponding to the potential of the gate terminal of the pixel output unit SF appears on the vertical signal line VL as a signal. Since the signal φRES is at the high level at this timing, the reset unit RES is turned on, and a level corresponding to the state in which the gate terminal of the pixel output unit SF is reset appears on the vertical signal line VL. Further, when the signals φC, φC1, φC2, and φC3 are respectively set to the high level, the inverting input terminal and the output terminal of the operational amplifier Amp are short-circuited, and the feedback capacitors C1, C2, and C3 are reset. Due to the virtual grounding of the operational amplifier Amp, the potentials of both terminals of the feedback capacitors C1 and C2 can be regarded as the same potential as the power supply potential Vref. Since the signals φCTN1, φCTS1, φCTN2, and φCTS2 are at a high level, the corresponding switches are turned on, and the holding capacitors CTN1, CTS1, CTN2, and CTS2 are reset by the output of the operational amplifier Amp.

  At time t1, the signal φRES transitions to a low level, the reset unit RES is turned off, and the reset state of the gate terminal of the pixel output unit SF is released. A noise component generated with the cancellation of the reset state contributes to the pixel noise n.

  At time t2, the signals φC1, φC2, φC3, φCTN1, φCTS1, φCTN2, and φCTS2 become low level, and the corresponding switches are turned off.

  Thereafter, at time t3, the signal φC transitions to a low level, so that the short-circuit state of the input / output terminals of the operational amplifier is released. In the input capacitor C0, the level corresponding to the reset of the gate terminal of the pixel output unit SF is clamped by the power supply potential Vref.

  At time t4, the signals φC1 and φCTN1 become high level, and at time t5, the signal φCTN1 becomes low level, so that the output of the column amplifier 102 at this time is held in the holding capacitor CTN1. Here, since the signal φC1 is at a high level, only the feedback capacitor C1 is electrically connected to the period path of the operational amplifier Amp. That is, the gain of the column amplification unit 102 is C0 / C1 = C0 / C0 = 1. The signal held in the holding capacitor CTN1 includes an offset component caused by the column amplification unit 102.

  At time t6, the signal φC1 changes to low level, and at time t7, the signal φC2 changes to high level, so that only the feedback capacitor C2 is electrically connected to the feedback path of the operational amplifier Amp. That is, the gain of the column amplification unit 102 is C0 / C2 = C0 / (C0 / 8) = 8.

  When the signal φCTN2 becomes a high level in a pulse shape from time t7 and the signal φCTN2 becomes a low level, a signal including an offset component caused by the column amplification unit 102 is held in the holding capacitor CTN2.

  When the signal φTX transits to a high level at time t8, the charge accumulated in the photodiode PD is transferred to the gate terminal of the pixel output unit SF. As a result, the potential at the gate terminal of the pixel output unit SF changes, so that the level appearing on the vertical signal line VL also changes. At this time, since the input capacitor C0 is in a floating state, only the change in potential from the level of the vertical signal line VL clamped at time t1 is input to the inverting input terminal of the operational amplifier Amp. That is, among the noise components generated before the clamp capacitance, the noise components correlated with the level of the vertical signal line VL at time t3 and the level at the timing after time t8 can be reduced by the clamping operation. it can. As a result, a signal based on photoelectric conversion is input to the operational amplifier Amp. However, fluctuations in the current flowing through the constant current source Iconst, noise called 1 / f noise generated in the pixel output unit SF, and the like are different at time t1 and time t8 (no correlation), and are reduced by the clamping operation. I can't. In the present embodiment, such a non-correlated noise component corresponds to the pixel noise n.

  At time t8, only the feedback capacitor C2 having a capacitance value that is 1/8 times the capacitance value of the input capacitor C0 is present in the feedback path of the operational amplifier Amp, so that a signal based on photoelectric conversion is amplified with a gain of 8 times. become. The signal φCTS2 is at a high level in a pulse shape from time t8, and the signal amplified eight times by the column amplifier 102 is held in the holding capacitor CTS2 when the signal φCTS2 transitions to a low level. The signal held in the holding capacitor CTS2 includes an offset caused by the column amplification unit 102, similarly to the holding capacitor CTN2.

  At time t9, the signal φC2 changes to low level, and at time t10, the signal φC1 changes to high level, so that only the feedback capacitor C1 is electrically connected to the feedback path of the operational amplifier Amp. Since the capacitance value of the feedback capacitor C1 is the same as the capacitance value of the input capacitor C0, the signal input to the column amplifier 102 is amplified with a gain of 1.

  When the signal φCTS1 changes to the high level from time t10 and changes to the low level, a signal obtained by amplifying the level appearing on the vertical signal line VL with a gain of 1 is held in the holding capacitor CTS1. Here, the signal held in the storage capacitor CTS1 includes an offset caused by the column amplification unit 102 as in the case of the storage capacitor CTN1.

  Thereafter, when the signal φSEL becomes a low level, the pixel selection unit SEL is turned off, and the selection state of the pixel 101 is released.

  Since the signal φHn is sequentially set to the high level from time t11, the signals from the pixels 101 for one row are sequentially converted to the differential amplifier D.D. Amp1 and D.I. It is output via Amp2. Since the signals held in the holding capacitors CTS1, CTN1, CTS2, and CTN2 include an offset caused by the column amplifier 102, the differential amplifier D.D. Amp1 and D.I. The offset component can be reduced by taking the difference by Amp2. Here, the differential amplifier D.D. A signal S1 amplified by a gain of 1 from Amp1 is supplied to a differential amplifier D.D. Amp2 outputs a signal S2 amplified with a gain of 8 times. The signals S1 and S2 include the output noise N described above.

  The column amplifier 102 sequentially amplifies and outputs the first signal G1 and the second signal G8 by the same column amplifier. In the present embodiment, since the column amplifying unit 102 is provided in each column, it is possible to perform processing in parallel for the pixels 101 for one row. In other words, since it can be driven at a lower speed than the output amplifier 1042, there is an advantage that it is difficult to generate noise.

  Next, an operation as a solid-state imaging device will be described for the first embodiment of the present invention. FIG. 10 is an explanatory diagram of imaging timing of the solid-state imaging device according to the first embodiment. First, a process for generating a correction coefficient K by imaging a subject for forming a gain error correction signal will be described. In the period T1, exposure is performed, in the period T2, a reset signal of the pixel 101 is read, and the reset signal is clamped at the input unit of the column amplifier 102. Next, in a period T3, the exposure signal of the pixel 101 is read, and the CDS operation of the CDS circuit is finished. The signal is output outside the solid-state imaging device 1. In the period T4, the AD conversion unit 21 converts from analog to digital. With the signal processing described in FIG. 3, the comparison unit 224 compares the two signal levels in the period T5, the comparison unit 224 generates the correction coefficient K based on the gain error ΔV in the period T6, and the comparison unit 224 in the period T7. The correction coefficient K is stored in the correction data memory unit 225. With the same operation, the correction coefficient K between the gains is held in the camera.

  Next, processing during imaging will be described. From the period T1 to T4, the same operation as the generation of the correction coefficient K is performed. Thereafter, in period T8, the correction unit 226 corrects DATA2 using the stored correction coefficient. In period T9, switching between DATA1 and DATA2 is performed by the bit switching flag φb, and a 15-bit digital signal DATA3 is output. As described above, the pixel signals are sequentially read from the pixel unit 10 of the solid-state imaging device 1, and the correction unit 226 corrects the gain error based on the correction coefficient K and performs bit switching (periods T2 to T4, T8, T9) Obtain image data. In the period T10, the DSP 23 performs signal processing of the corrected signal DATA3 and records it in the recording unit 3. A wide dynamic signal in which the image level difference is difficult to see at such an imaging timing is recorded.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the first embodiment, a subject for correction signal formation is imaged and a gain error is detected. Further, the column amplifying unit 102 or the memory unit 103 has offset noise or gain error that becomes a fixed pattern due to variations in the semiconductor process, and degrades the image performance. The second embodiment of the present invention is intended to eliminate the noise and subject shooting for forming a correction signal by inputting a reference signal to the vertical signal line VL. Hereinafter, the points of the present embodiment different from the first embodiment will be described.

  FIG. 11 shows a schematic configuration of a solid-state imaging device 1 having a reference signal input circuit (reference signal input unit) 107 according to the second embodiment of the present invention. The column amplification unit 102 includes column amplification units 102-1 and 102-2. The vertical signal line VL is connected to the reference signal line 1072 of the reference signal input circuit 107 through a switch controlled by the pulse φS2. The reference signal input circuit 107 controls the switch controlled by the pulse φS1 at the same time as turning on the switch controlled by the pulse φS2 before imaging (or when the imaging power is turned on). As a result, a reference signal having an amplitude corresponding to the imaging sensitivity is input to detect a gain error or offset noise of the signal processing system at the subsequent stage. The reference signal input circuit 107 has a signal source 1071 composed of two power supply voltages Vs1 and Vs2, and selectively outputs the reference signal voltages Vs1 and Vs2 to the vertical signal line VL. The power supply voltage Vs2 is variably controlled. The signal source 1071 controls the conduction / non-passage of the switch with the pulse φS1, so that the signal Vs1-Vs2 is generated in the vertical signal line VL in the reference signal line 1072. The signal of Vs1-Vs2 is set so as to have a signal level equal to or lower than the signal level VH (b) when the column amplification unit 102 makes the gain high.

  Vs1 is a potential corresponding to the reset level of the pixel 101, and Vs2 is a potential corresponding to the exposure signal of the pixel 101. Then, the CDS process described in FIGS. 6 and 8 and the gain process of the column amplifier 102 can be performed to detect gain errors of different gains. If the power supply Vs2 is configured by a digital-analog (DA) converter, the signal level can be easily changed according to each gain of the column amplifier 102. When the gain of the column amplifier 102 is increased, it is necessary to make it very small so that the reference signal level is not saturated, but the DA converter can easily generate the potential. As described above, since the gain error can be detected by the reference signal input circuit 107 having a very simple configuration, the gain error detection before imaging is very effective.

  The imaging timing of the solid-state imaging device according to this embodiment will be described with reference to FIG. First, a process for generating the correction coefficient K will be described. In the period T1, the solid-state imaging device is turned on (turned on). Then, in the period T2, the reference signal input circuit 107 outputs the reference signal voltage Vs1 corresponding to the reset signal of the pixel 101 to the vertical signal line VL. Next, in the period T3, the reference signal input circuit 107 outputs the reference signal voltage Vs2 corresponding to the exposure signal of the pixel 101 to the vertical signal line VL. As a result, the column amplifier 102 amplifies the Vs1-Vs2 reference signal with the first gain and the second gain, and outputs the first signal G1 and the second signal G8. Next, in the period T4, the AD conversion unit 21 converts the first signal G1 and the second signal G8 from analog to digital. By the signal processing of FIG. 3, in the period T5, the comparison unit 224 compares two signal levels, in the period T6, the comparison unit 224 generates a correction coefficient K based on the gain error ΔV, and in the period T7, the comparison unit 224 The correction coefficient K for each gain error is stored in the correction data memory unit 225. As described above, when the power is turned on, the column amplifier 102 outputs the first signal G1 and the second signal G8 obtained by amplifying the reference signals Vs1-Vs2, and the comparator 224 outputs the third signal. A gain error ΔV between G8 # and the first signal G1 is detected, and a correction coefficient K is generated.

  Next, processing during imaging will be described. For example, when the imaging system is produced at a production site such as a factory or when the correction coefficient at the time of initial setting of the imaging system is acquired, the same operation as the imaging timing already described in FIG. 10 is performed. On the other hand, when the correction coefficient is updated every time imaging is performed, the correction coefficient is calculated and held in the memory before the start of exposure in the period T1 immediately after the power of the imaging system is turned on. The operation is performed at the same timing as in FIG.

  As described above, the plurality of pixels 101 are arranged in a matrix and generate signals by photoelectric conversion. The reference signal input circuit 107 generates reference signals Vs1-Vs2. The column amplifying unit 102 is provided in each column of the plurality of pixels 101, and the first signal G1 obtained by amplifying the signals of the plurality of pixels 101 or the reference signals Vs1-Vs2 with the first gain and the first gain larger than the first gain. A second signal G8 amplified with a gain of 2 is output. The AD conversion unit 21 converts the first signal G1 and the second signal G8 from analog to digital. When the column amplification unit 102 outputs the first signal G1 and the second signal G8 obtained by amplifying the reference signals Vs1 to Vs2, the comparison unit 224 sets the second signal G8 to the same gain level as the first signal G1. A gain error ΔV between the level-shifted third signal G8 # and the first signal G1 is detected. The correction unit 226 outputs the first signal G1 and the second signal G2 based on the gain error ΔV when the column amplification unit 102 outputs the first signal G1 and the second signal G8 obtained by amplifying the signals of the plurality of pixels 101. The signal G8 or the third signal G8 # is corrected.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 12 is a diagram showing a schematic configuration of a pixel 101 having a reference signal input circuit according to the third embodiment of the present invention. In the second embodiment (FIG. 11), a gain error or the like of the column amplifier 102 is detected using the reference signal from the reference signal input circuit 107. In this embodiment, the pixel 101 has a reference signal input circuit that outputs a reference signal. Hereinafter, the points of the present embodiment different from the second embodiment will be described. In response to the signal φS1, the switch connects the reset switch RES to the node of the power supply potential VDD or the reference potential Vs2. When resetting, the reset switch RES is connected to the node of the power supply potential VDD, and the gate terminal of the pixel output unit SF is reset with the power supply potential VDD. On the other hand, at the time of reading the reference signal, not the charge due to the exposure of the photodiode PD but the reset switch RES is connected to the node of the reference potential Vs2, the reference potential Vs2 is supplied to the gate terminal of the pixel output unit SF, and the vertical signal line A reference potential is output to VL. The power source for the reference potential Vs2 may be a DA converter. By inputting the reference signal from the pixel unit 10 in this way, it is possible to detect errors in the column amplification unit 102, the AD conversion unit 21 and the like, and to correct these errors, thereby obtaining a high-quality image.

  As described above, the pixel 101 includes the photodiode (photoelectric conversion element) PD, the transfer switch TX, and the field effect transistor SF. The photodiode PD generates a signal by photoelectric conversion. The transfer switch TX is connected to the photoelectric conversion element PD. The field effect transistor SF has a gate connected to the photodiode PD via the transfer switch TX, a drain connected to the node of the power supply potential VDD, and a source that outputs a signal to the column amplification unit 102 via the pixel selection unit SEL. . The reference signal input circuit has a power supply of the reference potential Vs2 and a switch of the control signal φS1, and selectively outputs the reference signals Vs2 and VDD to the gate of the field effect transistor SF. Supplying the reference signal VDD to the gate of the field effect transistor SF corresponds to supplying the reference signal voltage Vs1 of the second embodiment. Supplying the reference signal Vs2 to the gate of the field effect transistor SF corresponds to supplying the reference signal voltage Vs2 of the second embodiment. The operation of this embodiment is the same as that of the second embodiment.

(Fourth embodiment)
FIG. 13 is a diagram showing a schematic configuration of a solid-state imaging device 1 according to the fourth embodiment of the present invention. In the present embodiment, an AD converter 108 and the reference signal input circuit 107 of the embodiment of FIG. 11 are provided after the column amplifier 102 in the first embodiment of FIG. Hereinafter, the points of the present embodiment different from the second embodiment will be described. In the AD conversion unit 108, each amplification unit of the column amplification unit 102 converts the output signal from analog to digital. The AD conversion unit 108 converts the first signal G1 and the second signal G8 from analog to digital by different AD conversion units. Since the AD conversion unit 108 is provided for each of the two gain signals from the column amplification unit 102 in the solid-state imaging device 1, high-speed processing is possible. The bit processing unit 22 (FIG. 2) in the fourth embodiment uses the bit processing unit 22 of the embodiment of FIG. When the gain error is detected, the gain of the column amplifying unit 102 is set by the sensitivity setting at the time of photographing, and the reference signal level is set and inputted according to the gain, so the comparison level determining unit 222 (FIG. 3) It becomes unnecessary. At that time, the timing generator (TG) 24 controls the comparator 224. During actual imaging, the timing generation unit 24 operates as the comparison level determination unit 222 with respect to the signal DATA2 (G8). Even if the AD conversion unit 108 having a somewhat large gain error is configured in the solid-state imaging device 1, the signal errors of the column amplification unit 102 and the AD conversion unit 108 can be accurately detected and corrected by the reference signal input.

  FIG. 14 is an explanatory diagram of imaging timing of the solid-state imaging device according to the present embodiment. Hereinafter, a point in which the method for generating the correction coefficient K of the present embodiment is different from that of the second embodiment will be described. In the period T4, the AD conversion unit 108 converts the first signal G1 and the second signal G8 from analog to digital. By the signal processing of FIG. 3, in the period T5, the comparison unit 224 compares two signal levels, in the period T6, the comparison unit 224 generates a correction coefficient K based on the gain error ΔV, and in the period T7, the comparison unit 224 The correction coefficient K for each gain error is stored in the correction data memory unit 225. The timing at the time of imaging is the same as in the second embodiment.

(Fifth embodiment)
FIG. 15 is a diagram showing a schematic configuration of a solid-state imaging device 1 according to the fifth embodiment of the present invention. The present embodiment is characterized in that one AD conversion unit 108 is provided for each pixel column with respect to the fourth embodiment (FIG. 13). Hereinafter, differences of this embodiment from the fourth embodiment will be described. The column amplifying unit 102 includes a column amplifying unit 102-1 that outputs a first signal G1 having a low gain and a column amplifying unit 102-2 that outputs a second signal G8 having a high gain. -1 and 102-2 amplify and output the first signal G1 and the second signal G8. The signal selection unit 109 selects either the low gain first signal G1 or the high gain second signal G8 by switch control. The AD conversion unit 108 converts one of the first signal G1 and the second signal G8 selected by the signal selection unit 109 from analog to digital. The signal selection unit 109 selects the second signal G8 when the second signal G8 is equal to or lower than the first signal level VH (b), and the second signal G8 is based on the first signal level VH (b). When it is larger, the first signal G1 is selected. The AD converter 108 sequentially converts the first signal G1 or the second signal G8 from analog to digital by the same AD converter. Then, the signal selection unit 109 transfers the same selection signal φb as in FIG. 3 to the horizontal signal line HLB in parallel with the previous digital signal via the AD conversion unit 108. The selection signal φb is a signal indicating which one of the first signal G1 and the second signal G8 is selected. Like the first embodiment, the selection signal φb is at a low level when the first signal G1 is selected. Yes, it is high when the second signal G8 is selected. The bit switching unit 227 is provided on the horizontal signal line HLB. From the AD conversion unit 108 and the signal selection unit 109, either the first signal G1 or the second signal G8 is transferred to the horizontal signal line HLB together with the selection signal φb according to the pixel signal level for each column, The data is output to the switching unit 227. The bit switching unit 227 has the same configuration as in FIG. 4 and performs the same operation. That is, the bit switching unit 227 selects the second signal G8 and outputs a high gain signal when the selection signal φb is at a high level, and outputs the first signal G1 with a low gain when the selection signal φb is at a low level. Output as a signal. The solid-state imaging device 1 outputs the selection signal φb together with the low gain signal or the high gain signal. The selection signal φb may be transferred in parallel with the first signal G1 or the second signal, or may be transferred serially. In the output data of the bit switching unit 227, a gain error ΔV is detected and corrected by a bit processing unit 22-1 (FIG. 16) described later.

  As shown in FIG. 8, the column amplification unit 102 may sequentially amplify and output the first signal G1 and the second signal G8 by the same column amplification unit. In that case, the column amplifying unit 102 outputs the second signal G8 previously amplified with high gain, and then outputs the first signal G1 amplified later with low gain. Thereby, the signal selection unit 109 selects a signal to be AD converted by determining the signal level of the second signal G8. Since the signal level is determined using the second signal amplified with high gain, the accuracy requirement for the circuit that determines the signal level is not necessarily high.

  In this embodiment, since the number of AD conversion units in the AD conversion unit 108 is halved, the size of the solid-state imaging device 1 is reduced, power consumption is reduced, and the number of data from the AD conversion unit 108 is also halved. As a result, the number of terminals of the package of the solid-state imaging device 1 can be reduced. Therefore, it is advantageous in terms of cost.

  FIG. 16 is a diagram illustrating a schematic configuration of a bit processing unit 22-1 according to the fifth embodiment of the present invention. The bit processing unit 22-1 is provided in place of the AD conversion unit 21 and the bit processing unit 22 in FIG. 2 and inputs an output signal of the solid-state imaging device 1. Hereinafter, differences between the bit processing unit 22-1 and the bit processing unit 22 of FIG. 3 will be described.

  First, the correction coefficient K generation process will be described. When the power of the solid-state imaging device is turned on, the reference signal input circuit 107 outputs the reference signal to the vertical signal line VL. Then, the signal selection unit 109 sequentially selects the first signal G1 and the second signal G8 regardless of the signal level of the second signal G8. The selection signal φb is at a low level when the first signal G1 is selected, and is at a high level when the second signal G8 is selected. The bit switching unit 227 sequentially outputs a low gain signal and a high gain signal. The data synchronization unit 228 sequentially inputs a low gain signal and a high gain signal and outputs signals DATA1 and DATA2 in parallel. The signal DATA1 is a low gain signal output from the bit switching unit 227, and the signal DATA2 is a high gain signal output from the bit switching unit 227. The comparison unit 224 compares the signals DATA1 and DATA2, detects the gain error ΔV, and stores the reciprocal of the gain error ΔV in the correction data memory unit 225 as the gain error correction coefficient K. That is, the comparison unit 224 detects a gain error ΔV between the first signal G1 and the second signal G8 when the first signal G1 and the second signal G8 are level-shifted to the same gain level. When generating the correction coefficient K, the correction coefficient for the entire column amplifier can be obtained if there are at least two signals of the first and second signals. Further, by calculating a plurality of correction coefficients and averaging them, a more accurate correction coefficient can be obtained.

  Next, processing during imaging will be described. When the correction coefficient is generated when the camera is initialized and stored, an exposure signal is output from the pixel 101 to the vertical signal line VL. Then, the first signal G1 and the second signal G8 amplified by the column amplifier 102 are AD-converted by the AD converter 108, and then sequentially output from the solid-state imaging device 1. Digital signals output from the solid-state imaging device 1 are sequentially input to the bit processing unit 22-1. Then, when the selection signal φb input from the solid-state imaging device 1 is at the high level, the correction unit 226 corrects the correction data memory unit 225 for the lower 12 bits of the data of the input high gain signal as in FIG. Correction is performed by multiplying the coefficient K, and the signal DATA3 is output. Further, when the selection signal φb is at a low level, the correction unit 226 outputs the input low gain signal as it is as the signal DATA3.

  Note that the correction unit 226 may correct the low gain signal, the first signal G1, or the second signal G8 instead of correcting the high gain signal. The bit processing unit 22-1 in FIG. 16 may be provided in the solid-state imaging device 1 in FIG. In this case, circuit design is performed using the bit switching unit 227 as the bit processing unit 22-1.

  According to the present embodiment, the number of column amplifying units 102 can be reduced as compared with the case where the column amplifying units 102 that amplify the first signal G1 and the second signal G8 are separately provided. can do. In addition, since the first signal G1 or the second signal G8 is selected and converted from analog to digital, compared to the case where both the first signal G1 and the second signal G2 are converted from analog to digital, The operation speed can be improved.

(Sixth embodiment)
FIG. 17 is a diagram showing a schematic configuration of a solid-state imaging device 1 according to the sixth embodiment of the present invention. This embodiment is an embodiment in which the bit processing unit 22 of FIG. 3 is provided in the solid-state imaging device 1 with respect to the fourth embodiment of FIG. The bit processing unit 22 is provided on the horizontal signal line HLB. By providing the bit processing unit 22 in the solid-state image pickup device 1, the solid-state image pickup device 1 outputs only a 15-bit wide dynamic range signal that has been AD converted, so the external processing circuit unit is only the DSP 23 (FIG. 2). Therefore, it is possible to reduce the size and cost of the solid-state imaging device. The imaging timing of the solid-state imaging device according to this embodiment is substantially the same as that of the fourth embodiment in FIG.

  According to the first to sixth embodiments, it is possible to reduce the gain error of the column amplification unit 102 and / or the conversion error of the AD conversion units 21 and 108 when signals amplified with different gains are obtained.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

101 pixels, 102-1, 102-2 column amplifying unit, 103 memory unit, 104 output unit, 107 reference signal input circuit

Claims (7)

A plurality of pixels arranged in a matrix and generating signals by photoelectric conversion;
A reference signal input unit for generating a reference signal;
A first signal obtained by amplifying a signal of the plurality of pixels or the reference signal with a first gain and a second gain larger than the first gain provided in each column of the plurality of pixels; A column amplifier that outputs the signal of
An analog-to-digital converter that converts the first signal into a first digital signal and converts the second signal into a second digital signal;
A solid-state imaging device comprising: a correction unit that performs correction processing so that a gain error between the first digital signal and the second digital signal after the same gain level is reduced. In addition, for each column of the plurality of pixels, a signal line that connects the plurality of pixels and the column amplification unit,
The solid-state imaging device according to claim 1, wherein the reference signal input unit selectively outputs the reference signal to the signal line. The pixel is
A photoelectric conversion element that generates a signal by photoelectric conversion;
A transfer switch connected to the photoelectric conversion element;
A field effect transistor having a gate connected to the photoelectric conversion element via the transfer switch, a drain connected to a power supply potential node, and a source outputting a signal to the column amplifier;
The solid-state imaging device according to claim 1, wherein the reference signal input unit selectively outputs the reference signal to a gate of the field effect transistor.   4. The device according to claim 1, wherein when the power is turned on, the column amplifier outputs the first signal and the second signal obtained by amplifying the reference signal. 5. Solid-state imaging device.   Furthermore, it has a bit switching part which selects the signal correct | amended by the said correction | amendment part, or the said 1st signal which is not correct | amended by the said correction | amendment part, or the said 2nd signal. The solid-state imaging device according to any one of the above.   The bit switching unit selects the signal corrected by the correction unit when the second signal is less than or equal to the first signal level, and the bit switching unit selects the first signal when the second signal is greater than the first signal level. 6. The solid-state imaging device according to claim 5, wherein one signal is selected. A plurality of pixels arranged in a matrix and generating signals by photoelectric conversion;
A reference signal input unit for generating a reference signal;
A column amplifier provided in each column of the plurality of pixels;
A method for driving a solid-state imaging device having an analog-digital converter,
Causing the column amplification unit to output a first signal obtained by amplifying the plurality of pixel signals or the reference signal with a first gain and a second signal obtained by amplifying with a second gain greater than the first gain; ,
The analog-to-digital conversion unit converts the first signal into a first digital signal, and converts the second signal into a second digital signal,
A method for driving a solid-state imaging device, wherein correction processing is performed so that a gain error between the first digital signal and the second digital signal after the same gain level is reduced.

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