JP6370413B2 - Imaging apparatus, imaging system, and driving method of imaging apparatus - Google Patents

Description

The present invention relates to an imaging apparatus , an imaging system, and a driving method of the imaging apparatus .

  In recent years, some digital cameras using a CMOS image sensor as an image sensor read out the pixel signal at high speed by performing analog-digital (AD) conversion of the pixel signal in the image sensor. As one of the AD conversion techniques, a method is known in which a pixel signal is compared with a reference signal (ramp signal) that changes with time by a comparator to acquire AD conversion data corresponding to the signal amplitude. As described above, an image pickup device including an AD converter is expected to have higher-speed reading and higher resolution.

  Considering the optical shot noise of the pixel signal, it is sufficient if the number of bits is sufficient to ensure the S / N ratio, and when divided into a plurality of signal levels, the number of bits is reduced to increase the speed of reading and increase the speed. It is possible to reduce the resolution. Further, a method of combining a plurality of comparators and a plurality of reference signals according to signal amplitude is known (see, for example, Patent Document 1).

JP 2007-281987 A

  Since the technique of Patent Document 1 uses a plurality of comparators, there is a problem in that the response speed varies depending on the manufacturing variation of elements constituting the comparators and an error occurs in AD conversion data. In addition, there is a problem that the circuit area and power consumption increase.

An object of the present invention is to provide an imaging apparatus , an imaging system, and an imaging apparatus driving method capable of generating a digital signal of a signal based on a high-resolution photoelectric conversion unit .

Imaging apparatus of the present invention includes a photoelectric conversion unit that generates an electric charge based on the photoelectric conversion, and the analog-to-digital converting unit, and an arithmetic unit, wherein the analog-to-digital conversion unit is a noise signal and a first change rate first by performing a comparison of the outputs a first comparison result signal, the signal to be larger than the first change rate based on the charge is compared with the ramp signal potential changes over time a comparator circuit potential at the second change rate is the second comparison result signal by performing a second comparison is a comparison of the ramp signal which varies with time, the analog-to-digital The conversion unit generates a first digital signal based on the noise signal using the first comparison result signal, and the analog-to-digital conversion unit converts the charge into the charge using the second comparison result signal. Based on signal based It generates a second digital signal, the arithmetic unit so as to reduce the difference in resolution of the first digital signal and said second digital signal, by the second digital signal to a bit shift or operation A third digital signal is generated, and the arithmetic unit generates a difference signal between the first digital signal and the third digital signal.

A digital signal based on a high- resolution photoelectric conversion unit can be obtained.

It is a block diagram of the image pick-up element by the 1st Embodiment of this invention. It is explanatory drawing of the S / N ratio of a pixel signal. It is explanatory drawing of a some ramp signal. It is a block diagram of the AD conversion part of the 1st Embodiment of this invention. FIG. 5 is a timing chart of the AD conversion unit in FIG. 4. It is explanatory drawing of the bit shift part of AD conversion data. It is a block diagram of the AD conversion part by the 2nd Embodiment of this invention. It is a block diagram of the AD conversion part by the 3rd Embodiment of this invention. It is a block diagram of the bit number adjustment part of AD conversion data. It is a block diagram of an imaging system. It is a conceptual diagram which shows the structural example of the image pick-up element of FIG. It is an equivalent circuit diagram of a pixel. FIG. 12 is a timing diagram illustrating an operation example of the image sensor illustrated in FIG. 11.

(First embodiment)
FIG. 1 is a schematic configuration diagram of an image sensor 100 according to the first embodiment of the present invention. Reference numeral 100 denotes an imaging device called a CMOS image sensor, which photoelectrically converts a received subject image and outputs an electrical signal as a digital signal. The image sensor 100 includes a pixel unit 10, a vertical scanning circuit 15, an amplification unit 20, a ramp signal generation circuit (reference signal generation circuit) 25, a comparison unit 30, a counter unit 40, a memory unit 50, an output circuit 60, and a horizontal scanning circuit 65. And a timing generation circuit (TG) 70. The pixel unit 10 includes a plurality of pixels 10-1 arranged in a two-dimensional matrix. The pixel 10-1 outputs a pixel signal by photoelectric conversion. The vertical scanning circuit 15 outputs drive pulses X-1, X-2,. The amplifying unit 20 amplifies the pixel signal from the pixel unit 10. The ramp signal generation circuit 25 generates a ramp signal (reference signal) that changes with time as a comparison signal with the pixel signal. The comparison unit 30 compares the pixel signal amplified by the amplification unit 20 with the ramp signal. The counter unit 40 counts until the comparison unit 30 outputs the comparison result. The memory unit 50 holds the count data of the counter unit 40 and performs bit shift and calculation of the held data. The horizontal scanning circuit 65 transfers data from the memory unit 50 to the output circuit 60 by horizontal scanning. The timing generation circuit 70 controls the timing of each of the circuit blocks.

  In the pixel portion 10, a plurality of pixels 10-1 are arranged on the area, but only four pixels are illustrated in FIG. 1 for simplicity. The row of each pixel 10-1 is sequentially driven by drive pulses X-1 and X-2 from the vertical scanning circuit 15, and the reset signal (reference signal) of each pixel 10-1 and the effective signal which is a photoelectric conversion signal are vertical. It is guided to the amplifying unit 20 through the output lines V-1 to Vn. Each circuit is provided for each of the vertical output lines V- 1 to V-n from the amplifier unit 20 to the memory unit 50. Each amplifying circuit 20-1 of the amplifying unit 20 may have only a function of amplifying the signal from the pixel 10-1, or may have a CDS processing function for performing differential processing of the reset signal from the effective signal. . When the CDS processing function is not provided in the amplifier unit 20, CDS processing is performed at the input unit of the comparison unit 30. Further, although the amplification unit 20 is not essential, the amplification has an effect of reducing the influence of noise generated in the comparison unit 30.

  The comparison unit 30 includes a comparison circuit 30-1 corresponding to the pixel column from the amplification unit 20, and a selection circuit 30-2 that selects one of the plurality of ramp signals. The comparison unit 30 first determines whether the amplitude of the pixel signal from the amplifier circuit 20-1 is larger or smaller than the comparison reference signal set in consideration of the SN ratio of the pixel signal, and the pixel signal is determined according to the result. A ramp signal to be compared with is selected and a comparison process is performed. Each comparison circuit 30-1 outputs an inverted signal, which is a comparison result compared with one selected ramp signal, based on the input signal amplitude determination result. The comparison unit 30 compares the pixel signal with the ramp signal, and the counter unit 40 counts the counter clock from the rise of the ramp signal to the inversion of the output signal. It is held in the circuit 50-1. The memory circuit 50-1 shifts or calculates the AD conversion data of the reset signal and the AD conversion data of the valid signal to increase the number of bits, and transfers it to the output circuit 60 by the scanning pulse from the horizontal scanning circuit 65.

  As described above, since the image sensor 100 compares the ramp signal with one comparator circuit 30-1 in accordance with the amplitude of the pixel signal, the AD conversion data with a small number of bits is converted into the AD converted data with a small number of bits. There is an effect that can be acquired.

  FIG. 2 is an explanatory diagram of the SN ratio of the pixel signal for explaining the operation principle of the image sensor 100 of FIG. In FIG. 2, the horizontal axis indicates the amount of light incident on the pixel 10-1, and the vertical axis indicates the signal level photoelectrically converted according to the amount of incident light. A solid line 201 is a signal, and it is assumed that the signal level 1V is N = 10,000 photocharges. A broken line 202 represents light shot noise, and the amount of noise is represented by √N as is well known. A broken line 203 represents pixel system noise after CDS (including noise caused by an amplifier, not including noise caused by AD conversion). If the pixel system noise 203 is 0.2 mV, the SN ratio, which is the ratio of the signal level 1 V and the pixel system noise 0.2 mV, is 74 dB. In order to perform AD conversion while covering this SN ratio, a resolution of about 14 bits is required in consideration of quantization bit errors. Since the counter period increases as the resolution becomes higher, AD conversion time is required, and the signal reading speed is low for the image pickup device, and consequently high-speed shooting cannot be performed.

  Therefore, this embodiment achieves high-speed reading by reducing the number of AD conversion bits. For example, if the large amplitude signal level is 1 V, the optical shot noise 202 is large. Therefore, if the large amplitude signal level is 10000 charges, the optical shot noise is 100 and the SN ratio is 40 dB. . When the small amplitude signal level is 10 mV, the SN ratio is 20 dB. That is, it can be seen that any resolution at which a signal-to-noise ratio of just over 40 dB is ensured at any point of the signal level.

  In FIG. 2, 10-bit AD conversion is considered by dividing the large amplitude signal AD (H) and the small amplitude signal AD (L) by 62.5 mV, which is 1/16 of the signal 1V (corresponding to 4 bits). The AD conversion resolution for a signal amplitude of 1 V is represented by a two-dot chain line 204, and the AD conversion resolution for a signal amplitude of 62.5 mV is represented by a one-dot chain line 205. Then, both AD conversions have 10-bit AD conversion accuracy, but the AD resolution is small even if the quantization error is considered in the optical shot noise 202. By bit shifting these two AD conversion data, 14-bit AD conversion data can be obtained with a 10-bit AD converter.

The conversion for the large amplitude signal and the conversion for the small amplitude signal are each performed with 10 bits, and the ratio of the slope of the ramp signal supplied during the conversion, that is, the rate of change of the reference signal with respect to time, is set to 16. 2 ⁴ = 16 corresponds to a change in resolution of 4 bits. By combining both of these relationships, a 14-bit resolution is obtained for a signal range of 1V. Here, the conversion of a large amplitude signal is considered. In the present embodiment, it is determined whether the signal is a large amplitude signal with 1/16 of the maximum value 1V of the signal amplitude. This is 1000 mV / 16 = 62.5 mV. Therefore, the boundary of determination is 62.5 mV.

  On the other hand, in the conversion of a small amplitude signal, AD conversion is performed on a small amplitude signal up to 62.5 mV, which is a boundary, with a ramp signal having a slope of 1/16 of the ramp signal with respect to the large amplitude signal. Therefore, the AD conversion resolution 205 of the small amplitude signal is 1/16 of the AD conversion resolution 204 of the large amplitude signal. Therefore, the resolution of 10-bit AD conversion with respect to the signal amplitude of 62.5 mV is 62.5 mV / 1024≈0.0612 mV. The resolution of 0.0612 mV is a sufficiently small value with respect to the value of 0.2 mV of the pixel noise 203 described above. Note that the 62.5 mV signal at the boundary may be handled as either a large amplitude signal or a small amplitude signal.

  FIG. 3 is an explanatory diagram of a plurality of ramp signals according to the present embodiment. FIG. 3 shows a slope which is a time change of the ramp signal. The first ramp signal (first reference signal) VH is used for a signal amplitude of 62.5 mV or more in FIG. 2, and the second ramp signal (second reference) is used for a signal less than 62.5 mV. Signal) VL is used. The second ramp signal has a smaller slope (change rate with respect to time) than the first ramp signal VH. The slope ratio between the ramp signals VH and VL is 16. If the slope ratio is set to 16, the resolution for 4 bits can be increased. Since both of the AD conversion circuits have 10-bit conversion and the same longest conversion period, the counter clocks have the same clock frequency. If the slope ratio is set to 8, the resolution for 3 bits can be increased. In FIG. 2, since the AD conversion resolution of the small amplitude signal is sufficiently smaller than the system noise, 9 bits may be used. In this case, since the maximum clock frequency fmax of the counter is assigned to 10-bit AD conversion in order to shorten the conversion period, the counter clock of the 9-bit AD conversion circuit is ½ × fmax. The slope ratio of the ramp signal and the resolution of the AD conversion circuit are determined by the number of saturated charges of the pixel, system noise, resolution necessary for the image sensor 100, and the like. The slope ratio of the ramp signals VH and VL having different slopes is preferably a multiple of 2. The counter unit 40 may count the ramp signals VH and VL using a counter clock having the same frequency or may use a counter clock having a different frequency.

  FIG. 4 is a block diagram of an AD conversion unit for explaining the connection with the input / output circuit of the comparison circuit 30-1 according to the first embodiment of the present invention. Blocks having the same functions as those in FIG. Is omitted. The AD converter can convert the photoelectrically converted analog signal into a digital signal at high speed.

  Next, in order to facilitate the description of the present embodiment, a configuration example and operation of an imaging apparatus that does not have an AD converter will be described. FIG. 11 is a diagram illustrating a configuration example of the pixel unit 210 and the amplifier circuit 220-1 in the image sensor, and is a diagram in which the comparison unit 30, the counter unit 40, and the memory unit 50 are omitted. The CDS circuit 119 is provided at the subsequent stage of the amplifier circuit 220-1. The pixel unit 210 includes a plurality of pixels 210-1 arranged in a plurality of columns and a plurality of rows. In FIG. 11, signals output from the pixels in the odd-numbered columns counting from the left are read out by a readout circuit arranged below the pixel portion 210. On the other hand, signals output from the pixels in the even-numbered columns counting from the left are read out by a readout circuit (not shown) arranged above the pixel unit 210. In this manner, by providing readout circuits alternately, the area of two columns of the pixel portion 210 can be used when the readout circuits are laid out.

  FIG. 12 is a circuit diagram of one pixel 210-1. The transfer switch 102 is driven by a transfer pulse PTX. The reset switch 103 is driven by a reset pulse PRES. The row selection switch 105 is driven by a row selection pulse PSEL. PTX is a symbol representing PTX1 to PTXn (n is the number of rows). PRES is a symbol representing PRES 1 to n. PSEL is a symbol representing PSEL1 to PSELn.

  FIG. 13 is a timing chart showing an operation example of the image sensor shown in FIG. Hereinafter, an operation example of the image sensor will be described with reference to FIGS. Prior to the reading operation, the image sensor is exposed for a set exposure time, and photocharge is accumulated in the photodiode 101. In the following description, it is assumed that a row driven by PRES1, PTX1, and PSEL1 output from the vertical scanning circuit 215 is selected.

  First, the pixel reset pulse PRES changes from the high level to the low level, and the reset of the gate electrode of the amplification MOSFET 104 is released. At this time, the floating diffusion portion FD connected to the gate electrode holds a potential corresponding to the release of the reset. Subsequently, when the row selection pulse PSEL becomes high level, an output corresponding to the potential of the floating diffusion portion FD appears on the vertical output line V-1 by the source follower circuit formed by the amplification MOSFET 104 and the constant current source 107. In this state, when the clamp pulse PC0R is activated to a high level, the clamp switch 109 is turned on and the variable amplifying unit 131 enters a voltage follower state, and the electrode on the column amplifier side of the clamp capacitor 108 becomes substantially equal to the voltage VREF. . Thereafter, the clamp pulse PC0R is deactivated from the high level to the low level, and the output on the vertical output line V-1 is clamped.

Subsequently, the accumulation pulse PTN is activated to a high level, and the offset signal of the amplifier circuit 220-1 is stored in the storage capacitor 112n via the transfer gate 110n. Thereafter, the transfer pulse PTX is activated to a high level, whereby the transfer switch 102 is set to a high level for a certain period, and the photoelectric charge accumulated in the photodiode 101 is transferred to the gate electrode of the amplification MOSFET 104. Here, the transferred charge is an electron. If the absolute value of the amount of transferred charge is Q and the capacitance of the floating diffusion portion FD is CFD, the gate potential decreases by Q / CFD. In response to this, the potential of the vertical output line V-1 changes. Assuming that the source follower gain is Gsf, a change ΔVvl of the potential Vvl of the vertical output line V-1 due to transfer of charges from the photodiode 101 to the floating diffusion portion FD is expressed by the following equation (1).
ΔVvl = −Q · Gsf / CFD (1)

This potential change ΔVvl is voltage amplified by a variable amplifying unit 131 including an operational amplifier 120, a clamp capacitor 108, and a feedback capacitor 121, and an output Vct of the variable amplifying unit 131 is expressed by equation (2).
Vct = VREF + Q · (Gsf / CFD) · (C0 / Cf) (2)

  Here, C0 indicates the capacitance of the clamp capacitor 108, and Cf indicates the capacitance value of the feedback capacitors 121a, 121b, and 121c that are selected when the sensitivity switching pulses x1, x2, and x4 are activated. For example, C0 = 1 pF. When the feedback capacitor 121a is selected, Cf = 1 pF, when the feedback capacitor 121b is selected, Cf = 0.5 pF, and when the feedback capacitor 121c is selected, Cf = 0.25 pF. The voltage amplification factors represented by -C0 / Cf are -1 times, -2 times, and -4 times, respectively. That is, in the system in which negative feedback is applied to the operational amplifier 120, by switching which one of the plurality of feedback capacitors 121a to 121c is selected, the feedback coefficient determined by the voltage division ratio between Cf and C0 is changed, The voltage amplification factor can be switched. Note that a negative sign in the voltage amplification factor indicates an inverting amplifier circuit. The accumulation pulse PTS goes high after the transfer pulse PTX goes low, and the level output from the amplifier circuit 220-1 at this time is accumulated in the storage capacitor 112s via the transfer gate 110s.

  Subsequently, the column selection switches 114s and 114n are sequentially turned on by the scanning pulses COLSEL1, COLSEL2,... Generated by the horizontal scanning circuit 65. Then, the signals stored in the storage capacitor 112s are output to the horizontal output line 116s in the column order, and the signals stored in the storage capacitor 112n are output to the horizontal output line 116n in the column order. The signal pairs in a plurality of columns are sequentially output to the horizontal output lines 116s and 116n. The difference processing unit 118 outputs the difference between the signal pairs in each column output to the horizontal output lines 116s and 116n. Thereby, noise components included in the signal held in the holding capacitor 112s can be reduced.

  FIG. 5 is a timing diagram illustrating a driving method of the image sensor 100 of the present embodiment, and in particular, is a timing diagram of the AD conversion unit of FIG. Hereinafter, the AD conversion operation will be described with reference to FIGS. In FIG. 5, a period Tad is an AD conversion period of the N signal and S signal of the analog signal Va read from the pixel, and a period Tdata is an AD conversion data transfer period. In the period Tad, the period Td is an N signal AD conversion period of N signals from the pixels, and a comparison signal for this is the ramp signal VR. A period Tj is a signal level determination period of the S signal, and a comparison signal for this is the reference signal VREF. The period Tu is the S signal AD conversion period, and the comparison signal for this is the ramp signal VH (or the ramp signal VL). The output signal Va of the amplifier circuit 20-1 mainly takes an N signal level and an S signal level as shown in the figure, and is led to the input terminal of the comparison circuit 30-1. A ramp signal VRAMP, which is a comparison signal of the signal Va, is input to the other input terminal of the comparison circuit 30-1. The N signal in the following description corresponds to a signal sampled by the signal PTN in FIG. 13 when the CDS circuit is provided before the comparison unit 30. On the other hand, when the CDS circuit is not provided, this corresponds to a signal output to the vertical signal line in response to resetting of the floating diffusion portion. Similarly, the S signal in the following description corresponds to a signal sampled by the signal PTS in FIG. 13 when the CDS circuit is provided before the comparison unit 30. On the other hand, when the CDS circuit is not provided, it corresponds to a signal output to the vertical signal line by transferring the charge generated in the photodiode to the floating diffusion portion.

  The ramp signal generation circuit 25 is controlled by the control signal CNT2 of the timing generation circuit 70 to generate the ramp signal VH / reference signal VREF and the ramp signal VL / ramp signal VR. The ramp signal VH is a ramp signal for upper bits with a large slope, and the ramp signal VL is a ramp signal for lower bits with a small slope. The reference signal VREF is a comparison reference signal for determining the S signal level, and the ramp signal VR is a ramp signal to be compared with the N signal. These four types of ramp signals are selected by the selection circuit 30-2 controlled by the control signal CNT1 of the timing generation circuit 70 and input to the comparison circuit 30-1. The timing generation circuit 70 controls the ramp signal generation circuit 25 by the control signal CNT2.

  The comparison circuit 30-1 compares the N signal and the ramp signal VR in the N signal AD conversion period Td, and the period from when the ramp signal VR starts to change until the magnitude relationship with the N signal is reversed is Tr. Suppose there is. The counter circuit 40-1 counts during the period Tr, and the memory circuit 50-1 holds the count value as N signal data. The ramp signal VR has the same slope as the ramp signal VL. By setting the same inclination, high-resolution N-signal AD conversion data can be obtained. Next, the comparison circuit 30-1 compares the signal levels of the S signal and the reference signal VREF in the S signal level determination period Tj. In the illustrated example, during the S signal level determination period Tj, the comparison circuit 30-1 outputs a high level selection signal SEL representing a comparison result in which the S signal is greater than the reference signal VREF to the selection circuit 30-2. As a result, the selection circuit 30-2 selects the ramp signal VH having a large slope in the S signal AD conversion period Tu and outputs it to the comparison circuit 30-1. The comparison circuit 30-1 compares the S signal and the ramp signal VH, and the counter circuit 40-1 performs a counting operation during a period Ts until the magnitude relationship between the two is reversed. The memory circuit 50-1 holds the count value as S signal AD conversion data. If the output of the comparison circuit 30-1 does not reverse during the S signal level determination period Tj, this indicates a comparison result that the selection signal SEL is at a low level and the S signal level is smaller than the reference signal VREF. 2 selects a ramp signal VL having a small inclination as the ramp signal. In that case, the comparison circuit 30-1 compares the S signal with the ramp signal VL. The selection circuit 30-2 selects the ramp signal VH or VL having a different slope according to the level of the S signal amplified by the amplification unit 20. That is, the selection circuit 30-2 sets the rate of change of the ramp signal with respect to time according to the level of the S signal based on the pixel. The comparison circuit 30-1 compares the ramp signal selected by the selection circuit 30-2 with the S signal amplified by the amplification unit 20. The counter circuit 40-1 counts from the start of the change of the ramp signal until the comparison circuit 30-1 outputs a signal indicating that the magnitude relationship between the S signal and the ramp signal is reversed.

  In FIG. 5, the ramp signal VR and the ramp signal VL have the same slope as described above. In the N signal AD conversion period Td, the ramp signal VR is compared with the N signal. However, since the N signal is also a reference signal for the S signal, high accuracy is required. Since the ramp signal VR has the same slope as the ramp signal VL that generates the lower bits, there is an advantage that the same ramp signal generation circuit 25 can be used. The count result of the counter circuit 40-1 is stored in the memory unit 50. The memory unit 50 subtracts the N signal AD conversion data from the S signal AD conversion data. The subtracted data is transferred from the memory unit 50 to the output circuit 60 under the control of the horizontal scanning circuit 65. By this difference processing, AD conversion errors due to variations in the offset variation of the amplifier circuit 20-1 and the response speed of the comparison circuit 30-1 are removed. The AD conversion data of the S signal AD-converted using the ramp signal VL is subjected to a difference from the N signal AD conversion data. On the other hand, the S signal AD conversion data AD-converted using the ramp signal VH is bit-shifted by 4 bits because the slope of the ramp signal is different from that of the N signal AD conversion data. The difference is made. The main causes of the potential fluctuation of the N signal are the N signal when the pixel is reset, the offset of the amplifier circuit 20-1, and the fluctuation component (up to several tens of mV) when the comparison circuit 30-1 is initially set. The offset component of the N signal and the amplifier circuit 20-1 is reduced by the CDS processing in the previous stage of the comparison circuit 30-1, but the fluctuation component of the comparison circuit 30-1 may be considered as the N signal AD conversion data. As a result of the difference processing, the N signal is reduced. The AD conversion data of the large amplitude signal is 14 bits, but in the description of FIG. 6, the lower 4 bits (4LSB) are smaller than the optical shot noise 202 (FIG. 2), and can be used as dummy data.

  The gain of the amplifier circuit 20-1 in FIG. 4 is 1 when the pixel signal from the pixel unit 10 is the signal 201 described in FIG. However, the imaging system described later with reference to FIG. 10 has sensitivity settings suitable for the shooting environment. For example, when the sensitivity setting is 16 times, the signal level 62.5 mV in FIG. 2 is amplified to 1 V and input to the comparison circuit 30-1. At this time, the resolution of 10-bit AD conversion for comparing the large amplitude signal with the ramp signal VH is sufficient for the SN ratio necessary for AD conversion. Therefore, if the sensitivity setting is 16 times or more, the selection circuit 30-2 selects the ramp signal VH by the control signal CONT1 from the timing generation circuit 70 and outputs it to the comparison circuit 30-1. good. Since the S / N ratio of the pixel unit 10 is greatly affected by the aperture area of the pixel unit 10, the slope ratio of the ramp signal VH and the ramp signal VL and the sensitivity setting for selecting the ramp signal VH vary depending on the aperture area. .

  FIG. 6 is an explanatory diagram of a bit shift unit of AD conversion data according to the present embodiment. For example, the bit shift unit in the memory circuit 50-1 performs a bit shift process. The AD conversion data here is described as data obtained by subtracting data obtained by AD conversion of the N signal from data obtained by AD conversion of the S signal. FIG. 6A shows a case where the S signal is larger than the comparison reference signal (62.5 mV in this embodiment), and the AD conversion data is a comparison result with the ramp signal VH having a large slope. The AD conversion data D0 to D9 are shifted by 4 bits and output as AD conversion data Da4 to Da13. In this case, since the lower bits below the data Da3 are smaller than the optical shot noise 202, low level data is output. FIG. 6B shows a case where the S signal is smaller than the comparison reference signal, and the AD conversion data is a comparison result with the ramp signal VL having a small inclination. The AD conversion data D0 to D9 are not bit-shifted and output as they are as AD conversion data Da0 to Da9. In this case, since the signal amplitude up to the data Da9 is AD-converted, there is no high level in the upper bits higher than the data Da10, so the data Da10 to Da13 are set to the low level. Note that there may be three or more types of ramp signals having different inclinations. The bit shift unit bit-shifts data D0 to D9 corresponding to at least the ramp signal having the largest inclination.

  In this embodiment, since the slope of the ramp signal is changed with the boundary of the S signal amplitude of 62.5 mV as described above, when the amplitude of the S signal is 62.5 mV or more, the AD-converted 10-bit The AD conversion data D0 to D9 are shifted by 4 bits. As a result, 14-bit AD conversion data Da0 to Da13 can be acquired. In the present embodiment, the switching of the ramp signal has been described as the signal level of 62.5 mV, but may be 65 mV or 70 mV. That is, the S signal is always compared with the ramp signal VH or the ramp signal VL, and AD conversion data can be acquired. In this case, the difference in resolution between the optical shot noise 202 and the AD conversion data is different, but the AD conversion resolution is smaller than that of the optical shot noise 202, so that there is no problem. As described above, the determination of the switching signal level does not need to be equal to or less than the AD conversion accuracy with respect to the AD conversion accuracy, and may be low accuracy.

  The above-described bit shift unit captures data when the data from the counter unit 40 is held in the memory unit 50, when it is transferred from the memory unit 50 to the output circuit 60, when it is output from the output circuit 60 to the outside of the image sensor 100, or the like. It can be provided in the element. Further, the bit shift unit may be provided outside the image sensor 100 (for example, the video signal processing circuit unit 830 in FIG. 10). At this time, if bit data for recognizing the signal determination level (selection signal SEL) with respect to the comparison reference signal is added to the AD conversion data, it becomes easy to cope with any bit shift method. The AD conversion data D0 to D9 output from the counter unit 40 are output together with flag data indicating the level of the S signal.

(Second Embodiment)
FIG. 7 is a block diagram of an AD conversion unit according to the second embodiment of the present invention. In the present embodiment, the signal level is determined by a signal level determination circuit (selection circuit) 30-3. Hereinafter, the points of the present embodiment different from the first embodiment will be described. As described in the description of the bit shift in FIG. 6, since the determination of the ramp signal switching may be low accuracy, it is not always necessary to perform the determination by the comparison circuit 30-1, and the determination may be made by the signal level determination circuit 30-3. good. In this case, the ramp signal generation circuit 25 outputs the ramp signal VH and the ramp signal VL / ramp signal VR to the selection circuit 30-2. The signal level determination circuit 30-3 outputs a high level determination signal SEL2 to the selection circuit 30-2 when the S signal is greater than the reference signal VREF, and the selection circuit 30-2 performs ramping based on the high level determination signal SEL2. The signal VH is output to the comparison circuit 30-1. On the other hand, the signal level determination circuit 30-3 outputs a low level determination signal SEL2 to the selection circuit 30-2 when the S signal is smaller than the reference signal VREF, and the selection circuit 30-2 outputs the low level determination signal SEL2. Is output to the comparison circuit 30-1. The ramp signal VRAMP of this embodiment does not require the reference signal VREF. The ramp signal generation circuit 25
Thus, since the ramp signal VREF is not generated, the ramp signal generation circuit 25 can be simplified.

(Third embodiment)
FIG. 8 is a block diagram of an AD conversion unit according to the third embodiment of the present invention. Hereinafter, the points of the present embodiment different from the second embodiment will be described. In the present embodiment, the ramp signal generation circuit 25 generates the ramp signal VH and outputs it to the attenuator 30-4. The attenuator 30-4 attenuates the ramp signal VH generated by the ramp signal generation circuit 25, thereby generating a ramp signal VL and a ramp signal VR having different slopes. The attenuator 30-4 outputs the ramp signal VH, the ramp signal VL, or the ramp signal VR to the comparison circuit 30-1 according to the control signal CONT1 and the determination signal SEL2 (or the selection signal SEL). By providing the attenuator 30-4, there is an effect that the number of wires from the ramp signal generation circuit 25 to the attenuator 30-4 can be halved.

  FIG. 9 is a block diagram of the AD conversion data bit number adjustment unit of the present embodiment. The bit number adjustment unit has an output buffer. In the description of the first to third embodiments, 10-bit AD conversion data D0 to D9 is bit-shifted to 14-bit AD conversion data Da0 to Da13 to achieve high resolution. However, depending on the application of the image sensor 100, low resolution and low power consumption may be required. When a dark subject is imaged and the pixel signal is amplified, light shot noise and system noise increase, and the signal-to-noise ratio of the signal deteriorates. In this case, the AD conversion data may be 12 bits or 10 bits. The output buffer receives supply of the power supply voltage Vdd, buffers the 14-bit data Da0 to Da13, and outputs them. The output buffers for the lower 4-bit data Da0 to Da3 are supplied with the power supply voltage Vdd by the control signals Dcont2 and Dcont4. When the output buffers of the lower 4 bits data Da0 to Da3 do not input the power supply voltage Vdd by the control signals Dcont2 and Dcont4, the output buffers of the upper 10 bits data Da4 to Da13 output 10 bits data Da4 to Da13. On the other hand, when the output buffer of the lower 2-bit data Da0 and Da1 does not input the power supply voltage Vdd by the control signal Dcont2, the output buffer of the upper 12-bit data Da2 to Da13 outputs the 12-bit data Da2 to Da13. To do. Thereby, 14-bit, 12-bit, or 10-bit AD conversion data can be output. The bit number adjustment unit reduces the number of bits of the data bit-shifted by the bit shift unit of FIG. 6 according to the control signals Dcont2 and Dcont4. The number of bits used and power consumption of AD conversion data can be controlled by the control signals Dcont2 and Dcont4. By controlling the number of used bits, there is an effect that the power consumption of the image sensor 100 can be reduced and the power consumption of the image signal processing of the imaging system of FIG. 10 can be reduced. The number of bits used can be controlled according to the amplification factor of the amplification unit 20 or the sensitivity setting of the imaging system of FIG.

(Fourth embodiment)
FIG. 10 is a diagram illustrating a configuration example of an imaging system according to the fourth embodiment of the present invention. The imaging system 800 includes, for example, an optical unit 810, an imaging device 100, a video signal processing circuit unit 830, a recording / communication unit 840, a timing control circuit unit 850, a system control circuit unit 860, and a reproduction / display unit 870. The imaging device 820 includes the imaging device 100 and a video signal processing circuit unit 830. As the image sensor 100, the image sensor 100 described in the above embodiments is used.

  An optical unit 810 that is an optical system such as a lens forms an image of a subject by forming light from the subject on the pixel unit 10 (FIG. 1) in which a plurality of pixels are two-dimensionally arranged in the image sensor 100. To do. The image sensor 100 outputs a signal corresponding to the light imaged on the pixel unit 10 at a timing based on the signal from the timing control circuit unit 850. A signal output from the image sensor 100 is input to a video signal processing circuit unit 830 that is a video signal processing unit, and the video signal processing circuit unit 830 performs an operation on the input signal according to a method determined by a program or the like. Signal processing such as the bit shift processing of FIG. 6 is performed. The signal obtained by the processing in the video signal processing circuit unit 830 is sent to the recording / communication unit 840 as image data. The recording / communication unit 840 sends a signal for forming an image to the reproduction / display unit 870 and causes the reproduction / display unit 870 to reproduce / display a moving image or a still image. The recording / communication unit 840 receives a signal from the video signal processing circuit unit 830 and communicates with the system control circuit unit 860, and records a signal for forming an image on a recording medium (not shown). Also works.

  The system control circuit unit 860 controls the operation of the imaging system in an integrated manner, and controls the driving of the optical unit 810, the timing control circuit unit 850, the recording / communication unit 840, and the reproduction / display unit 870. Further, the system control circuit unit 860 includes a storage device (not shown) that is a recording medium, for example, and a program and the like necessary for controlling the operation of the imaging system are recorded therein. Further, the system control circuit unit 860 supplies a signal for switching the driving mode in accordance with, for example, a user operation into the imaging system. Specific examples include a change in a line to be read out and a line to be reset, a change in an angle of view associated with electronic zoom, and a shift in angle of view associated with electronic image stabilization. The timing control circuit unit 850 controls the drive timing of the image sensor 100 and the video signal processing circuit unit 830 based on control by the system control circuit unit 860 which is a control unit.

  As described above, in the first to fourth embodiments, it is determined whether the signal to be AD-converted is a large amplitude signal or a small amplitude signal, and a ramp signal having a slope suitable for the determined signal is compared. AD conversion data is obtained, and multi-biting is achieved by the bit shift processing of FIG. In a dark shooting environment, although depending on exposure conditions, the S signal tends to be a small amplitude signal, and it is conceivable to increase the sensitivity by amplifying the S signal. In the first embodiment, the sensitivity can be increased by amplifying the signal by the amplifier circuit 20-1. When the signal from the pixel unit 10 is input to the comparison circuit 30-1 without being amplified, the slope of the ramp signal can be changed to increase the sensitivity as a result. The above embodiment does not uniquely determine the slope of the ramp signal, but can change the slope of the ramp signal in response to the required sensitivity increase. For example, when the sensitivity increase is doubled, the slope of the ramp signal is changed. It can be controlled to 1/2.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof. For example, as the reference signal, a ramp signal whose level changes linearly with respect to time has been described, but a ramp signal that changes stepwise may be used.

10-1 pixel, 30-1 comparison circuit, 30-2 selection circuit, 40-1 counter circuit

Claims (11)

A photoelectric conversion unit that generates charges based on photoelectric conversion;
An analog-digital converter,
An arithmetic unit,
The analog-digital converter is
Noise signal and the first potential change rate outputs a first comparison result signal by performing a first comparison is a comparison of the ramp signal which varies with time, a signal based on the charge the second comparison result signal by performing a second comparison is a comparison of the ramp signal in which the first potential change rate greater than the second change rate changes with time and A comparison circuit that
The analog-to-digital conversion unit generates a first digital signal based on the noise signal using the first comparison result signal,
The analog-to-digital conversion unit generates a second digital signal based on the signal based on the charge using the second comparison result signal,
The arithmetic unit generates a third digital signal by bit-shifting or calculating the second digital signal so as to reduce a difference in resolution between the first digital signal and the second digital signal. ,
The imaging unit is characterized in that the arithmetic unit generates a difference signal between the first digital signal and the third digital signal. Claim based on the ratio between the previous SL second rate of change the first rate of change, by calculating the second digital signal, wherein said third digital signal is generated The imaging apparatus according to 1. Furthermore, the analog-digital converter has a memory,
The memory holds the first digital signal and the second digital signal;
The memory of the previous SL based on the ratio of the second change rate and the first rate of change, the imaging of claim 1 or 2, wherein the performing the process of calculating the second digital signal apparatus. The comparison circuit outputs a third comparison result signal by performing a third comparison that is a comparison between the signal based on the charge and a threshold before the second comparison,
The second comparison is performed using a ramp signal whose potential changes at the first rate of change when the third comparison result signal indicates that the signal based on the charge is smaller than the threshold value. If the third comparison result signal indicates that the signal based on the charge is larger than the threshold value, the third comparison result signal is performed using a ramp signal whose potential changes at the second rate of change. The imaging device according to any one of claims 1 to 3 . The second digital signal, based on the value of the third comparison result signal, said first rate of change and the second change rate and the difference can be based on the bit shift or computing the determined The imaging apparatus according to claim 4 . And a selection circuit;
And a ramp signal generating circuit for outputting the ramp signal with said ramp signal and the second rate of change with a first rate of change in the selection circuit,
The selection circuit selects one of the ramp signals output from the ramp signal generation circuit according to the level of the third comparison result signal, and outputs the selected one to the comparison circuit. Item 6. The imaging device according to Item 4 or 5 . The ramp signal generation circuit outputs a ramp signal whose potential changes at the first rate of change to the selection circuit via a first wiring,
The ramp signal generation circuit outputs a ramp signal whose potential changes at the second rate of change to the selection circuit via a second wiring,
The imaging apparatus according to claim 6, wherein the ramp signal generation circuit outputs the threshold value to the selection circuit via one of the first wiring and the second wiring. The comparison circuit includes a first input terminal to which a signal based on the charge is input, and a second input terminal to which the first ramp signal and the second ramp signal are sequentially input. The imaging device according to any one of claims 1 to 7 . An imaging device;
A signal processing unit that generates an image based on a signal output from the imaging device;
The imaging device
A photoelectric conversion unit that generates charges based on photoelectric conversion;
An analog-digital converter,
The analog-digital converter is
A first comparison result signal is output by performing a first comparison, which is a comparison between a noise signal and a ramp signal whose potential changes with time at a first rate of change, and a signal based on the charge A comparison circuit that outputs a second comparison result signal by performing a second comparison that is a comparison with a ramp signal whose potential changes with time at a second change rate greater than the first change rate . Have
The analog-to-digital conversion unit generates a first digital signal based on the noise signal using the first comparison result signal,
The analog-to-digital conversion unit generates a second digital signal based on the signal based on the charge using the second comparison result signal,
The signal processing unit generates a third digital signal by bit-shifting or calculating the second digital signal so as to reduce a difference in resolution between the first digital signal and the second digital signal. And
The image processing system, wherein the signal processing unit generates a difference signal between the first digital signal and the third digital signal. The imaging device according to any one of claims 1 to 8 ,
And a signal processing unit that generates an image based on a signal output from the imaging device. A method for driving an imaging apparatus having a photoelectric conversion unit that generates charges based on photoelectric conversion,
Generating a first comparison result signal by performing a first comparison that is a comparison between a noise signal and a ramp signal whose potential changes with time at a first rate of change ;
A second comparison result is obtained by performing a second comparison which is a comparison between the signal based on the charge and a ramp signal whose potential changes with time at a second change rate larger than the first change rate . Generating a signal;
Generating a first digital signal based on the noise signal using the first comparison result signal;
Using the second comparison result signal from the start of the second comparison to generate a second digital signal based on the charge-based signal;
Generating a third digital signal by bit-shifting or calculating the second digital signal so as to reduce a difference in resolution between the first digital signal and the second digital signal ;
And a step of generating a difference signal between the first digital signal and the third digital signal.

Images