JP4758002B2 - 炭化フッ素ガスケミストリーを用いた二酸化珪素をエッチングする方法 - Google Patents

炭化フッ素ガスケミストリーを用いた二酸化珪素をエッチングする方法 Download PDF

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Publication number
JP4758002B2
JP4758002B2 JP2000547650A JP2000547650A JP4758002B2 JP 4758002 B2 JP4758002 B2 JP 4758002B2 JP 2000547650 A JP2000547650 A JP 2000547650A JP 2000547650 A JP2000547650 A JP 2000547650A JP 4758002 B2 JP4758002 B2 JP 4758002B2
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Japan
Prior art keywords
etching
silicon oxide
layer
oxygen
opening
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JP2000547650A
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Japanese (ja)
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JP2002514012A (ja
JP2002514012A5 (enExample
Inventor
キーヴァン カージュノーリ,
トーマス, ディー. グエン,
ジョージ ミューラー,
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Lam Research Corp
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Lam Research Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2000547650A 1998-05-05 1999-04-22 炭化フッ素ガスケミストリーを用いた二酸化珪素をエッチングする方法 Expired - Fee Related JP4758002B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/071,960 1998-05-05
US09/071,960 US6117786A (en) 1998-05-05 1998-05-05 Method for etching silicon dioxide using fluorocarbon gas chemistry
PCT/US1999/008798 WO1999057757A1 (en) 1998-05-05 1999-04-22 Method for etching silicon dioxide using fluorocarbon gas chemistry

Publications (3)

Publication Number Publication Date
JP2002514012A JP2002514012A (ja) 2002-05-14
JP2002514012A5 JP2002514012A5 (enExample) 2006-06-15
JP4758002B2 true JP4758002B2 (ja) 2011-08-24

Family

ID=22104686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000547650A Expired - Fee Related JP4758002B2 (ja) 1998-05-05 1999-04-22 炭化フッ素ガスケミストリーを用いた二酸化珪素をエッチングする方法

Country Status (6)

Country Link
US (1) US6117786A (enExample)
EP (1) EP1078395A1 (enExample)
JP (1) JP4758002B2 (enExample)
KR (1) KR100628932B1 (enExample)
TW (1) TWI222136B (enExample)
WO (1) WO1999057757A1 (enExample)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531067B1 (en) * 1998-12-28 2003-03-11 Asahi Kasei Microsystems Co., Ltd. Method for forming contact hole
US6797189B2 (en) 1999-03-25 2004-09-28 Hoiman (Raymond) Hung Enhancement of silicon oxide etch rate and nitride selectivity using hexafluorobutadiene or other heavy perfluorocarbon
JP4173307B2 (ja) * 1999-06-24 2008-10-29 株式会社ルネサステクノロジ 半導体集積回路の製造方法
US6635335B1 (en) 1999-06-29 2003-10-21 Micron Technology, Inc. Etching methods and apparatus and substrate assemblies produced therewith
DE19937994C2 (de) * 1999-08-11 2003-12-11 Infineon Technologies Ag Ätzprozeß für eine Dual Damascene Strukturierung einer Isolierschicht auf einer Halbleiterstruktur
US20050158666A1 (en) * 1999-10-15 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple etch method for etching material etchable with oxygen containing plasma
US6486069B1 (en) * 1999-12-03 2002-11-26 Tegal Corporation Cobalt silicide etch process and apparatus
US6547979B1 (en) * 2000-08-31 2003-04-15 Micron Technology, Inc. Methods of enhancing selectivity of etching silicon dioxide relative to one or more organic substances; and plasma reaction chambers
JP2002110647A (ja) * 2000-09-29 2002-04-12 Hitachi Ltd 半導体集積回路装置の製造方法
DE10053780A1 (de) * 2000-10-30 2002-05-16 Infineon Technologies Ag Verfahren zur Strukturierung einer Siliziumoxid-Schicht
US6554004B1 (en) * 2000-11-07 2003-04-29 Motorola, Inc. Method for removing etch residue resulting from a process for forming a via
US6686296B1 (en) * 2000-11-28 2004-02-03 International Business Machines Corp. Nitrogen-based highly polymerizing plasma process for etching of organic materials in semiconductor manufacturing
US7311852B2 (en) * 2001-03-30 2007-12-25 Lam Research Corporation Method of plasma etching low-k dielectric materials
US6746961B2 (en) 2001-06-19 2004-06-08 Lam Research Corporation Plasma etching of dielectric layer with etch profile control
US7129178B1 (en) * 2002-02-13 2006-10-31 Cypress Semiconductor Corp. Reducing defect formation within an etched semiconductor topography
JP4153708B2 (ja) * 2002-03-12 2008-09-24 東京エレクトロン株式会社 エッチング方法
US7547635B2 (en) * 2002-06-14 2009-06-16 Lam Research Corporation Process for etching dielectric films with improved resist and/or etch profile characteristics
US20040171260A1 (en) * 2002-06-14 2004-09-02 Lam Research Corporation Line edge roughness control
US6706640B1 (en) * 2002-11-12 2004-03-16 Taiwan Semiconductor Manufacturing Co., Ltd Metal silicide etch resistant plasma etch method
DE10318568A1 (de) * 2003-04-15 2004-11-25 Technische Universität Dresden Siliziumsubstrat mit positiven Ätzprofilen mit definiertem Böschungswinkel und Verfahren zur Herstellung
JP4538209B2 (ja) * 2003-08-28 2010-09-08 株式会社日立ハイテクノロジーズ 半導体装置の製造方法
US7078337B2 (en) * 2003-09-30 2006-07-18 Agere Systems Inc. Selective isotropic etch for titanium-based materials
US7700492B2 (en) * 2005-06-22 2010-04-20 Tokyo Electron Limited Plasma etching method and apparatus, control program and computer-readable storage medium storing the control program
JP2007251034A (ja) * 2006-03-17 2007-09-27 Hitachi High-Technologies Corp プラズマ処理方法
US7718542B2 (en) * 2006-08-25 2010-05-18 Lam Research Corporation Low-k damage avoidance during bevel etch processing
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
US8507385B2 (en) * 2008-05-05 2013-08-13 Shanghai Lexvu Opto Microelectronics Technology Co., Ltd. Method for processing a thin film micro device on a substrate
CN102001616A (zh) * 2009-08-31 2011-04-06 上海丽恒光微电子科技有限公司 装配和封装微型机电系统装置的方法
JP6096470B2 (ja) * 2012-10-29 2017-03-15 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
CN103824767B (zh) * 2012-11-16 2017-05-17 中微半导体设备(上海)有限公司 一种深硅通孔的刻蚀方法
US9165785B2 (en) * 2013-03-29 2015-10-20 Tokyo Electron Limited Reducing bowing bias in etching an oxide layer
JP7403314B2 (ja) * 2019-12-26 2023-12-22 東京エレクトロン株式会社 エッチング方法及びエッチング装置
KR20230121424A (ko) 2022-02-11 2023-08-18 삼성전자주식회사 반도체 소자

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08130211A (ja) * 1994-10-31 1996-05-21 Tokyo Electron Ltd エッチング方法
WO1996036984A1 (en) * 1995-05-19 1996-11-21 Lam Research Corporation Electrode clamping assembly and method for assembly and use thereof
JPH1041274A (ja) * 1996-04-29 1998-02-13 Applied Materials Inc 誘電層のエッチング方法
JPH1098021A (ja) * 1996-09-19 1998-04-14 Seiko Epson Corp 半導体装置の製造方法
JPH11186229A (ja) * 1997-12-18 1999-07-09 Toshiba Corp ドライエッチング方法及び半導体装置の製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254213A (en) * 1989-10-25 1993-10-19 Matsushita Electric Industrial Co., Ltd. Method of forming contact windows
US5013400A (en) * 1990-01-30 1991-05-07 General Signal Corporation Dry etch process for forming champagne profiles, and dry etch apparatus
US5021121A (en) * 1990-02-16 1991-06-04 Applied Materials, Inc. Process for RIE etching silicon dioxide
US5013398A (en) * 1990-05-29 1991-05-07 Micron Technology, Inc. Anisotropic etch method for a sandwich structure
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric
JP3146561B2 (ja) * 1991-06-24 2001-03-19 株式会社デンソー 半導体装置の製造方法
US5269879A (en) * 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
KR100264445B1 (ko) * 1993-10-04 2000-11-01 히가시 데쓰로 플라즈마처리장치
US5431778A (en) * 1994-02-03 1995-07-11 Motorola, Inc. Dry etch method using non-halocarbon source gases
TW320749B (enExample) * 1994-09-22 1997-11-21 Tokyo Electron Co Ltd
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
JP3778299B2 (ja) * 1995-02-07 2006-05-24 東京エレクトロン株式会社 プラズマエッチング方法
US5626716A (en) * 1995-09-29 1997-05-06 Lam Research Corporation Plasma etching of semiconductors
US5780338A (en) * 1997-04-11 1998-07-14 Vanguard International Semiconductor Corporation Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08130211A (ja) * 1994-10-31 1996-05-21 Tokyo Electron Ltd エッチング方法
WO1996036984A1 (en) * 1995-05-19 1996-11-21 Lam Research Corporation Electrode clamping assembly and method for assembly and use thereof
JPH1041274A (ja) * 1996-04-29 1998-02-13 Applied Materials Inc 誘電層のエッチング方法
JPH1098021A (ja) * 1996-09-19 1998-04-14 Seiko Epson Corp 半導体装置の製造方法
JPH11186229A (ja) * 1997-12-18 1999-07-09 Toshiba Corp ドライエッチング方法及び半導体装置の製造方法

Also Published As

Publication number Publication date
KR100628932B1 (ko) 2006-09-27
US6117786A (en) 2000-09-12
JP2002514012A (ja) 2002-05-14
TWI222136B (en) 2004-10-11
KR20010043324A (ko) 2001-05-25
EP1078395A1 (en) 2001-02-28
WO1999057757A1 (en) 1999-11-11

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