JP4728238B2 - 相互接続部のテストを実施するための方法および装置 - Google Patents

相互接続部のテストを実施するための方法および装置 Download PDF

Info

Publication number
JP4728238B2
JP4728238B2 JP2006526063A JP2006526063A JP4728238B2 JP 4728238 B2 JP4728238 B2 JP 4728238B2 JP 2006526063 A JP2006526063 A JP 2006526063A JP 2006526063 A JP2006526063 A JP 2006526063A JP 4728238 B2 JP4728238 B2 JP 4728238B2
Authority
JP
Japan
Prior art keywords
pattern
component
controller
interconnect
communication path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006526063A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007506160A5 (https=
JP2007506160A (ja
Inventor
ユング,フィリップ
Original Assignee
ラムバス・インコーポレーテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ラムバス・インコーポレーテッド filed Critical ラムバス・インコーポレーテッド
Publication of JP2007506160A publication Critical patent/JP2007506160A/ja
Publication of JP2007506160A5 publication Critical patent/JP2007506160A5/ja
Application granted granted Critical
Publication of JP4728238B2 publication Critical patent/JP4728238B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544Scanning methods, algorithms and patterns
    • G01R31/31855Interconnection testing, e.g. crosstalk, shortcircuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2006526063A 2003-09-15 2004-06-29 相互接続部のテストを実施するための方法および装置 Expired - Fee Related JP4728238B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/663,572 2003-09-15
US10/663,572 US7031868B2 (en) 2003-09-15 2003-09-15 Method and apparatus for performing testing of interconnections
PCT/US2004/021369 WO2005036190A1 (en) 2003-09-15 2004-06-29 Method and apparatus for performing testing of interconnections

Publications (3)

Publication Number Publication Date
JP2007506160A JP2007506160A (ja) 2007-03-15
JP2007506160A5 JP2007506160A5 (https=) 2007-09-06
JP4728238B2 true JP4728238B2 (ja) 2011-07-20

Family

ID=34274411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006526063A Expired - Fee Related JP4728238B2 (ja) 2003-09-15 2004-06-29 相互接続部のテストを実施するための方法および装置

Country Status (4)

Country Link
US (2) US7031868B2 (https=)
JP (1) JP4728238B2 (https=)
CN (1) CN1849520B (https=)
WO (1) WO2005036190A1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007526992A (ja) * 2003-07-09 2007-09-20 イスラーユック エレクトロニクス リミテッド 電気故障検出のためのシステム、装置、及び方法
US7478005B2 (en) 2005-04-28 2009-01-13 Rambus Inc. Technique for testing interconnections between electronic components
US9053164B2 (en) * 2005-05-05 2015-06-09 International Business Machines Corporation Method, system, and program product for using analysis views to identify data synchronization problems between databases
US7375541B1 (en) * 2005-11-08 2008-05-20 Mediatek Inc. Testing method utilizing at least one signal between integrated circuits, and integrated circuit and testing system thereof
US20080204040A1 (en) * 2007-02-28 2008-08-28 Harry Muljono Systems and arrangements for determining properties of a transmission path
US7791982B2 (en) * 2007-06-29 2010-09-07 Karr Lawrence J Impact energy powered golf ball transmitter
US9501302B1 (en) * 2008-06-06 2016-11-22 Amdocs Software Systems Limited System, method, and computer program for combining results of event processing received from a plurality of virtual servers
US8850458B1 (en) * 2008-06-06 2014-09-30 Amdocs Software Systems Limited System, method, and computer program for combining results of event processing received from a plurality of servers
JP5655534B2 (ja) * 2009-12-18 2015-01-21 日本電波工業株式会社 電圧制御可変容量及び電圧制御発振器
US8495758B2 (en) * 2010-06-18 2013-07-23 Alcatel Lucent Method and apparatus for providing scan chain security
CN101995546B (zh) * 2010-11-16 2013-02-27 复旦大学 基于边界扫描的可编程逻辑器件自动测试系统与方法
CN102435797A (zh) * 2011-09-29 2012-05-02 上海交通大学 示波器无线探头
US9190146B2 (en) 2013-02-28 2015-11-17 Kabushiki Kaisha Toshiba Variable resistance memory system with redundancy lines and shielded bit lines
US9454499B2 (en) 2013-06-11 2016-09-27 Intel Corporation Asynchronous communication between devices
CN104502835B (zh) * 2014-12-09 2017-05-17 中国航空工业集团公司第六三一研究所 一种串行链路片内信号质量示波电路及方法
US9768834B2 (en) * 2015-02-11 2017-09-19 International Business Machines Corporation Parallel testing of a controller area network bus cable
CN109901044B (zh) * 2017-12-07 2021-11-12 英业达科技有限公司 多电路板的中央处理单元差分测试系统及其方法
CN109901048B (zh) * 2017-12-09 2021-04-27 英业达科技有限公司 以不同扫描链测试差分线路的系统及其方法
CN112305398A (zh) 2019-08-01 2021-02-02 富港电子(东莞)有限公司 自动化电路板测试系统及其方法
CN110412403B (zh) * 2019-08-07 2021-09-17 中核控制系统工程有限公司 核安全级系统通用输入输出端口动态诊断电路及方法
US11204849B2 (en) * 2020-03-13 2021-12-21 Nvidia Corporation Leveraging low power states for fault testing of processing cores at runtime

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02247754A (ja) * 1989-03-20 1990-10-03 Pfu Ltd メモリシステムの断線検出処理装置
US5624741A (en) * 1990-05-31 1997-04-29 E. I. Du Pont De Nemours And Company Interconnect structure having electrical conduction paths formable therein
JPH0436857A (ja) * 1990-06-01 1992-02-06 Oki Electric Ind Co Ltd マルチプロセッサシステムにおけるバス診断方式
JPH06249919A (ja) 1993-03-01 1994-09-09 Fujitsu Ltd 半導体集積回路装置の端子間接続試験方法
JPH09237164A (ja) * 1996-03-04 1997-09-09 Oki Electric Ind Co Ltd 半導体ディスク装置
US5717701A (en) * 1996-08-13 1998-02-10 International Business Machines Corporation Apparatus and method for testing interconnections between semiconductor devices
WO1999039218A2 (en) * 1998-02-02 1999-08-05 Koninklijke Philips Electronics N.V. Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit
AR022137A1 (es) 1998-12-31 2002-09-04 Kimberly Clark Co Una composicion de materia, una pelicula y un articulo que comprenden dicha composicion
JP3771393B2 (ja) * 1999-04-30 2006-04-26 富士通株式会社 半導体記憶装置、この半導体記憶装置を搭載した回路基板、および、この半導体記憶装置の接続試験方法
DE10005161A1 (de) * 1999-04-30 2000-11-02 Fujitsu Ltd Halbleiter-Speicheranordnung, Leiterplatte, auf welcher eine Halbleiter-Speicheranordnung montiert ist, und Verfahren zum Testen der Zwischenverbindung zwischen einer Halbleiter-Speicheranordnung und einer Leiterplatte
US6609221B1 (en) * 1999-08-31 2003-08-19 Sun Microsystems, Inc. Method and apparatus for inducing bus saturation during operational testing of busses using a pattern generator
US6505317B1 (en) * 2000-03-24 2003-01-07 Sun Microsystems, Inc. System and method for testing signal interconnections using built-in self test
US6885209B2 (en) * 2002-08-21 2005-04-26 Intel Corporation Device testing
US7047458B2 (en) * 2002-12-16 2006-05-16 Intel Corporation Testing methodology and apparatus for interconnects

Also Published As

Publication number Publication date
CN1849520B (zh) 2012-01-11
US20050060116A1 (en) 2005-03-17
CN1849520A (zh) 2006-10-18
US7031868B2 (en) 2006-04-18
US20060167646A1 (en) 2006-07-27
WO2005036190A1 (en) 2005-04-21
JP2007506160A (ja) 2007-03-15

Similar Documents

Publication Publication Date Title
JP4728238B2 (ja) 相互接続部のテストを実施するための方法および装置
US7139957B2 (en) Automatic self test of an integrated circuit component via AC I/O loopback
EP1266236B1 (en) System and method for testing signal interconnections using built-in self test
US6256760B1 (en) Automatic test equipment scan test enhancement
US7412342B2 (en) Low cost test for IC's or electrical modules using standard reconfigurable logic devices
CN1329833C (zh) 用于容错和柔性测试签名生成器的方法和装置
EP2389596A1 (en) Fault testing for interconnections
US6347387B1 (en) Test circuits for testing inter-device FPGA links including a shift register configured from FPGA elements to form a shift block through said inter-device FPGA links
EP3660526B1 (en) Test system with embedded tester
US20050258856A1 (en) High-speed interface circuit test module, module under high-speed interface circuit test, and high-speed interface circuit test method
CN107045100B (zh) 片上测试图案生成
US9043662B2 (en) Double data rate memory physical interface high speed testing using self checking loopback
CN106610462A (zh) 电子系统、系统诊断电路与其操作方法
KR101452959B1 (ko) 실장형 테스트 장비 및 그 방법
US6880118B2 (en) System and method for testing operational transmissions of an integrated circuit
KR20190066482A (ko) 인터포저를 사용하는 번 인 테스트 장치 및 테스트 방법
US6986087B2 (en) Method and apparatus for improving testability of I/O driver/receivers
Ungar et al. High-speed I/O capabilities added to military automatic test equipment (ATE) using synthetic instruments
CN100416284C (zh) 一种电缆测试装置及方法
US20030149913A1 (en) Method and apparatus for efficient burn-in of electronic circuits
US20030163774A1 (en) Method, apparatus, and system for efficient testing
Chakraborty et al. A practical approach to comprehensive system test & debug using boundary scan based test architecture
CN114585933B (zh) 用于存储测试系统中的设备接口的校准数据的方法、设备接口、测试系统和计算机程序
CN116593864A (zh) 测试方法和集成电路装置
Ley et al. Defect coverage for non-intrusive board tests

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070629

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070629

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090611

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090918

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20091218

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091228

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100118

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101110

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110209

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110217

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110310

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110331

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110414

R150 Certificate of patent or registration of utility model

Ref document number: 4728238

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140422

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees