JP4679273B2 - クロックデータリカバリ回路 - Google Patents

クロックデータリカバリ回路 Download PDF

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Publication number
JP4679273B2
JP4679273B2 JP2005196489A JP2005196489A JP4679273B2 JP 4679273 B2 JP4679273 B2 JP 4679273B2 JP 2005196489 A JP2005196489 A JP 2005196489A JP 2005196489 A JP2005196489 A JP 2005196489A JP 4679273 B2 JP4679273 B2 JP 4679273B2
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JP
Japan
Prior art keywords
clock
vdl
code
value
control code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005196489A
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English (en)
Japanese (ja)
Other versions
JP2007019630A5 (enExample
JP2007019630A (ja
Inventor
将 石井
尊則 廣田
敦彦 石橋
康 早川
毅 大下
賀之 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005196489A priority Critical patent/JP4679273B2/ja
Priority to US11/477,597 priority patent/US7822158B2/en
Publication of JP2007019630A publication Critical patent/JP2007019630A/ja
Publication of JP2007019630A5 publication Critical patent/JP2007019630A5/ja
Priority to US12/883,272 priority patent/US8175205B2/en
Application granted granted Critical
Publication of JP4679273B2 publication Critical patent/JP4679273B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2005196489A 2005-07-05 2005-07-05 クロックデータリカバリ回路 Expired - Fee Related JP4679273B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005196489A JP4679273B2 (ja) 2005-07-05 2005-07-05 クロックデータリカバリ回路
US11/477,597 US7822158B2 (en) 2005-07-05 2006-06-30 Clock data recovery circuit capable of generating clock signal synchronized with data signal
US12/883,272 US8175205B2 (en) 2005-07-05 2010-09-16 Clock data recovery circuit capable of generating clock signal synchronized with data signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005196489A JP4679273B2 (ja) 2005-07-05 2005-07-05 クロックデータリカバリ回路

Publications (3)

Publication Number Publication Date
JP2007019630A JP2007019630A (ja) 2007-01-25
JP2007019630A5 JP2007019630A5 (enExample) 2008-08-14
JP4679273B2 true JP4679273B2 (ja) 2011-04-27

Family

ID=37678491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005196489A Expired - Fee Related JP4679273B2 (ja) 2005-07-05 2005-07-05 クロックデータリカバリ回路

Country Status (2)

Country Link
US (2) US7822158B2 (enExample)
JP (1) JP4679273B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7240231B2 (en) * 2002-09-30 2007-07-03 National Instruments Corporation System and method for synchronizing multiple instrumentation devices
US7801258B2 (en) * 2007-04-02 2010-09-21 National Instruments Corporation Aligning timebases to share synchronized periodic signals
KR101341924B1 (ko) * 2011-10-21 2013-12-19 포항공과대학교 산학협력단 정전식 터치센서
US8855179B1 (en) 2012-05-24 2014-10-07 Pmc-Sierra Us, Inc. Measuring impairments of digitized signals in data and timing recovery circuits
US9265458B2 (en) 2012-12-04 2016-02-23 Sync-Think, Inc. Application of smooth pursuit cognitive testing paradigms to clinical drug development
US9380976B2 (en) 2013-03-11 2016-07-05 Sync-Think, Inc. Optical neuroinformatics
KR101597235B1 (ko) * 2014-11-26 2016-02-24 라이트웍스 주식회사 수동형 광 네트워크의 클럭 데이터 회복용 클럭 제공 장치
KR101597233B1 (ko) * 2014-11-26 2016-02-24 라이트웍스 주식회사 버스트 모드 클럭 데이터 회복 회로
US9379880B1 (en) * 2015-07-09 2016-06-28 Xilinx, Inc. Clock recovery circuit
CN110798854B (zh) * 2018-08-03 2021-10-26 上海华为技术有限公司 一种时钟状态检测方法及装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358741A (en) * 1979-09-17 1982-11-09 Ilc Data Device Corporation Micro time and phase stepper
JP2844921B2 (ja) * 1990-11-30 1999-01-13 カシオ計算機株式会社 ビット同期回路
JPH06296184A (ja) * 1993-04-08 1994-10-21 Fujitsu Ltd クロック再生回路
JP3159585B2 (ja) * 1993-12-07 2001-04-23 三菱電機株式会社 クロック抽出回路
US6316966B1 (en) * 1999-07-16 2001-11-13 Conexant Systems, Inc. Apparatus and method for servo-controlled self-centering phase detector
US6807225B1 (en) * 2000-05-31 2004-10-19 Conexant Systems, Inc. Circuit and method for self trimming frequency acquisition
US6331792B1 (en) * 2000-06-30 2001-12-18 Conexant Systems, Inc. Circuit and method for unlimited range frequency acquisition
US6377082B1 (en) * 2000-08-17 2002-04-23 Agere Systems Guardian Corp. Loss-of-signal detector for clock/data recovery circuits
JP3450293B2 (ja) * 2000-11-29 2003-09-22 Ｎｅｃエレクトロニクス株式会社 クロック制御回路及びクロック制御方法
US7099424B1 (en) * 2001-08-28 2006-08-29 Rambus Inc. Clock data recovery with selectable phase control
US7515656B2 (en) * 2002-04-15 2009-04-07 Fujitsu Limited Clock recovery circuit and data receiving circuit
US7127022B1 (en) * 2003-03-21 2006-10-24 Xilinx, Inc. Clock and data recovery circuits utilizing digital delay lines and digitally controlled oscillators
KR100541548B1 (ko) * 2003-09-08 2006-01-11 삼성전자주식회사 대역 확산 클럭 발생회로 및 방법

Also Published As

Publication number Publication date
US20110007855A1 (en) 2011-01-13
US7822158B2 (en) 2010-10-26
JP2007019630A (ja) 2007-01-25
US20070018704A1 (en) 2007-01-25
US8175205B2 (en) 2012-05-08

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