JP4663470B2 - 半導体素子内蔵型多層回路基板 - Google Patents
半導体素子内蔵型多層回路基板 Download PDFInfo
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- JP4663470B2 JP4663470B2 JP2005286440A JP2005286440A JP4663470B2 JP 4663470 B2 JP4663470 B2 JP 4663470B2 JP 2005286440 A JP2005286440 A JP 2005286440A JP 2005286440 A JP2005286440 A JP 2005286440A JP 4663470 B2 JP4663470 B2 JP 4663470B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73267—Layer and HDI connectors
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- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2924/01—Chemical elements
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- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Description
このような構成にすることにより、凹部内に収容した半導体素子と絶縁性基材との密着力が阻害されたり、凹部内における半導体素子の安定性が悪くなるようなことがなくなる。
しかも、半導体素子内蔵型基板の複数を重ね合わせたのち、一体化させたときの位置ずれがなくなり、多層回路基板の品質が向上する。
さらにまた、半導体素子に応力がかかることもないため素子内部に結晶欠陥が発生したりしてデバイス特性が劣化することもない。
そして、複数個の半導体素子内蔵型基板を積層して一体化する際、積層された半導体素子内蔵型基板どうしは、導電性バンプによって電気的に接続される。
以下、半導体素子内蔵型基板の構成をさらに詳しく説明する。
スルーホールと半導体素子とは、この半導体素子上に形成された電極パッドとスルーホールに対応して形成されたスルーホールパッドとの間に導体配線を形成することにより電気的に接続される。この導体配線は、半導体素子と絶縁性基材の表面を被覆しかつ前記各パッドに対応した位置に開口部を設けてなる絶縁層の表面に沿って形成され、スルーホールパッドと電極パッドとを電気的に接続する。この導体配線によって半導体素子内蔵型基板内の電気的な接続が行われる。
即ち、このような半導体素子内蔵型基板は、ほぼ同じ構造を有する他の半導体素子内蔵型基板と共に積層され、必要に応じて接着剤を介して、一体化され、高密度化および高機能化された多層回路基板にされる。
なお、導電性ペーストとしては、金属粒子に、エポキシ樹脂などの熱硬化性樹脂や、ポリフェニレンスルフィド(PPS)樹脂を加えた有機系導電性ペーストが好ましい。
前記共重合体を合成する場合の単量体としては、例えば、エチレン、プロピレンなどがある。その中でも熱硬化性シクロオレフィン系樹脂であることが望ましい。加熱を行って架橋を形成させることにより、より剛性が高くなり機械的特性が向上するからである。
この他に、導電性バンプは、低融点金属であるはんだペーストを印刷する方法や、はんだめっきを行う方法、あるいははんだ溶融液に浸漬する方法によって形成することができる。上記低融点金属としては、Pb−Sn系はんだ、Ag−Sn系はんだ、インジウムはんだ等を使用することができる。
ここで、有機系接着剤の溶剤としては、NMP、DMF、アセトン、エタノールを用いることができる。
上記接着剤層の厚さは、5〜50μmが望ましい。接着剤層は、取扱が容易になるため、予備硬化(プレキュア)しておくことが好ましい。
半導体素子内蔵型多層回路基板を、下記(1)〜(17)の工程にしたがって製造した。特性をまとめて表1に示した。
(1) 窒化アルミニウム粉末(トクヤマ社製、平均粒径1.1μm):100質量部、イットリア(平均粒径0.4μm):4質量部、ショ糖:0.2質量部、および1−ブタノールおよびエタノール:計53質量部からなる混合物をドクターブレード法を用いて成形し、グリーンシート10を得た(図1(a)参照)。
表2の結果より、得られた半導体素子内蔵型多層回路基板は、最外層(50D)の半導体素子と最内層(50A)の半導体素子との温度差が小さく、放熱特性に優れ、良好に作動することが認められた。
上記(7)の工程を下記工程(A)に替えた以外は、実施例1と同様にして半導体素子内蔵型多層回路基板を製造した。特性は、表1に示したとおりである。
(A) 上記(5)で得た凹部25に位置する部位に開口を設けたステンレス製のメタルマスクをマスクとして、凹部25の内壁にAuを1〜10μmの厚さで蒸着する。次に、このAu膜上に、ダイシングによりチップ状に成形された半導体素子26(シリコン基材:25〜450℃における熱膨張率4.6×10-6/K)を嵌め込み、これを窒素雰囲気中で400℃、10分間加熱処理し、凹部25の内壁に蒸着したAu膜と半導体素子26との間にAuとSiとの共晶を形成させることで、半導体素子26を凹部25の内壁に接着・固定した。その際、半導体素子26の電極パッド27の表面が、絶縁性基材1の第1の表面に形成したスルーホールパッド40の表面とほぼ同一の平面上にあるように固定した。
表2の結果より、得られた半導体素子内蔵型多層回路基板は、最外層(50D)の半導体素子と最内層(50A)の半導体素子との温度差が小さく、放熱特性に優れ、良好に作動することが認められた。
上記(14)の工程を下記(B)の工程に代えた以外は、実施例1と同様にして半導体素子内蔵型多層回路基板を製造した。特性は、表1に示したとおりである。
(B)絶縁性基材1の第1の表面とは反対側の表面(以下、「第2の表面」という)のスルーホール20上に、低融点金属であるスズ−銀系はんだからなる導電性ペーストを用いて、印刷によって、直径80μm、高さ30μm、ピッチ600μmで導電性バンプ44を形成した。
本実施例では、それぞれ熱膨張率、熱伝導率、板厚および凹部の厚さの異なる窒化アルミニウム焼結体からなる絶縁性基材を用いて半導体素子内蔵型多層回路基板を製造した。特性は、表1に示したとおりである。
半導体素子26の電極パッド27表面と、絶縁性基材1のスルーホールパッド40表面との段差を変えた以外は、上記実施例1と同様にして半導体素子内蔵型多層回路基板を製造した。特性を表1に示した。
絶縁性基材1として面方向の熱膨張率が15×10-5/Kのガラス・エポキシ樹脂複合材料を用いて製造した半導体素子内蔵型多層回路基板について、最外層(50D)の半導体素子直上の表面温度と、最内層(50A)半導体素子の温度を測定した。その結果、半導体素子内蔵型多層回路基板は、過昇温(200℃超)により破損してしまった(表1および表2参照)。
10 グリーンシート
16 スルーホール用貫通孔
17 PETフィルム
20 充填スルーホール
25 半導体素子収容凹部
26 半導体素子
27 電極パッド
30 樹脂絶縁層
32、34 開口
40 スルーホールパッド
42 接続配線パターン
44 導電性バンプ
46 接着剤層
50A〜50D 半導体素子内蔵基板
Claims (6)
- 絶縁性基材に設けた凹部内に半導体素子を収容してなる半導体素子内蔵型基板の複数個を積層して形成した多層回路基板であって、
前記絶縁性基材が、高熱伝導性セラミックスからなると共に、この絶縁性基材の熱膨張率と前記半導体素子の熱膨張率との、20〜300℃の温度域における差が、1×10−5/K未満であり、かつ、
前記半導体素子内蔵型基板は、絶縁性基材の上下面を電気的に接続するためのスルーホールと、そのスルーホールに対応して設けられたスルーホールパッドと、半導体素子表面に設けられた電極パッドと、半導体素子と絶縁性基材の表面を被覆する絶縁層と、この絶縁層の表面に沿って形成され、前記スルーホールパッドと半導体素子の電極パッドとを接続する導体配線と、を有し、
該導体配線が、絶縁層の前記各パッドに対応した位置にそれぞれ設けられた、めっき充填されてなる開口部を介して電気的に接続されていることを特徴とする半導体素子内蔵型多層回路基板。 - 半導体素子内蔵型基板どうしが、導電性バンプによって電気的に接続されてなることを特徴とする請求項1に記載の半導体素子内蔵型多層回路基板。
- 前記凹部の底部厚みが、10〜250μmであることを特徴とする請求項1または2に記載の半導体素子内蔵型多層回路基板。
- 前記高熱伝導性セラミックスは、熱伝導率が100W/(m・K)以上のセラミックスであることを特徴とする請求項1〜3のいずれか1項に記載の半導体素子内蔵型多層回路基板。
- 前記高熱伝導性セラミックスが、窒化アルミニウムであることを特徴とする請求項1〜4のいずれか1項に記載の半導体素子内蔵型多層回路基板。
- 前記絶縁性基材の凹部内に収容した半導体素子の表面と、該絶縁性基材の表面との段差が10μm以内であることを特徴とする請求項1〜5のいずれか1項に記載の半導体素子内蔵型多層回路基板。
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