JP4643223B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4643223B2 JP4643223B2 JP2004316419A JP2004316419A JP4643223B2 JP 4643223 B2 JP4643223 B2 JP 4643223B2 JP 2004316419 A JP2004316419 A JP 2004316419A JP 2004316419 A JP2004316419 A JP 2004316419A JP 4643223 B2 JP4643223 B2 JP 4643223B2
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- Prior art keywords
- stress
- silicon nitride
- nitride film
- region
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 46
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 46
- 239000000758 substrate Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000004088 simulation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000013401 experimental design Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000002068 genetic effect Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
Description
以下、図1−図4を参照して実施例によるMOSトランジスタの素子分離構造を製造方法と共に説明する。この実施例においては、トレンチ内にシリコン窒化膜(SiN)を有し、n−MOS素子のトレンチ内シリコン窒化膜にはイオン注入を施さず、p−MOS素子のトレンチ内のシリコン窒化膜のみにイオン注入を施した構造を有している。
Claims (4)
- 半導体基板と、
前記半導体基板に形成され、活性領域を分離するトレンチの内壁に形成された絶縁膜と、
前記絶縁膜上に形成されたシリコン窒化膜と、
前記トレンチ内に埋設されたシリコン酸化膜とを具備し、
前記シリコン窒化膜の少なくとも一部分は結晶構造が破壊されて応力制御し、前記トレンチにより分離された活性領域はn−MOS素子用の第1の領域とp−MOS用の第2の領域とを含み、前記第2の領域における前記シリコン窒化膜に対してイオン注入されていることを特徴とする半導体装置。 - 前記第2の領域における電流方向と応力方向とが互いに平行であることを特徴とする請求項1記載の半導体装置。
- 前記イオン注入を行うイオン種はGe、As、Si、N、C及びFから選択された1つであることを特徴とする請求項2記載の半導体装置。
- 前記第2の領域における前記シリコン窒化膜の端面の前記半導体基板表面からの距離は前記第1の領域のそれよりも後退していることを特徴とする請求項1乃至3のいずれか1つ記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004316419A JP4643223B2 (ja) | 2004-10-29 | 2004-10-29 | 半導体装置 |
US11/260,480 US20060091475A1 (en) | 2004-10-29 | 2005-10-28 | Semiconductor device |
US12/263,830 US7605442B2 (en) | 2004-10-29 | 2008-11-03 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004316419A JP4643223B2 (ja) | 2004-10-29 | 2004-10-29 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006128477A JP2006128477A (ja) | 2006-05-18 |
JP4643223B2 true JP4643223B2 (ja) | 2011-03-02 |
Family
ID=36260834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004316419A Expired - Fee Related JP4643223B2 (ja) | 2004-10-29 | 2004-10-29 | 半導体装置 |
Country Status (2)
Country | Link |
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US (2) | US20060091475A1 (ja) |
JP (1) | JP4643223B2 (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8407634B1 (en) * | 2005-12-01 | 2013-03-26 | Synopsys Inc. | Analysis of stress impact on transistor performance |
JP2007189110A (ja) * | 2006-01-13 | 2007-07-26 | Sharp Corp | 半導体装置及びその製造方法 |
JP5182703B2 (ja) | 2006-06-08 | 2013-04-17 | 日本電気株式会社 | 半導体装置 |
JP5096719B2 (ja) * | 2006-09-27 | 2012-12-12 | パナソニック株式会社 | 回路シミュレーション方法及び回路シミュレーション装置 |
DE102006046377A1 (de) * | 2006-09-29 | 2008-04-03 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit Isoliergräben, die unterschiedliche Arten an Verformung hervorrufen |
KR101026479B1 (ko) * | 2006-12-28 | 2011-04-01 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
US7521763B2 (en) * | 2007-01-03 | 2009-04-21 | International Business Machines Corporation | Dual stress STI |
JP2008306139A (ja) * | 2007-06-11 | 2008-12-18 | Elpida Memory Inc | 半導体装置の素子分離構造の形成方法、半導体装置の素子分離構造及び半導体記憶装置 |
US8492846B2 (en) | 2007-11-15 | 2013-07-23 | International Business Machines Corporation | Stress-generating shallow trench isolation structure having dual composition |
US9639479B2 (en) * | 2009-09-23 | 2017-05-02 | Nvidia Corporation | Instructions for managing a parallel cache hierarchy |
US8772127B2 (en) * | 2010-12-29 | 2014-07-08 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and method for manufacturing the same |
US8921944B2 (en) * | 2011-07-19 | 2014-12-30 | United Microelectronics Corp. | Semiconductor device |
US8778758B2 (en) | 2012-08-30 | 2014-07-15 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device and semiconductor device |
US9190346B2 (en) | 2012-08-31 | 2015-11-17 | Synopsys, Inc. | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits |
US9817928B2 (en) | 2012-08-31 | 2017-11-14 | Synopsys, Inc. | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits |
US9379018B2 (en) | 2012-12-17 | 2016-06-28 | Synopsys, Inc. | Increasing Ion/Ioff ratio in FinFETs and nano-wires |
US8847324B2 (en) | 2012-12-17 | 2014-09-30 | Synopsys, Inc. | Increasing ION /IOFF ratio in FinFETs and nano-wires |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000216377A (ja) * | 1999-01-20 | 2000-08-04 | Nec Corp | 半導体装置の製造方法 |
WO2002043151A1 (en) * | 2000-11-22 | 2002-05-30 | Hitachi, Ltd | Semiconductor device and method for fabricating the same |
JP2003158241A (ja) * | 2001-11-26 | 2003-05-30 | Hitachi Ltd | 半導体装置及び製造方法 |
JP2003273206A (ja) * | 2002-03-18 | 2003-09-26 | Fujitsu Ltd | 半導体装置とその製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3691963B2 (ja) * | 1998-05-28 | 2005-09-07 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2000133700A (ja) * | 1998-10-22 | 2000-05-12 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6541350B2 (en) * | 2000-11-08 | 2003-04-01 | Macronix International Co., Ltd. | Method for fabricating shallow trench isolation |
JP2003179157A (ja) | 2001-12-10 | 2003-06-27 | Nec Corp | Mos型半導体装置 |
JP2003272306A (ja) | 2002-03-15 | 2003-09-26 | Tdk Corp | オーディオデータが記録された記録媒体、並びに、その再生方法及び再生装置 |
KR100443126B1 (ko) * | 2002-08-19 | 2004-08-04 | 삼성전자주식회사 | 트렌치 구조물 및 이의 형성 방법 |
KR100532503B1 (ko) * | 2004-02-03 | 2005-11-30 | 삼성전자주식회사 | 쉘로우 트렌치 소자 분리막의 형성 방법 |
JP2005251973A (ja) * | 2004-03-04 | 2005-09-15 | Fujitsu Ltd | 半導体装置の製造方法と半導体装置 |
JP4813778B2 (ja) * | 2004-06-30 | 2011-11-09 | 富士通セミコンダクター株式会社 | 半導体装置 |
-
2004
- 2004-10-29 JP JP2004316419A patent/JP4643223B2/ja not_active Expired - Fee Related
-
2005
- 2005-10-28 US US11/260,480 patent/US20060091475A1/en not_active Abandoned
-
2008
- 2008-11-03 US US12/263,830 patent/US7605442B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000216377A (ja) * | 1999-01-20 | 2000-08-04 | Nec Corp | 半導体装置の製造方法 |
WO2002043151A1 (en) * | 2000-11-22 | 2002-05-30 | Hitachi, Ltd | Semiconductor device and method for fabricating the same |
JP2003158241A (ja) * | 2001-11-26 | 2003-05-30 | Hitachi Ltd | 半導体装置及び製造方法 |
JP2003273206A (ja) * | 2002-03-18 | 2003-09-26 | Fujitsu Ltd | 半導体装置とその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2006128477A (ja) | 2006-05-18 |
US20090057777A1 (en) | 2009-03-05 |
US7605442B2 (en) | 2009-10-20 |
US20060091475A1 (en) | 2006-05-04 |
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