JP4635070B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4635070B2 JP4635070B2 JP2008086029A JP2008086029A JP4635070B2 JP 4635070 B2 JP4635070 B2 JP 4635070B2 JP 2008086029 A JP2008086029 A JP 2008086029A JP 2008086029 A JP2008086029 A JP 2008086029A JP 4635070 B2 JP4635070 B2 JP 4635070B2
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- 239000004065 semiconductor Substances 0.000 title claims description 44
- 229910052751 metal Inorganic materials 0.000 claims description 118
- 239000002184 metal Substances 0.000 claims description 117
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 102
- 229910021332 silicide Inorganic materials 0.000 claims description 101
- 239000013078 crystal Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 25
- 239000000203 mixture Substances 0.000 claims description 8
- 229910052720 vanadium Inorganic materials 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052703 rhodium Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 93
- 238000002955 isolation Methods 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 11
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000004151 rapid thermal annealing Methods 0.000 description 10
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 239000011259 mixed solution Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000005204 segregation Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Description
(半導体装置の構成)
図1は、本発明の第1の実施の形態に係る半導体装置の断面図である。この半導体装置1は、Si基板2上に形成されたウェル20と、Si基板2上にゲート絶縁膜3を介して形成されたゲート電極4と、ゲート電極4の上面に形成された第1のシリサイド層5と、ゲート電極4の側面に形成されたゲート側壁6と、Si基板2内のゲート電極4の下方に形成されたチャネル領域7と、Si基板2の表面近傍に形成されたエクステンション領域8aを含むソース・ドレイン領域8と、ソース・ドレイン領域8の上面に形成された第2のシリサイド層9と、Si基板2内に形成された素子分離領域10と、を有して概略構成される。
図5A(a)〜(c)および図5B(d)〜(f)は、本発明の第1の実施の形態に係る半導体装置の製造工程を示す断面図である。
本発明の第1の実施の形態によれば、ソース・ドレイン領域8の上面に設けられる第2のシリサイド層9と、ゲート電極4の上面に設けられる第1のシリサイド層5とで第2の金属元素の元素濃度を変えることにより、ゲート電極4上に低抵抗の第1のシリサイド層5が設けられ、ソース・ドレイン領域8上に成膜性に優れる第2のシリサイド層9が設けられるので、シリサイド層を設ける場所に応じて適切な特性を有するシリサイド層を備えた半導体装置1が得られる。
図6(a)〜(c)は、本発明の第2の実施の形態に係る半導体装置の製造工程を示す断面図である。第2の実施の形態では、スパッタリングによる第1の金属膜12および第2の金属膜15の形成に代えて、CVD法により第2の金属元素を含まないNi等の第1の金属元素からなる第2の金属膜15を形成し、更に第2の金属膜15を覆うようにCVD法により第2の金属元素からなる第3の金属膜16を設ける点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、簡単のために説明を省略する。
本発明の第2の実施の形態によれば、第1の実施の形態と同様にシリサイド層を設ける場所に応じて適切な特性を有するシリサイド層を備えた半導体装置1が得られる。
図7(a)〜(c)は、本発明の第3の実施の形態に係る半導体装置の製造工程を示す断面図である。第3の実施の形態は、ソース・ドレイン領域8の上面およびゲート電極4の上面に第2の金属元素を含まない第2の金属膜15を設けてシリサイド層を形成した後、ソース・ドレイン領域8にイオン注入によって第2の金属元素を混入させる点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、簡単のために説明を省略する。
本発明の第3の実施の形態によれば、ゲート電極4およびソース・ドレイン領域8に対するシリサイド層の形成後に、ソース・ドレイン領域8に選択的に第2の金属元素をイオン注入することによって、第1の実施の形態と同様にシリサイド層を設ける場所に応じて適切な特性を有するシリサイド層を備えた半導体装置1が得られる。
図8(a)〜(c)は、本発明の第4の実施の形態に係る半導体装置の製造工程を示す断面図である。第4の実施の形態では、ゲート電極4の上面にマスク膜11を形成し、第2の金属元素からなる第3の金属膜16の成膜に基づくソース・ドレイン領域8の上面のシリサイド化反応を行った後、第2の金属膜15の成膜に基づくゲート電極4の上面およびソース・ドレイン領域8の上面のシリサイド化反応を行う点において第1の実施の形態と異なる。なお、第1の実施の形態と同様の点については、簡単のために説明を省略する。
本発明の第4の実施の形態によれば、Ir等の第2の金属元素からなる第3の金属膜16によってソース・ドレイン領域8に対する第3のシリサイド層18を形成した後に、第2の金属膜15によるシリサイド化反応をゲート電極4の上面およびソース・ドレイン領域8に対して行うことで、第1の実施の形態と同様にシリサイド層を設ける場所に応じて適切な特性を有するシリサイド層を備えた半導体装置1が得られる。
本発明は、上記各実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。
Claims (4)
- 半導体基板と、
前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極上に形成された第1のシリサイド層と、
前記ゲート電極下方の前記半導体基板内に形成されたチャネル領域と、
前記半導体基板内の前記チャネル領域を挟んだ領域に形成されるソース・ドレイン領域と、
前記ソース・ドレイン領域上に形成されて前記第1のシリサイド層よりも結晶粒径の平均値が小さい、または結晶粒内の組成境界数の平均値が多い第2のシリサイド層と、
を有し、
前記第1および第2のシリサイド層を構成する結晶粒の少なくとも一部は、第1の金属元素およびSiからなる結晶子と第2の金属元素およびSiからなる結晶子とを含み、
前記第2のシリサイド層に含まれる前記第2の金属元素の元素濃度は、前記第1のシリサイド層に含まれる前記第2の金属元素の元素濃度よりも大であることを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極上に形成された第1のシリサイド層と、
前記ゲート電極下方の前記半導体基板内に形成されたチャネル領域と、
前記半導体基板内の前記チャネル領域を挟んだ領域に形成されるソース・ドレイン領域と、
前記ソース・ドレイン領域上に形成されて前記第1のシリサイド層よりも結晶粒径の平均値が小さい、または結晶粒内の組成境界数の平均値が多い第2のシリサイド層と、
を有し、
前記第2のシリサイド層を構成する結晶粒の少なくとも一部は、第1の金属元素およびSiからなる結晶子と第2の金属元素およびSiからなる結晶子とを含み、
前記第1のシリサイド層は、前記第2の金属元素を含まないことを特徴とする半導体装置。 - 前記第2のシリサイド層は、前記第2の金属元素の元素濃度が前記第1の金属元素に対して10〜50原子%であることを特徴とする請求項1または2に記載の半導体装置。
- 前記第1の金属元素は、V、Ti、Co、またはNiであり、
前記第2の金属元素は、Pd、Pt、Rh、In、Ir、またはRuであることを特徴とする請求項1から3のいずれかに記載の半導体装置。
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JP2008086029A JP4635070B2 (ja) | 2008-03-28 | 2008-03-28 | 半導体装置 |
US12/410,560 US20090243002A1 (en) | 2008-03-28 | 2009-03-25 | Semiconductor device and method of fabricating the same |
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JP5611574B2 (ja) | 2009-11-30 | 2014-10-22 | 株式会社東芝 | 抵抗変化メモリ及びその製造方法 |
JP5439147B2 (ja) * | 2009-12-04 | 2014-03-12 | 株式会社東芝 | 抵抗変化メモリ |
JP5161911B2 (ja) | 2010-03-25 | 2013-03-13 | 株式会社東芝 | 抵抗変化メモリ |
US8470700B2 (en) * | 2010-07-22 | 2013-06-25 | Globalfoundries Singapore Pte. Ltd. | Semiconductor device with reduced contact resistance and method of manufacturing thereof |
WO2016147316A1 (ja) | 2015-03-17 | 2016-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP6435030B2 (ja) * | 2017-09-29 | 2018-12-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Citations (4)
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JP2005019943A (ja) * | 2003-06-27 | 2005-01-20 | Samsung Electronics Co Ltd | ニッケル合金サリサイド工程、それを用いて半導体素子を製造する方法、これにより形成されたニッケル合金シリサイド膜及びそれを用いて製造された半導体素子 |
JP2005150267A (ja) * | 2003-11-13 | 2005-06-09 | Fujitsu Ltd | 半導体装置とその製造方法 |
JP2007053394A (ja) * | 2006-10-13 | 2007-03-01 | Fujitsu Ltd | 半導体装置とその製造方法 |
JP2008060101A (ja) * | 2006-08-29 | 2008-03-13 | Toshiba Corp | 半導体装置およびその製造方法 |
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US6620718B1 (en) * | 2000-04-25 | 2003-09-16 | Advanced Micro Devices, Inc. | Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device |
US6376320B1 (en) * | 2000-11-15 | 2002-04-23 | Advanced Micro Devices, Inc. | Method for forming field effect transistor with silicides of different thickness and of different materials for the source/drain and the gate |
JP2007214269A (ja) * | 2006-02-08 | 2007-08-23 | Sony Corp | 金属シリサイド形成方法および半導体装置の製造方法 |
JP2007335834A (ja) * | 2006-05-15 | 2007-12-27 | Toshiba Corp | 半導体装置およびその製造方法 |
US20070296052A1 (en) * | 2006-06-26 | 2007-12-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming silicide regions and resulting MOS devices |
US7737015B2 (en) * | 2007-02-27 | 2010-06-15 | Texas Instruments Incorporated | Formation of fully silicided gate with oxide barrier on the source/drain silicide regions |
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2008
- 2008-03-28 JP JP2008086029A patent/JP4635070B2/ja not_active Expired - Fee Related
-
2009
- 2009-03-25 US US12/410,560 patent/US20090243002A1/en not_active Abandoned
Patent Citations (4)
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JP2005019943A (ja) * | 2003-06-27 | 2005-01-20 | Samsung Electronics Co Ltd | ニッケル合金サリサイド工程、それを用いて半導体素子を製造する方法、これにより形成されたニッケル合金シリサイド膜及びそれを用いて製造された半導体素子 |
JP2005150267A (ja) * | 2003-11-13 | 2005-06-09 | Fujitsu Ltd | 半導体装置とその製造方法 |
JP2008060101A (ja) * | 2006-08-29 | 2008-03-13 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2007053394A (ja) * | 2006-10-13 | 2007-03-01 | Fujitsu Ltd | 半導体装置とその製造方法 |
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US20090243002A1 (en) | 2009-10-01 |
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