JP4619411B2 - 導電性リソグラフィーポリマー及びこれを用いたデバイスの作製方法 - Google Patents
導電性リソグラフィーポリマー及びこれを用いたデバイスの作製方法 Download PDFInfo
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- JP4619411B2 JP4619411B2 JP2007531196A JP2007531196A JP4619411B2 JP 4619411 B2 JP4619411 B2 JP 4619411B2 JP 2007531196 A JP2007531196 A JP 2007531196A JP 2007531196 A JP2007531196 A JP 2007531196A JP 4619411 B2 JP4619411 B2 JP 4619411B2
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- conductive
- film
- photolithography
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- photolithographic
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Images
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
- B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
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Description
(特許文献1) 米国特許第6078100号明細書
(特許文献2) 米国特許第5702566号明細書
(特許文献3) 米国特許第4650288号明細書
(特許文献4) 米国特許第6319643号明細書
(特許文献5) 欧州特許第130615号明細書
(特許文献6) 米国特許第3791858号明細書
(特許文献7) 米国特許第3306830号明細書
(特許文献8) 米国特許出願公開第2002/0150838号明細書
(特許文献9) 米国特許第6248658号明細書
(特許文献10) 米国特許第5300208号明細書
(特許文献11) 国際公開第01/33649号明細書
(特許文献12) 米国特許第5427841号明細書
(特許文献13) 米国特許第6331356号明細書
(特許文献14) 欧州特許第130612号明細書
Claims (28)
- デバイスを製作する方法であって、
第1の導電性フォトリソグラフィー膜を基板の上面に堆積させる段階と、
リソグラフィープロセスを用いて前記第1の導電性フォトリソグラフィー膜をパターニングして、第1の回路パターンを形成する段階と、
パターニングされた前記第1の導電性フォトリソグラフィー膜の上にめっき膜を形成する段階と、
を含む、
デバイスを製作する方法。 - 前記第1の導電性フォトリソグラフィー膜を基板の上面に堆積させる段階の前に、1以上のバイア(via)を有する第1の誘電体層を基板の表面に形成する段階をさらに含み、
前記第1の誘電体層が前記基板を前記第1の導電性フォトリソグラフィー膜から絶縁し、
前記第1の導電性フォトリソグラフィー膜が前記第1の誘電体層の表面に形成される、
請求項1に記載のデバイスを製作する方法。 - 前記基板が、内部に導電性素子が形成された1以上の造作部(feature)をさらに含み、
前記バイアが前記導電性素子との電気的相互接続を可能にする、
請求項2に記載のデバイスを製作する方法。 - 前記第1の導電性フォトリソグラフィー膜を前記導電性素子と相互接続させる段階をさらに含む、
請求項3に記載のデバイスを製作する方法。 - さらなる導電性膜を、前記第1の導電性フォトリソグラフィー膜の前記第1の回路パターン上に形成する段階と、
前記バイアにより、前記さらなる導電性膜を前記導電性素子と相互接続させる段階と、
をさらに含む、
請求項4に記載のデバイスを製作する方法。 - 前記さらなる導電性膜を形成することが、電解プロセスを使用することを含む、
請求項5に記載のデバイスを製作する方法。 - 第2の導電性フォトリソグラフィー膜を前記基板の底面に堆積させる段階と、
リソグラフィープロセスを用いて前記第2の導電性フォトリソグラフィー膜をパターニングして、第2の回路パターン形成する段階と、
をさらに含む、
請求項1から請求項6までの何れか一項に記載のデバイスを製作する方法。 - 前記第2の導電性フォトリソグラフィー膜を堆積させる段階の前に、前記基板の底面に1以上のバイアを有する第2の誘電体層を形成する段階をさらに含み、
前記第2の誘電体層が前記基板の底面を前記第2の導電性フォトリソグラフィー膜から絶縁し、
前記第2の導電性フォトリソグラフィー膜が前記第2の誘電体層の表面に形成される、
請求項7に記載のデバイスを製作する方法。 - 前記基板が、内部に導電性素子が形成された1以上の造作部をさらに含み、
前記バイアが前記導電性素子との電気的相互接続を可能にする、
請求項8に記載のデバイスを製作する方法。 - 前記第2の導電性フォトリソグラフィー膜を前記導電性素子と相互接続させる段階をさらに含む、
請求項9に記載のデバイスを製作する方法。 - さらなる導電性膜を、前記第2の導電性フォトリソグラフィー膜の前記第2の回路パターン上に形成する段階と、
前記バイアにより、前記さらなる導電性膜を前記導電性素子と相互接続させる段階と、
をさらに含む、
請求項10に記載のデバイスを製作する方法。 - 前記さらなる導電性膜を形成することが、電解プロセスを使用することを含む、
請求項11に記載のデバイスを製作する方法。 - 前記第1の導電性フォトリソグラフィー膜を基板の上面に堆積させる段階が、プリント回路基板の基板の上面に、前記第1の導電性フォトリソグラフィー膜を堆積させる段階を含む、
請求項1から請求項12までの何れか一項に記載のデバイスを製作する方法。 - 電子デバイスであって、
基板と、
前記基板の表面に形成される誘電体層と、
前記誘電体層の表面に形成され、パターニングされて回路パターンを形成する導電性フォトリソグラフィー膜と、
パターニングされた前記導電性フォトリソグラフィー膜の上に形成されるめっき膜と、
を備える、
電子デバイス。 - 前記導電性フォトリソグラフィー膜が、
エポキシアクリレート、熱硬化剤及び導電性ポリマーの混合物を50重量%〜60重量%;
リソグラフィー反応性成分を20重量%〜30重量%;
光活性材料を10重量%〜15重量%
導電性フォトリソグラフィーポリマーの導電率を高める添加剤を3重量%〜5重量%
含む、
請求項14に記載の電子デバイス。 - 前記基板が、内部に導電性素子が形成された1つ又は複数の造作部をさらに備え、
前記誘電体層がそれを貫通するように創出されたバイアを有し、
前記バイアが前記導電性素子との電気的相互接続を可能にし、
前記導電性フォトリソグラフィー膜が前記バイアを介して前記導電性素子と電気的に相互接続される、
請求項14または請求項15に記載の電子デバイス。 - 前記導電性フォトリソグラフィー膜の回路パターン上に形成されるさらなる導電性膜をさらに含み、
前記さらなる導電性膜が前記バイアを介して前記導電性素子と相互接続される、
請求項16に記載の電子デバイス。 - 前記導電性フォトリソグラフィー膜が導電性のポリマーを含む、
請求項14から請求項17までの何れか一項に記載の電子デバイス。 - 前記基板が、プリント回路基板の基板を含む、
請求項14から請求項18までの何れか一項に記載の電子デバイス。 - 前記導電性フォトリソグラフィー膜が、レジストを含む、
請求項14から請求項19までの何れか一項に記載の電子デバイス。 - 前記導電性フォトリソグラフィー膜が、金属の粉末および炭素の粉末の少なくとも一方を含む、
請求項14から請求項20までの何れか一項に記載の電子デバイス。 - 導電性フォトリソグラフィー膜が、前記基板の上面に形成される第1の導電性フォトリソグラフィー膜と、前記基板の底面に形成される第2の導電性フォトリソグラフィー膜とを含む、
請求項14から請求項21までの何れか一項に記載の電子デバイス。 - 前記めっき層と、前記導電性フォトリソグラフィー膜との間に形成された無電解めっき膜の一部が除去されて得られる、
請求項14から請求項22までの何れか一項に記載の電子デバイス。 - 前記導電性フォトリソグラフィー膜が、ナノサイズの金属粉末を含む、
請求項14から請求項23までの何れか一項に記載の電子デバイス。 - デバイスを製作する方法であって、
基板の上面に形成される第1の絶縁層の表面に、第1の導電性フォトリソグラフィー膜を堆積させる段階と、
回路パターンに従って前記第1の導電性フォトリソグラフィー膜をマスキングする段階と、
前記第1の導電性フォトリソグラフィー膜を露光する段階と、
前記第1の導電性フォトリソグラフィー膜を現像して、前記第1の導電性フォトリソグラフィー膜の一部を除去する段階と、
前記第1の導電性フォトリソグラフィー膜を現像した後で、前記第1の導電性フォトリソグラフィー膜の上にめっき膜を形成する段階と、
を含む、
デバイスを製作する方法。 - 前記マスキング、前記露光及び前記現像の後で、前記第1の導電性フォトリソグラフィー膜の表面に第2の絶縁層を形成する段階と、
第2の導電性フォトリソグラフィー膜を前記第2の絶縁層の上面に堆積させる段階と、
回路パターンに従って前記第2の導電性フォトリソグラフィー膜をマスキングする段階と、
前記第2の導電性フォトリソグラフィー膜を露光する段階と、
前記第2の導電性フォトリソグラフィー膜を現像して、前記第2の導電性フォトリソグラフィー膜の一部を除去する段階と、
をさらに含む、
請求項25に記載のデバイスを製作する方法。 - 前記めっき膜の上に第2の絶縁層を形成する段階と、
前記第2の絶縁層の表面に第2の導電性フォトリソグラフィー膜を堆積させる段階と、
回路パターンに従って前記第2の導電性フォトリソグラフィー膜をマスキングする段階と、
前記第2の導電性フォトリソグラフィー膜を露光する段階と、
前記第2の導電性フォトリソグラフィー膜を現像して、前記第2の導電性フォトリソグラフィー膜の一部を除去する段階と、
をさらに含む、
請求項25に記載のデバイスを製作する方法。 - 前記第1の導電性フォトリソグラフィー膜を堆積させる段階が、前記第1の導電性フォトリソグラフィー膜を、プリント回路基板の基板の上面に形成される第1の絶縁層の表面に堆積させる段階を含む、
請求項25から請求項27までの何れか一項に記載のデバイスを製作する方法。
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US10/938,161 US7279268B2 (en) | 2004-09-09 | 2004-09-09 | Conductive lithographic polymer and method of making devices using same |
PCT/US2005/030407 WO2006031411A2 (en) | 2004-09-09 | 2005-08-26 | A conductive lithographic polymer mixture and method of making devices using same |
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JP (1) | JP4619411B2 (ja) |
KR (2) | KR101035156B1 (ja) |
CN (1) | CN101189553B (ja) |
DE (1) | DE112005002156T5 (ja) |
HK (1) | HK1120870A1 (ja) |
TW (1) | TWI333128B (ja) |
WO (1) | WO2006031411A2 (ja) |
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WO2006031411A2 (en) | 2006-03-23 |
HK1120870A1 (en) | 2009-04-09 |
US20060051707A1 (en) | 2006-03-09 |
US20070269743A1 (en) | 2007-11-22 |
KR101035156B1 (ko) | 2011-05-17 |
KR101007561B1 (ko) | 2011-01-14 |
KR20080052695A (ko) | 2008-06-11 |
CN101189553A (zh) | 2008-05-28 |
CN101189553B (zh) | 2014-10-22 |
US7279268B2 (en) | 2007-10-09 |
TWI333128B (en) | 2010-11-11 |
KR20070047822A (ko) | 2007-05-07 |
WO2006031411A3 (en) | 2007-12-21 |
DE112005002156T5 (de) | 2007-06-28 |
JP2008512721A (ja) | 2008-04-24 |
TW200622492A (en) | 2006-07-01 |
US7700246B2 (en) | 2010-04-20 |
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