JP4546094B2 - デュアルダマシン配線をパターン形成する三層マスキングアーキテクチャ - Google Patents

デュアルダマシン配線をパターン形成する三層マスキングアーキテクチャ Download PDF

Info

Publication number
JP4546094B2
JP4546094B2 JP2003582809A JP2003582809A JP4546094B2 JP 4546094 B2 JP4546094 B2 JP 4546094B2 JP 2003582809 A JP2003582809 A JP 2003582809A JP 2003582809 A JP2003582809 A JP 2003582809A JP 4546094 B2 JP4546094 B2 JP 4546094B2
Authority
JP
Japan
Prior art keywords
mask layer
layer
dielectric
trench
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003582809A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005522053A (ja
JP2005522053A5 (https=
Inventor
エイチ.ザ サード タウンゼンド,ポール
ケー. ミルス,リン
イェー.エム. ウェタールース,ヨースト
ジェイ. ストリットマター,リチャード
Original Assignee
ダウ グローバル テクノロジーズ インコーポレイティド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ダウ グローバル テクノロジーズ インコーポレイティド filed Critical ダウ グローバル テクノロジーズ インコーポレイティド
Publication of JP2005522053A publication Critical patent/JP2005522053A/ja
Publication of JP2005522053A5 publication Critical patent/JP2005522053A5/ja
Application granted granted Critical
Publication of JP4546094B2 publication Critical patent/JP4546094B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/665Porous materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6506Formation of intermediate materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6508Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a liquid
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662Laminate layers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68Organic materials, e.g. photoresists
    • H10P14/683Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/73Etching of wafers, substrates or parts of devices using masks for insulating materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/072Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
    • H10P14/6342Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H10P14/6686Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/692Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041Photolithographic processes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP2003582809A 2002-04-02 2003-03-28 デュアルダマシン配線をパターン形成する三層マスキングアーキテクチャ Expired - Fee Related JP4546094B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US36948902P 2002-04-02 2002-04-02
US36949002P 2002-04-02 2002-04-02
PCT/US2003/009700 WO2003085724A1 (en) 2002-04-02 2003-03-28 Tri-layer masking architecture for patterning dual damascene interconnects

Publications (3)

Publication Number Publication Date
JP2005522053A JP2005522053A (ja) 2005-07-21
JP2005522053A5 JP2005522053A5 (https=) 2006-05-25
JP4546094B2 true JP4546094B2 (ja) 2010-09-15

Family

ID=28794365

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003582809A Expired - Fee Related JP4546094B2 (ja) 2002-04-02 2003-03-28 デュアルダマシン配線をパターン形成する三層マスキングアーキテクチャ

Country Status (8)

Country Link
US (1) US6815333B2 (https=)
EP (1) EP1493182B1 (https=)
JP (1) JP4546094B2 (https=)
KR (1) KR101051276B1 (https=)
CN (1) CN100375265C (https=)
AU (1) AU2003222115A1 (https=)
TW (1) TWI335047B (https=)
WO (1) WO2003085724A1 (https=)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6251770B1 (en) * 1999-06-30 2001-06-26 Lam Research Corp. Dual-damascene dielectric structures and methods for making the same
US6933586B2 (en) * 2001-12-13 2005-08-23 International Business Machines Corporation Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
TWI335615B (en) * 2002-12-27 2011-01-01 Hynix Semiconductor Inc Method for fabricating semiconductor device using arf photolithography capable of protecting tapered profile of hard mask
WO2004073018A2 (en) * 2003-02-05 2004-08-26 Dow Global Technologies Inc. Sacrificial benzocyclobutene/norbornene polymers for making air gaps within semiconductor devices
US20060264065A1 (en) * 2003-02-05 2006-11-23 So Ying H Sacrificial styrene benzocyclobutene copolymers for making air gap semiconductor devices
US7585785B2 (en) * 2003-02-05 2009-09-08 Dow Global Technologies Sacrificial benzocyclobutene copolymers for making air gap semiconductor devices
TW200505966A (en) * 2003-04-02 2005-02-16 Dow Global Technologies Inc Organosilicate resin formulation for use in microelectronic devices
ITMI20031591A1 (it) * 2003-08-01 2005-02-02 St Microelectronics Srl Metodo per fabbricare strutture di isolamento
US7323113B2 (en) * 2003-11-20 2008-01-29 Uchicago Argonne, Llc Pattern transfer with self-similar sacrificial mask layer and vector magnetic field sensor
US7078350B2 (en) * 2004-03-19 2006-07-18 Lam Research Corporation Methods for the optimization of substrate etching in a plasma processing system
TW200609118A (en) * 2004-05-21 2006-03-16 Jsr Corp Laminated body and semiconductor device
KR100714284B1 (ko) * 2004-06-25 2007-05-02 주식회사 하이닉스반도체 워드라인 스트래핑 구조를 갖는 반도체 메모리 소자의메탈라인 형성 방법
US7129159B2 (en) * 2004-08-17 2006-10-31 International Business Machines Corporation Integrated dual damascene RIE process with organic patterning layer
WO2006058150A2 (en) * 2004-11-23 2006-06-01 Massachusetts Institute Of Technology Multilevel fabrication processing by functional regrouping of material deposition, lithography, and etching
US7790630B2 (en) * 2005-04-12 2010-09-07 Intel Corporation Silicon-doped carbon dielectrics
KR100703559B1 (ko) * 2005-12-28 2007-04-03 동부일렉트로닉스 주식회사 듀얼다마신 구조를 가지는 반도체 소자 및 그 제조방법
US7602068B2 (en) 2006-01-19 2009-10-13 International Machines Corporation Dual-damascene process to fabricate thick wire structure
US8071487B2 (en) * 2006-08-15 2011-12-06 United Microelectronics Corp. Patterning method using stacked structure
US7732936B2 (en) * 2006-09-06 2010-06-08 Intel Corporation Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer
US7687395B2 (en) * 2006-11-02 2010-03-30 International Business Machines Corporation Contact aperture and contact via with stepped sidewall and methods for fabrication thereof
KR100828029B1 (ko) * 2006-12-11 2008-05-08 삼성전자주식회사 스택형 반도체 장치의 제조 방법
US7947565B2 (en) * 2007-02-07 2011-05-24 United Microelectronics Corp. Forming method of porous low-k layer and interconnect process
US7884019B2 (en) * 2007-06-07 2011-02-08 Texas Instruments Incorporated Poison-free and low ULK damage integration scheme for damascene interconnects
US7709370B2 (en) 2007-09-20 2010-05-04 International Business Machines Corporation Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures
US8084862B2 (en) * 2007-09-20 2011-12-27 International Business Machines Corporation Interconnect structures with patternable low-k dielectrics and method of fabricating same
US8618663B2 (en) * 2007-09-20 2013-12-31 International Business Machines Corporation Patternable dielectric film structure with improved lithography and method of fabricating same
KR101036803B1 (ko) * 2009-07-20 2011-05-25 서울대학교산학협력단 전자빔 리소그라피용 레지스트 및 전자빔 리소그라피용 레지스트 현상방법
JP2013520841A (ja) * 2010-02-25 2013-06-06 アプライド マテリアルズ インコーポレイテッド プラズマ化学気相堆積による、有機官能基と共にシリコンを含有するハイブリッド前駆体を使用する超低誘電材料
JP5568340B2 (ja) 2010-03-12 2014-08-06 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
CN102194736B (zh) * 2010-03-15 2014-01-01 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
TWI396482B (zh) * 2010-07-30 2013-05-11 光明電子股份有限公司 線路基板製程及線路基板結構
US9111994B2 (en) * 2010-11-01 2015-08-18 Magnachip Semiconductor, Ltd. Semiconductor device and method of fabricating the same
CN102487036B (zh) * 2010-12-01 2014-09-03 中芯国际集成电路制造(北京)有限公司 互连结构的制造方法
JP6061610B2 (ja) * 2012-10-18 2017-01-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN104183538B (zh) * 2013-05-21 2018-03-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9034748B2 (en) 2013-09-04 2015-05-19 International Business Machines Corporation Process variability tolerant hard mask for replacement metal gate finFET devices
US9412581B2 (en) * 2014-07-16 2016-08-09 Applied Materials, Inc. Low-K dielectric gapfill by flowable deposition
US20160133572A1 (en) * 2014-11-07 2016-05-12 Globalfoundries Inc. Methods of forming a protective layer on an insulating layer for protection during formation of conductive structures
KR102399345B1 (ko) * 2014-11-12 2022-05-19 삼성전자주식회사 반도체 장치의 제조 방법
CN106356330B (zh) * 2015-07-17 2019-03-29 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9659874B2 (en) * 2015-10-14 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming deep trench and deep trench isolation structure
US10242872B2 (en) * 2017-03-21 2019-03-26 International Business Machines Corporation Rework of patterned dielectric and metal hardmask films
US10643858B2 (en) 2017-10-11 2020-05-05 Samsung Electronics Co., Ltd. Method of etching substrate
US12334398B2 (en) 2021-08-23 2025-06-17 International Business Machines Corporation Multilayer dielectric stack for damascene top-via integration

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275695A (en) * 1992-12-18 1994-01-04 International Business Machines Corporation Process for generating beveled edges
JPH08148563A (ja) * 1994-11-22 1996-06-07 Nec Corp 半導体装置の多層配線構造体の形成方法
US5550405A (en) * 1994-12-21 1996-08-27 Advanced Micro Devices, Incorporated Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS
US6218078B1 (en) * 1997-09-24 2001-04-17 Advanced Micro Devices, Inc. Creation of an etch hardmask by spin-on technique
US6140226A (en) * 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
JP3102409B2 (ja) * 1998-04-30 2000-10-23 日本電気株式会社 配線の形成方法及びプラズマアッシング装置
US6071809A (en) 1998-09-25 2000-06-06 Rockwell Semiconductor Systems, Inc. Methods for forming high-performing dual-damascene interconnect structures
US6312874B1 (en) * 1998-11-06 2001-11-06 Advanced Micro Devices, Inc. Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials
US6140023A (en) * 1998-12-01 2000-10-31 Advanced Micro Devices, Inc. Method for transferring patterns created by lithography
US6475904B2 (en) * 1998-12-03 2002-11-05 Advanced Micro Devices, Inc. Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques
US6218317B1 (en) * 1999-04-19 2001-04-17 National Semiconductor Corp. Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration
US6509259B1 (en) 1999-06-09 2003-01-21 Alliedsignal Inc. Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices
US6265319B1 (en) 1999-09-01 2001-07-24 Taiwan Semiconductor Manufacturing Company Dual damascene method employing spin-on polymer (SOP) etch stop layer
US6498399B2 (en) 1999-09-08 2002-12-24 Alliedsignal Inc. Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits
JP2001077196A (ja) 1999-09-08 2001-03-23 Sony Corp 半導体装置の製造方法
US6309962B1 (en) * 1999-09-15 2001-10-30 Taiwan Semiconductor Manufacturing Company Film stack and etching sequence for dual damascene
JP2001176965A (ja) * 1999-12-20 2001-06-29 Nec Corp 半導体装置及びその製造方法
US6559070B1 (en) * 2000-04-11 2003-05-06 Applied Materials, Inc. Mesoporous silica films with mobile ion gettering and accelerated processing
US6720249B1 (en) * 2000-04-17 2004-04-13 International Business Machines Corporation Protective hardmask for producing interconnect structures
JP2002026122A (ja) * 2000-07-04 2002-01-25 Sony Corp 半導体装置の製造方法
US7115531B2 (en) * 2000-08-21 2006-10-03 Dow Global Technologies Inc. Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices
US6383912B1 (en) * 2000-10-23 2002-05-07 Honeywell International, Inc. Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics
US6451712B1 (en) * 2000-12-18 2002-09-17 International Business Machines Corporation Method for forming a porous dielectric material layer in a semiconductor device and device formed
WO2002083327A1 (en) 2001-04-16 2002-10-24 Honeywell International Inc. Layered stacks and methods of production thereof
US20030119305A1 (en) * 2001-12-21 2003-06-26 Huang Robert Y. S. Mask layer and dual damascene interconnect structure in a semiconductor device
US7764602B2 (en) 2004-05-07 2010-07-27 France Telecom Method and system for protecting a communication network, said communication network including a transport network

Also Published As

Publication number Publication date
TW200306616A (en) 2003-11-16
TWI335047B (en) 2010-12-21
US6815333B2 (en) 2004-11-09
CN100375265C (zh) 2008-03-12
WO2003085724A1 (en) 2003-10-16
JP2005522053A (ja) 2005-07-21
WO2003085724A8 (en) 2004-11-04
EP1493182B1 (en) 2013-01-23
US20030219973A1 (en) 2003-11-27
AU2003222115A1 (en) 2003-10-20
KR20040099390A (ko) 2004-11-26
KR101051276B1 (ko) 2011-07-22
EP1493182A1 (en) 2005-01-05
CN1647263A (zh) 2005-07-27

Similar Documents

Publication Publication Date Title
JP4546094B2 (ja) デュアルダマシン配線をパターン形成する三層マスキングアーキテクチャ
KR100795714B1 (ko) 마이크로일렉트로닉 장치의 제조에 있어서 유기 중합체유전체용 하드마스크로서의 유기 규산염 수지
TW543116B (en) Mechanically reinforced highly porous low dielectric constant films
JP4988335B2 (ja) 相互接続構造及びこれの製造方法
KR100974042B1 (ko) 금속간 유전체로서 사용된 낮은 k 및 극도로 낮은 k의 오가노실리케이트 필름의 소수성을 복원하는 방법 및 이로부터 제조된 물품
US20090079076A1 (en) Patternable dielectric film structure with improved lithography and method of fabricating same
CN1512542A (zh) 电子设备生产
WO2009039523A1 (en) Interconnect structures containing patternable low-k dielectrics and methods of fabricating same
CN1369111A (zh) 电子器件中有机介电薄膜集成化时使用硅氧烷介电薄膜的工艺
WO2011147670A1 (en) Interconnect structure
KR100656225B1 (ko) 스핀-온 세라믹 막으로 구성된 패터닝층
JP4688411B2 (ja) 複合絶縁被膜
KR100935620B1 (ko) 금속간 유전체로서 사용된 낮은 k 및 극도로 낮은 k의오가노실리케이트 필름의 소수성을 복원하는 방법 및이로부터 제조된 물품
CN100428453C (zh) 含有低k介电阻挡膜的互连结构及其制造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060327

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060327

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080225

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100401

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100601

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100701

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130709

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4546094

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees