CN100375265C - 用于图形化双波纹互连的三层掩膜结构 - Google Patents
用于图形化双波纹互连的三层掩膜结构 Download PDFInfo
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- CN100375265C CN100375265C CNB038077574A CN03807757A CN100375265C CN 100375265 C CN100375265 C CN 100375265C CN B038077574 A CNB038077574 A CN B038077574A CN 03807757 A CN03807757 A CN 03807757A CN 100375265 C CN100375265 C CN 100375265C
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本发明涉及一种对于铜基础的双波纹集成方法,其使用具有交替蚀刻选择特性的三个上部硬掩膜层(150,160,170),比如无机/有机/无机层的,在低K(low-k)电介质叠层(120,130,140)中布线。
Description
技术领域
本发明涉及用于集成电路中多层互连制作的方法和结构,更确切地说,涉及用于双波纹集成的硬掩膜结构和工艺。
背景技术
集成电路器件包含了通过多层金属互连连接的晶体管。这些金属互连(线或插头)被夹层电介质(ILD)彼此分隔,也就是被金属互连之间的电绝缘材料彼此分隔开。金属互连被形成在层内被ILD彼此分开的线或槽中。该层有时被作为槽层。另外,通过包含孔的通孔层或者通过在ILD材料中填充了导体金属的通孔,在相邻槽层中的金属线被分开。该层有时被作为通孔层。
一般而言,集成电路制品使用SiOx作为夹层电介质(ILD)。然而,由于集成电路器件越来越小的特征,SiOx的绝缘性能被认为不足以阻止降低电路性能的串扰(cross-talk)和其它的内部干扰。由此,具有更低的介电常数(小于3.0)的替代材料“低K(low-k)”材料被发展出来。这些低介电常数材料具有两种成分种类:含有大量硅来形成分子结构主要成分的那些材料(这里指的是无机电介质)和主要包括碳来形成分子结构主要成分的那些材料(这里指的是有机电介质)。无机电介质主要由硅和任意氧形成,在主要成分中,这些无机电介质可以包含有机部分。同样地,有机电介质主要包含碳和任意氧,在主要成分中,它们也可以具有少量硅或者组分中的其它类似分子。根据上述定义,无机低介电常数材料的例子是倍半硅氧烷(silsesquioxanes)和类似材料。根据上述定义,有机低介电常数材料的例子是聚芳撑(polyarylenes),包括聚芳撑醚(例如,来自DOW化学公司的SILKTM绝缘树脂,来自Honeywell的FlareTM树脂)和苯并环丁烯基(benzocyclobutene based)树脂(例如,来自DOW化学公司的CycloteneTM树脂,在其结构中含有硅原子)。而且,当集成电路中的特征尺寸被设计得更小时,使用多孔电介质层来进一步减小介电常数和改善电绝缘性能。
除材料选择之外,集成电路制品的制作方法(集成化)也是至关重要的。一种通常的制作方法叫做双波纹法,通孔和槽层电介质材料或者其它材料被施加上去,通过去除电介质材料来在这些层中形成通孔和槽,以获得需要的通孔和槽的图形,通孔和槽填充有导体金属。通孔和槽的形成是很复杂的,使用了种种光刻技术,包括光刻胶、掩膜层、种种蚀刻工艺等。
一种通常的双波纹方法,在首先应用到衬底的通孔层电介质材料和槽层电介质材料之间使用蚀刻阻挡层,以形成一个三层电介质叠层。例如,美国专利6,071,809中,无机电介质层被用于两种低K有机电介质层中。在WO 01/18861中,Chung等人认识到通过从槽和通孔的水平电介质材料选择不同分类的中间电介质层(也就是无机和有机类),叠层中的所有材料可以是低K电介质,由此,降低三层叠层的综合有效介电常数。Chung特别指出了具有被有机层分开的两个无机层的三层电介质叠层,并且给出了在无机层上部的上面使用有机光刻胶来形成三层电介质叠层中图形的教导。
当使用有机电介质时,由于光刻胶和有机电介质的蚀刻速率很相近,出现了复杂的问题。这使得在那些有机电介质中形成通孔和槽的做法变得更加复杂。另外,如果那部分是有机电介质,电介质叠层上部经受化学机械抛光法(CMP)的能力会变困难。由此,在接触和电介质材料是有机时,两个无机硬掩膜通常是通过化学气相沉积法(CVD)沉积在三层电介质上部来完成图形化过程。例如,在6,071,809号美国专利中,Zhao揭示了一种用于在三层电介质中利用由CVD氧化硅和CVD氮化硅组成的双硬掩膜来形成双波纹结构的方法。当接触和槽电介质通过有机电介质最普通的旋转涂覆被应用时,在掩膜结构中的额外的CVD工艺复杂、昂贵和产量有限。
“带低K电介质的高性能0.13mm铜BEOL技术”,R.G.Goldblatt等人,Proc.IITC,2000年六月,261-263页,描述了在通孔和槽都形成在里面的单片电介质材料中图形化的双波纹方法。该方法需要严格控制等离子蚀刻条件,使得层中朝向蚀刻部前面的平面部分能够被蚀刻。假定具有保持蚀刻形态的能力,单片电介质能够在减少电介质结构总电容的同时,通过消除蚀刻阻挡层来减少工艺的复杂性。在蚀刻阻挡层和硬掩膜上旋转已经在简单的单层掩膜系统中被说明(参见6,265,319号和6,218,078号美国专利的实施例)。
发明内容
申请人发明了一种简单、便捷的掩膜系统和用于单片集成电路或三层电介质叠层的双波纹图形化方法,其提供了必不可少的蚀刻选择性,同时考虑到使用用于施加电介质材料和掩膜材料的单独沉积方法(例如,自旋涂覆)的需要,以及在CMP步骤中(比如,有机电介质和多孔电介质)可能容易被破坏的电介质材料的使用。该系统具有额外的优势,如果需要的话,可以被用来最小化被用来在微电器件中制作金属互连结构的不同原料的数目。
由此,根据第一实施例,该发明是包含下列部分的制品:
a)一衬底;
b)在衬底上包括具有小于3.0的介电常数的上部的电介质叠层;
c)在电介质叠层上的第一掩膜层,该第一掩膜层能够抵抗用来去除铜的化学机械抛光方法的蚀刻,而且第一掩膜层相对于电介质叠层上部具有大于5∶1的蚀刻选择性比率;
d)在第一掩膜层上的第二掩膜层,第二掩膜层相对于第一掩膜层具有大于5∶1的蚀刻选择性比率,并且相对于电介质叠层上部具有小于3∶1的蚀刻特性比率;以及
e)在第二掩膜层上的第三掩膜层,第三掩膜层相对于第二掩膜层具有大于5∶1的蚀刻选择性比率,并且相对于第一掩膜层具有小于3∶1的蚀刻特性比率。
根据第二实施例,本发明是一种包含下列步骤的在电介质叠层中形成槽和通孔的方法:
(a)提供一衬底,把电介质叠层应用到衬底上,其中电介质叠层包括将要形成槽的上部和将要形成通孔的下部,以及位于上部和下部之间的一个蚀刻阻挡层,其中下部和上部具有小于3∶1的蚀刻选择性比率,蚀刻阻挡层相对于下部和上部具有大于5∶1的蚀刻选择性比率;
(b)施加第一掩膜层,第一掩膜层相对于电介质叠层上部具有大于5∶1的蚀刻选择性比率;
(c)施加第二掩膜层,第二掩膜层相对于第一掩膜层具有大于5∶1的蚀刻选择性比率并且相对于电介质叠层的上部具有小于3∶1的蚀刻特性比率;
(d)施加第三掩膜层,第三掩膜层相对于第二掩膜层具有大于5∶1的蚀刻选择性比率并且相对于第一掩膜层具有小于3∶1的蚀刻特性比率;
(e)根据槽的图形使第一、第二和第三掩膜层图形化;
(f)根据通孔图形给蚀刻阻挡层布图;
(g)把槽图形蚀刻进电介质叠层的上部,以形成至少一个槽,把通孔图形蚀刻进电介质叠层的下部,形成至少一个通孔;
(h)在通孔和槽中沉积金属;
(i)抛光多余的金属,其中第一掩膜层作为抛光阻挡层,
其中在第一掩膜层或蚀刻阻挡层的图形化期间,第三掩膜层的至少一实质部分被去除,在电介质叠层的蚀刻中,第二掩膜层的至少一实质部分被去除。
根据第三实施例的一种在电介质中形成槽和通孔的方法,其包括下列步骤:
(a)提供一衬底,把电介质层施加到衬底上,其中电介质层包括将要形成槽的上部和将要形成通孔的下部;
(b)施加第一掩膜层,第一掩膜层在抛光步骤中作为阻挡层以及相对于电介质层具有大于5∶1的蚀刻选择性比率;
(c)施加第二掩膜层,其相对于第一掩膜层具有大于5∶1的蚀刻选择性比率;
(d)施加第三掩膜层,第三掩膜层相对于第二掩膜层具有大于5∶1的蚀刻选择性比率并且相对于第一掩膜层具有小于3∶1的蚀刻特性比率;
(e)根据槽的图形使第二和第三掩膜层图形化;
(f)根据通孔图形使第一掩膜层图形化;
(g)把通孔图形的部分蚀刻进电介质层;
(h)根据第二和第三掩膜层中的槽的图形使第一掩膜层图形化,同时去除第三掩膜层的实质部分;
(i)继续电介质层的蚀刻,从而在电介质层下部形成至少一个通孔,在电介质层上部形成至少一个槽;
(j)其中在第一掩膜层或蚀刻阻挡层的图形化期间,第三掩膜层被充分地去除,在电介质叠层的蚀刻中,第二掩膜层被充分地去除;
(k)在通孔和槽中沉积金属;
(l)抛光多余的金属,其中第一掩膜层作为抛光阻挡层。
这里使用的“相似的蚀刻特性”指的是两种材料在同样的化学条件下蚀刻,具有的蚀刻选择性相对于叠层中的其它材料在相同范围内。优选地,这些材料相对于其它材料具有的蚀刻选择性比率是小于5∶1,优选是小于3∶1,更好地是小于2∶1。
这里使用的“蚀刻选择性”指的是第一种和第二种材料当暴露在化学蚀刻环境时在完全不同的比率下蚀刻,使得它们分别被图形化。优选地,当这里提到的层的蚀刻选择性相对于其它材料而言,该层具有的蚀刻选择性比率大于5∶1,优选是大于7∶1,更好的是大于10∶1。
这里使用的“蚀刻选择性比率”指的是对某种蚀刻化学剂来说,一种材料被蚀刻的比率被第二种材料被蚀刻的比率分开。
附图说明
附图1是具有一个掩埋的蚀刻阻挡层的本发明的一个优选实施例的示意图(未按比例);
附图2是具有一个单片电介质层的本发明的一个优选实施例的示意图(未按比例);
附图3是使用附图1中制品的一个优选集成电路的示意图(未按比例);
附图4是使用附图1中制品的一个优选集成电路的示意图(未按比例);
附图5是使用可光定义的抛光阻挡层和掩埋的蚀刻阻挡层的优选集成电路的示意图(未按比例);
附图6是使用可光定义的抛光阻挡层和单片电介质层的优选集成电路的示意图(未按比例);
附图7是本发明具有多孔通孔和槽的水平电介质的优选多层结构的显微照片。
具体实施方式
这里使用的通孔指的是一个孔,在其中形成金属的互连插头。通孔的深度受到形成通孔的电介质层厚度的限制。通孔的长度和宽度是同一量级的。
这里使用的槽指的是一个沟,在其中形成金属的互连线。槽的深度受到形成槽的电介质层厚度的限制。槽的长度和与宽度相差很大。
本发明中使用的衬底105包括任何已知的衬底,在它上面形成需要的金属互连结构。特别优选的衬底是包括可根据需要连接到金属互连结构的晶体管的衬底。
本发明的制品和方法可以用来构造任何水平的金属互连结构。这样,由于常常需要几个互连层,衬底一般包含现存的金属导线106和连接部107,根据本发明的方法形成的相应的槽和通孔将被连接到连接部。这个例子中,衬底在其表面上可以包含可选铜扩散屏障层110,通常是氮化硅或碳化硅,特别地金属线106存在于衬底中。假如使用这样一个铜扩散屏障层110,本发明的方法还将包括在连接槽和通孔的下一层中沉积金属之前的刻通该层。
参见附图1,根据一实施例,本发明是具有衬底105的制品100。该实施例中,电介质叠层115包含三部分:下部120作为接触电介质或通孔电介质,中部130作为蚀刻阻挡层或掩埋硬掩膜,上部140作为槽电介质。
用于接触电介质层120和槽电介质层140的材料是介电常数小于3.0的低介电常数材料,优选的是小于2.7,更好的是大概小于2.3。这些电介质层可以是多孔的。接触电介质层120和槽电介质层140可以相同或者不同,但是必须是同一种类,也就是,要么是有机电介质材料,要么是无机电介质材料。优选地,两层都是有机电介质材料。更优选地,两层都是多孔有机电介质材料。选择蚀刻阻挡层130的种类使其与电介质层120和140的种类不同。从而,电介质层优选有机材料,蚀刻阻挡层优选无机材料。优选地,蚀刻阻挡层也具有大约小于3.7的相对小的低介电常数,更优选的是小于3.0。
本发明的掩膜系统145包含三层:第一掩膜层或者抛光阻挡层150,第二掩膜层或者蚀刻缓冲层160,第三掩膜层或者上部掩膜层170。选择抛光阻挡层150使其能够抵御或者至少能够保护电介质叠层不受沉积金属后通常进行的化学机械抛光处理工艺的影响。尽管一些无机电介质层自身能够抵御化学机械抛光处理工艺,其它的,比如多孔无机电介质可能会受到这些处理过程的损害。选择抛光阻挡层150使其与槽电介质140的种类不同而与蚀刻阻挡层130的种类相同。从而,槽电介质优选是有机的,抛光阻挡层优选是无机的。最后,既然那是可能,不是要求,抛光阻挡层作为制品的部分保留,在施加下一互连层前没有从制品中去除,抛光阻挡层比如蚀刻阻挡层130具有相对低的介电常数是希望得到的。抛光阻挡层可以与蚀刻阻挡层的材料相同或者不同。
蚀刻缓冲层160与槽电介质140的种类相同,与抛光阻挡层150的种类相反。从而槽电介质优选有机材料,那么蚀刻缓冲层也优选有机材料。由于蚀刻缓冲层在处理过程中被去除,所以该层不是最终制品的一部分,那么该层的介电常数是不重要的。然而,假如用于制作过程的材料的数量减少对使用者来说是重要的,则用作电介质的同样的材料也被用作蚀刻缓冲层。最后,上部掩膜170的材料种类和抛光阻挡层150以及蚀刻阻挡层130的相同。像蚀刻缓冲层一样,在处理过程中上部掩膜被去除,从而该层的介电常数是不重要的。然而,假如用于制作过程的材料的数量减少对使用者来说是重要的,则用作抛光阻挡层或蚀刻阻挡层的同样的材料也被用作上部掩膜。
根据可替换的实施例,本发明的制品如附图2所示。在这个实施例中,电介质是一个单片层125,而不是具有被蚀刻阻挡层分开的两个电介质层的电介质叠层。该绝电介质材料具有小于3.0的介电常数,优选是小于2.7,更好的是小于2.3。该层可以是有机的或者无机的,多孔的或者不是多孔的。然而,优选地,该层是有机的。更优选地,该层是多孔的。制品的其它组分仍然与上述附图1中所述的一样。注意,在这个实施例中,抛光阻挡层150和上部掩膜170应该是与电介质125和蚀刻缓冲层160不同的种类。
本发明的一个关键益处是可以使用同样的方法施加所有的电介质和掩膜层。优选地,通过可溶性覆盖物施加所有的层,跟着进行烘干,优选是通过凝胶点固化,通过使用相应的可溶性覆盖层使得这些层不会受到损害。最好是,根据已知方法通过旋转覆盖来制成可溶性覆盖层。
通过从两种不同种类的材料中使用可替换层,这里使用的无机材料包含了大量的形成分子结构主要成分的硅,有机材料包括分子结构中形成主要部分的重要的碳一能够通过在蚀刻有机材料化学和蚀刻无机材料化学两者之间替换而容易使电介质叠层图形化。这个布图方法不受限的例子如下:
现在参照附图3,显示了使三层掩膜和下面的三层电介质图形化的优选方法。该例子的目的是,三层电介质包括有机槽和通孔的水平电介质材料以及无机蚀刻阻挡层。当蚀刻缓冲材料是有机时,抛光阻挡层材料和上部掩膜材料是无机的。该有机材料可以相同也可以不同。无机材料可以相同或不同。在附图3a中,光刻胶180,被施加到三层硬掩膜上,并且使用槽图形210图形化,使用标准的光刻曝光。在附图3b中,槽图形通过使用含有等离子体的氟被转换到上部掩膜170中。在附图3c中,槽图形通过使用还原或者氧化等离子体被转换到蚀刻缓冲层160中。同样的蚀刻化学方法也会去除光刻胶。随着槽定义在三层硬掩膜的最上面两层中,光刻胶380的第二次应用,被图形化为214,其带着使用标准光刻实践的通孔设计,如附图3d中所示。通孔图形被转换到三层硬掩膜的抛光阻挡层150中,使用了包含等离子体的氟,如附图3e所示。对槽和通孔的图形来说,这个步骤完成了三层硬掩膜中图形的限定。通孔图形被转换到上部电介质140中,使用了氧化或者还原等离子体,如附图3f中所示。蚀刻也去除了通孔光刻胶层380。在这点上将系统暴露到氟等离子体下,把通孔图形转换到蚀刻阻挡层130中,去除上部掩膜170,并且把槽图形转换到抛光阻挡层150中,如附图3g所示。最后把系统暴露到氧化或者还原等离子体中,把槽图形转移到上部电介质140中,以及把通孔图形转移到通孔120中,去除蚀刻缓冲层160,如附图3h所示。最后的步骤是使用调整后的氟等离子体去除薄的铜扩散屏障层110,暴露出下部电路元件或者互连结构。这种方法使用标准的金属沉积和抛光技术,准备出用于金属布线限定的系统。在金属图形镶嵌上后,半导体通过使用上述步骤准备用于与附加层的进一步互连。
假如系统是带有有机蚀刻阻挡层的无机电介质,抛光阻挡层、蚀刻缓冲层和上部掩膜层将会分别是有机的、无机的和有机的,在每一个步骤的蚀刻化学将会与上面对应的内容相反。
任意地,上部掩膜层170可以是可光图形化的,特别是正特性(positive tone),此时将不需要最初的光刻胶层180。相似地,抛光阻挡层150可以是光图形化的,特别是负特性(negative tone),此时将不需要第二光刻胶380。
现在参见附图4,显示了一种使三层掩膜以及附图2中所示的下面的单片电介质叠层图形化的优选方法。该例子的目的是,电介质叠层和蚀刻缓冲层是有机的,抛光阻挡层和上部掩膜层是无机的。相反的结构(也就是无机电介质和蚀刻缓冲层,具有有机抛光阻挡层和上部掩膜层)也能被使用,在每一步骤中使用相反的化学特性,如下面所述。该有机材料可以相同也可以不同。无机材料可以相同或不同。在附图4a中,光刻胶180,被施加到三层硬掩膜上,并且使用槽图形210图形化,使用标准的光刻曝光。在附图4b中,槽图形通过使用含有等离子体的氟被转换到上部掩膜170中。在附图4c中,槽图形通过使用还原或者氧化等离子体被转换到蚀刻缓冲层160中。同样的蚀刻化学方法也会去除光刻胶。随着槽定义在三层硬掩膜的最上面两层中,光刻胶380的第二次应用,被图形化为214,其具有使用标准光刻实践的通孔设计,如附图4d中所示。光刻胶中定义了接触部图形,通孔图形被转换到三层硬掩膜的抛光阻挡层150中,使用了包含等离子体的氟,如附图4e所示。对槽和通孔的图形来说,这个步骤完成了三层硬掩膜中图形的限定。接触部图形至少部分地转换到单片电介质125中,使用了氧化或者还原等离子体,如附图4f所示。蚀刻也去除了接触部光刻胶层380。在这点上把系统暴露到氟等离子体下,去除上部掩膜170,并且把槽图形转换到抛光阻挡层150中,如附图4g所示。最后把系统暴露到氧化或者还原等离子体中,把槽图形和通孔图形转移到单片集成块中,去除蚀刻缓冲层160,如附图4h所示。最后的步骤是使用调整后的氟等离子体去除薄的铜扩散屏障层110,暴露出下部电路元件或者互连结构。这种方法使用标准金属沉积和抛光技术,准备出用于金属布线限定的系统。在金属图形镶嵌上后,半导体通过使用上述步骤准备用于与附加层的进一步互连。
任意地,上部掩膜层170可以是可光图形化的,特别是正特性,此时将不需要最初的光刻胶层180。相似地,抛光阻挡层150可以是光图形化的,特别是负特性,此时将不需要第二光刻胶380。
现在参见附图5,显示了描述使用三层电介质和三层硬掩膜的本发明实施例的截面图,其中在构造三层硬掩膜期间,抛光阻挡层和上部掩膜层在每一次沉积过后立即被图形化。假如使用光定义的抛光阻挡层和上部掩膜层时,该方法可能是方便的。这个例子的目的是,三层电介质包括有机槽和通孔的水平电介质材料以及无机蚀刻阻挡层,以及当蚀刻缓冲材料是有机时抛光阻挡层和上部掩膜材料是无机的。参见附图5,该系统的截面示意图显示了构造和图形化三层掩膜和下面的三层电介质的方法。在包含有第一级器件备接触或者互连图形的衬底上,形成铜扩散屏障层110。该铜扩散屏障层优选是CVD氮化硅,更优选的是自旋聚合体。通过应用相应的沉积方法以及固化由通孔电介质120、蚀刻阻挡层130和上部电介质层140构成三层电介质,优选通孔旋转涂覆。图形化的抛光阻挡层750被沉积并且使用槽图形808来图形化。优选地,该层使用标准光刻和干法蚀刻技术来溶剂涂覆和图形化,更优选地,通过对光敏性的图形化抛光阻挡层750材料进行直接照射来进行,如附图5a所示。蚀刻缓冲层160被沉积,优选地在图形化抛光阻挡层750上通过溶剂涂覆,如附图5b所示。图形化的上部掩膜770相应地被应用和使用通孔图形812图形化。优选地,该层使用标准光刻和干法蚀刻工艺来溶剂涂覆和图形化,更优选地,通过对光敏性的上部掩膜770材料进行直接照射来进行,如附图5c所示。晶片被放置在活性离子腐蚀工具中,通过使用氧化或者还原的等离子体蚀刻,通孔图形被首先转移到蚀刻缓冲层160和上部电介质140层中,如附图5d中所示。在附图5e中,通孔图形通过含有等离子的氟的蚀刻被转移到蚀刻阻挡层130中。该蚀刻步骤也去除了图形化的上部掩膜770。系统被最后的暴露到氧化或者还原的等离子体中,把槽图形转移到上部电介质140中,把通孔图形转移到通孔电介质120中,并且去除蚀刻缓冲层160,如附图5f所示。最后的步骤是使用调整后的氟等离子体去除薄的铜扩散屏障层110,暴露出下部电路元件或者互连结构。这种方法使用标准的金属沉积和抛光技术,准备出用于金属布线限定的系统。在金属图形镶嵌上后,半导体通过使用上述步骤准备用于与附加层的进一步互连。
假如系统是带有有机蚀刻阻挡层的无机电介质,抛光阻挡层、蚀刻缓冲层和上部掩膜层将会分别是有机的、无机的和有机的,在每一个步骤的蚀刻化学将会与上面对应的内容相反。
现在参见附图6,显示了描述使用单片电介质和三层硬掩膜的本发明实施例的截面图,其中在构造三层硬掩膜期间,抛光阻挡层和上部掩膜层在每一次沉积过后立即被图形化。假如使用光定义的抛光阻挡层和上部掩膜层,该方法可能是方便的。这个例子的目的是,单片电介质由有机电介质材料组成,以及当蚀刻缓冲材料是有机时抛光阻挡层和上部掩膜材料是无机的。在包含有第一级器件接触部或者互连图形的衬底上,形成铜扩散屏障层110。该铜扩散屏障层优选是CVD氮化硅,更优选的是自旋聚合体。单片电介质(MD)125,优选地通过随后固化的溶剂涂覆来施加。如附图6a所示,图形化的抛光阻挡层750被沉积并且使用槽图形808来图形化。优选地,该层使用标准光刻和干法蚀刻技术来溶剂涂覆和图形化,更优选地,通过对光敏性的图形化抛光阻挡层750的材料进行直接照射来进行。蚀刻缓冲层160被沉积,优选地在图形化的抛光阻挡层750上通过溶剂涂覆,如附图6b所示。图形化的上部掩膜770相应地被应用和使用通孔图形812图形化。优选地,该层使用标准光刻和干法蚀刻工艺来溶剂涂覆和图形化,更优选地,通过对光敏性的上部掩膜770材料进行直接照射来进行,如附图6c所示。晶片被放置在RIE工具中,通过使用氧化或者还原的等离子体蚀刻,通孔图形被首先转移到蚀刻缓冲层160中,接着部分转移到单片电介质125中,如附图6d中所示。在附图6e中,图形化的上部掩膜770被含有等离子体的氟去除。系统被最后的暴露到氧化或者还原的等离子体中,把槽图形和接触部图形转移到单片电介质125中,并且去除蚀刻缓冲层125,如附图6f所示。最后的步骤是使用调整后的氟等离子体去除薄的铜扩散屏障层110,暴露出下部电路元件或者互连结构。这种方法使用标准的金属沉积和抛光技术,准备出用于金属布线限定的系统。在金属图形镶嵌上后,半导体通过使用上述步骤准备用于与附加层的进一步互连。
当使用多孔电介质层时,小孔将会在蚀刻之前或者之后形成,假如在蚀刻之后时,则可能在金属化之前或者之后。然而,为确保用于掩膜系统的水平面,在至少一个上部硬掩膜材料被施加后形成小孔会更好。因此,对通过从基质电介质材料中去除热不稳定性孔隙原材料形成的多孔电介质系统来说,选择孔隙原和掩膜层使得孔隙原或者孔隙原的热不稳定性分解物能够通过硬掩膜扩散会更好。优选地,那时硬掩膜层具有小于1.5g/cm2的密度。
假如系统是带有有机蚀刻阻挡层的无机电介质,抛光阻挡层、蚀刻缓冲层和上部掩膜层将会分别是有机的、无机的和有机的,在每一个步骤的蚀刻化学将会与上面对应的内容相反。
当具有需要的介电常数的任何已知电介质材料被用于本发明时,优选有机电介质,特别是聚合体。更优选的电介质材料包括有机聚合体,其是具有二烯亲和物和二烯烃的单体通过狄尔斯阿尔德(DielsAlder)反应的反应产物。特别地,优选的有机聚合体是那些包括茂基和乙烯功能基(特别是苯基乙酸)的单体的反应产品。为了在最后的层中获得需要的交叉连接性能,至少某些单体必不可少地具有至少三个功能基。
假如需要多孔电介质材料,基质材料或基本电介质材料可以包含孔隙原,优选的是热不稳定性的孔隙原。这些孔隙原材料的实例有线性的、分杈的、星形的、圆头的、树状的、以及交叉连接的低聚体和聚合体。一个优选的孔隙原形态是交叉连接的毫微组分(nanoparticles)的聚合体。孔隙原任意地与基质化学结合,例如,通过反应基的内含物被结合到基质。用于孔隙原的合适的化学物质部分依赖于基质材料的选择。优选地,孔隙原的分解温度大约是250摄氏度到400摄氏度之间。适当的化学物质包括聚苯乙烯类比如聚苯乙烯和聚α甲基苯乙烯,聚丙烯腈类,聚氧化乙烯类,聚氧化丙烯类,聚乙烯类,聚乳酸类,聚硅氧烷类,聚已酸内酯类,聚氨酯类,聚异丁烯酸盐类,聚甲基丙烯酸酯类,聚丙烯酸酯类,聚丁二烯类,聚异戊二烯,聚酰胺类,聚四氢呋喃类,聚氯丙烯类,聚缩醛类,带末端胺基的环氧烷烃类(amine-capped alkylene oxides),聚交酯类,聚氧化丙烯类,以及乙二醇/聚己酸内酯类。
由于蚀刻阻挡层和任意地抛光阻挡层与器件一起保留,对这些材料来说一样需要低介电常数。由于优选的电介质材料是有机的,所以优选的蚀刻阻挡层和抛光阻挡层材料是无机的。优选的无机材料是交叉结合的有机硅氧烷。该有机硅氧烷优选的是从水解或者部分水解反应的替代的烷氧基硅烷或者替代酸基硅烷的产物中形成。
烷氧基或者酸基的水解产生混合的未水解、部分水解、全部水解的和低聚的烷氧基硅烷或酸基硅烷的混合物。当水解的或者部分水解的烷氧基硅烷或酸基硅烷与其它烷氧基硅烷或者酸基硅烷反应产生水、醇或酸和一个Si-O-Si键的时候发生低聚合。这里使用的术语“水解的烷氧基硅烷”或者“水解的酸基硅烷”包括任何程度的水解,部分的或者完全的,以及低聚的。水解前,替代烷氧基或者酸基硅烷优选为以下分子式:
其中,R为C1-C6亚烷基、C1-C6亚烃基、亚芳基或一个直接键(directbond);Y为C1-C6烷基、C2-C6链烯基、C2-6炔基、C6-20芳基、3-甲基丙烯酚氧基、3-丙烯酰氧基、3-氨基乙基-氨基、3-氨基、-SiZ2OR’或-OR’;R’在每次出现时为一个独立的C1-C6烷基或C2-C6酰基;Z为C1-C6烷基、C2-C6链烯基、C2-6炔基,C6-20芳基或一OR’。术语“亚烷基”指的是一种附属在相同碳原子上的脂肪族烃基。术语“亚烃基”指的是一种符合分子式-(CnH2n)-的基。术语“芳基”指的是一种芳族基,“芳族”是如莫里森(Morrison)和博伊德(Boyd)在《有机化学》(Organic Chemistry)1973年第三版中描述的,定义为含有(4n+2)个电子。术语“亚芳基”指的是一种具有两个附属点的芳基。术语“烷基”涉及饱和脂肪族基团,如甲基、乙基等。“链烯基”涉及含有至少一个双键的烷基,如乙烯、丁烯等。“炔基”涉及含有至少一个碳-碳三键的烷基。“酚基”涉及一种具有-C(O)R结构的基团(例如,一个C2酰基即为-C(O)CH3)。“酸基”涉及一种具有-OC(O)R结构的基团。在前描述的基团也可以含有其它的取代基,如卤素、烷基、芳基和杂基,如醚、肟(基)酮、酯、酰胺,或酸或碱部分,例如,梭基的、环氧的、氨基的、磺酸基的或疏基的,只要烷氧基硅烷同涂层组合物的其它组分相容。优选地,所用的硅烷为硅烷的混合物。硅烷可以为烷氧基硅烷、酸基硅烷、三烷氧基硅烷、三乙酸基硅烷、二烷氧基硅烷、二乙酸基硅烷、四烷氧基硅烷或四乙酸基硅烷。一些直接附着到硅原子上的有机基团的实例可以为苯基、甲基、乙基、乙丙烯酰氧丙基(ethacry loxyprl)、氨丙基、3-氨基乙基氨丙基、乙烯基、苄基、双环庚烯基、环己烯基乙基、环己基、环戊二烯基丙基、7-辛-1-烯基、苯乙基、烯丙基或乙酸基。硅烷优选通过无溶剂工艺水解或部分水解。硅烷保持有机部分甚至在固化之后一些有机基仍然直接键连到硅原子上。为了在硬掩膜层或蚀刻阻挡层中平衡所需特性,可以使用硅烷的混合物。例如,申请人已经发现将芳基烷氧基或芳基酸基硅烷(例如,苯基三甲氧基硅烷)与具有不饱和碳-碳键基团(例如,链烯基或烯炔酸烷基(alkyidenyl)部分如乙烯基或苯基乙炔基)的烷氧基硅烷或酸基硅烷结合使用,将会为优选的有机聚合物电介质材料提供优良的润湿、涂覆和粘合性能,特别是那些具有附加碳-碳不饱和键的芳族聚合物。芳族取代硅烷的存在同样提高了单个硅烷体系中的湿度灵敏性和介电常数。而且,已经发现将烷基烷氧基硅烷或烷基酸基硅烷(例如,甲基三甲氧基硅烷或乙基三甲氧基硅烷)与芳基和不饱和取代的硅烷结合使用,能够进一步提高所得的薄膜的湿度保持力/排除力和降低介电常数。而且,一烷氧基,一酸基、二烷氧基、二酸基、三烷氧基、三酸基、四烷氧基硅烷或四酸基硅烷的混合物可以以混合物的状态使用并能够增强蚀刻选择性,分支调节性等等。
特别地,优选下列组合物,该组合物是混合物的水解或部分水解的产物,该混合物包括
(a)50-95摩尔%的硅烷,具有分子式
其中Ra为C1-C6亚烷基、C1-C6亚烃基、亚芳基或一个直接键;Ya为C1-C6烷基、C2-C6链烯基、C2-6炔基、C6-20芳基、3-甲基丙烯酚氧基、3-丙烯酰氧基、3-氨基乙基-氨基、3-氨基、-SiZa2ORa’或-OR’;Ra’在每次出现时为一个独立的C1-C6烷基或C2-C6酰基;Za为C1-C6烷基、C2-C6链烯基、C2-6炔基、C6-20芳基或-ORa’,只要至少一个Za或Ra-Ya结合起来含有一个非芳族碳碳不饱和键。
(b)5-40摩尔%
其中Rb为C1-C6亚烷基、C1-C6亚烃基、亚芳基或一个直接键;Yb为C1-C6烷基、C2-C6链烯基、C2-6炔基、C6-20芳基、3-甲基丙烯酚氧基、3-丙烯酰氧基、3-氨基乙基-氨基、3-氨基、-SiZb2ORb’或-OR’;Rb’在每次出现时为一个独立的C1-C6烷基或C2-C6酰基;Zb为C1-C6烷基、C2-C6链烯基、C2-6炔基、C6-20芳基或-ORb’,只要至少一个Zb或Rb-Yb结合起来含有一个芳族环。
(c)0-45摩尔%
其中Rc为C1-C6亚烷基、C1-C6亚烃基、亚芳基或一个直接键;Yc为C1-C6烷基、C2-C6链烯基、C2-6炔基、C6-20芳基、3-甲基丙烯酚氧基、3-丙烯酰氧基、3-氨基乙基-氨基、3-氨基、-SiZc2ORc’或-OR’;Rc’在每次出现时为一个独立的C1-C6烷基或C2-C6酰基;Zc为C1-C6烷基、C2-C6链烯基、C2-6炔基、C6-20芳基或-ORc’,只要至少一个Zc或Rc-Yc结合起来含有一个链烯基。摩尔百分比基于存在的硅烷(a)、(b)和(c)的总摩尔数。
虽然本发明是根据附图进行具体描述,但本领域普通技术人员容易认识到对具体例子的一些变化,而那些变化将会落入本发明的精神和保护范围之内。相应地,对本领域技术人员来说,可以进行很多调整,它们都不会脱离权利要求的保护范围。
实施例
多层叠层按照下列步骤准备:
1)粘合促进剂,Dow AP5000,在600rpm时被施加在裸硅晶片上,以3000rpm旋转30秒,在185摄氏度下烘烤90秒。
2)孔电介质的原溶液通过部分地聚合双环戊二烯酮功能化单体和三苯乙炔功能化单体的混合物被制备,以及以交叉连接的微粒为基础的聚苯乙烯如美国申请号为10/077646(律师登记号是61568)中的例子所述通过微乳剂聚合来制备。微粒量占总量的20%。在600rpm时原溶液被施加到粘合促进剂层之上,在3000rpm时旋转30秒,150摄氏度时在氮气中烘烤2分钟,最后在400摄氏度时在氮气中烘烤3分钟。烘烤使树脂基质交叉连接,但是没有去除交叉连接的微粒,由此生成全密度的接触电介质层。
3)如WO 02/16477中所述,可交叉连接的有机硅氧烷低聚组合原物通过水解和后续的乙烯基三乙酰氧基硅烷和苯基三甲氧基硅烷的共聚来制备。可交叉连接的有机硅氧烷溶液被稀释到在Dowanol PMA中是8%固体。该溶液在60rpm时被施加到接触电介质层上,以3000rpm旋转30秒,在265摄氏度时烘烤60秒;从而,生成了蚀刻阻挡层。
4)如上所述第二次加入的原始溶液在600rpm时被施加到蚀刻阻挡层上,在3000rpm时旋转30秒,150摄氏度时在氮气中烘烤2分钟,最后在400摄氏度时在氮气中烘烤3分钟。由此生成了全密度的槽电介质层。
5)上所述的第二次加入的可交叉连接的有机硅氧烷溶液被稀释到在Dowanol PMA中是15%固体。该溶液在600rpm时被施加到槽电介质层上,在3000rpm时旋转30秒,在265摄氏度时烘烤60秒;从而生成一个抛光阻挡层。
6)ILK-ITM电介质树脂(来自Dow化学公司)在600rpm时被施加到抛光阻挡层上,以3000rpm旋转30秒,320摄氏度时在氮气中烘烤90秒,最后在400摄氏度时在氮气中烘烤3分钟。
7)最后,第三次加入的可交叉连接的有机硅氧烷溶液在600rpm时被施加到SILK树脂层上,在3000rpm时旋转30秒,在265摄氏度时烘烤60秒;从而生成一个上部硬掩膜层。
总的来说,七层使用所提到的交互组合物被相继施加到硅晶片上,并且间隔烘烤以交叉连接所述的每一层。这些烘烤不影响在微粒基础上的包含了交叉连接的聚苯乙烯的预先层的密度。
旋转涂覆后,晶片样品在室温下氮气中被放置在烤箱,升温到430摄氏度超过一小时,在430摄氏度时保持40分钟。冷却到室温后,通过肉眼检查发现该多层没有缺陷。通过显微镜检查发现交叉连接的微粒已经通过降解和随后的演化被去除,通过包含在结构中的多层掩膜,从而,如附图7中所述,在单独热处理中再现接触部和带有减少介电常数的槽电介质多孔体。
Claims (34)
1.一种用于双波纹图形化的制品,含有
a)一衬底;
b)在衬底上的包括具有小于3.0的介电常数的上部的电介质层,该电介质层或者是其中将要形成通孔和槽的单层或者是其中将要形成通孔和槽的三层电介质叠层;
c)在电介质层上的第一掩膜层,该第一掩膜层能够抵抗用来去除铜的化学机械抛光方法的蚀刻,而且第一掩膜层相对于电介质层上部具有大于5∶1的蚀刻选择性比率;
d)第一掩膜层上的第二掩膜层,第二掩膜层相对于第一掩膜层具有大于5∶1的蚀刻选择性比率,并且相对于电介质层上部具有小于3∶1的蚀刻特性比率;以及
e)在第二掩膜层上的第三掩膜层,第三掩膜层相对于第二掩膜层具有大于5∶1的蚀刻选择性比率,并且相对于第一掩膜层具有小于3∶1的蚀刻特性比率。
2.如权利要求1所述的制品,其中电介质层包括下部有机电介质层、上部有机电介质层和位于两者之间的无机蚀刻阻挡层。
3.如权利要求2所述的制品,其中上部和下部有机电介质层是多孔的。
4.如权利要求2所述的制品,其中上部和下部有机电介质层在有机基质物质内,在离散区域中包含热不稳定性的孔隙原。
5.如权利要求2所述的制品,其中第一掩膜层和第三掩膜层都是无机的,第二掩膜层是有机的。
6.如权利要求5所述的制品,其中蚀刻阻挡层的形成材料与第一掩膜层和第三掩膜层中的至少一个是相同的。
7.如权利要求1所述的制品,其中第一掩膜层与电介质层上部的蚀刻选择性比率大于7∶1。
8.如权利要求2所述的制品,其中第一掩膜层与蚀刻阻挡层的蚀刻选择性比率小于3∶1。
9.一种在电介质层中形成槽和通孔的方法,包括:
a)提供一衬底,在其一个表面上具有电介质层,电介质层包括下部和上部,以及位于上部和下部之间的蚀刻阻挡层,其中下部和上部具有小于3∶1的蚀刻选择性比率,蚀刻阻挡层相对于下部和上部具有大于5∶1的蚀刻选择性比率;
b)在电介质层上施加第一掩膜层,第一掩膜层相对于电介质层上部具有大于5∶1的蚀刻选择性比率;
c)在第一掩膜层上施加第二掩膜层,第二掩膜层相对于第一掩膜层具有大于5∶1的蚀刻选择性比率,并且相对于电介质层上部具有小于3∶1的蚀刻特性比率;
d)在第二掩膜层上施加第三掩膜层,第三掩膜层相对于第二掩膜层具有大于5∶1的蚀刻选择性比率,并且相对于第一掩膜层具有小于3∶1的蚀刻特性比率;
e)依据槽的图形图形化第一掩膜层;
f)使用通孔图形图形化蚀刻阻挡层;
g)把槽的图形蚀刻进电介质层上部,以形成至少一个槽,以及把通孔图形蚀刻进电介质层下部,以形成至少一个通孔;
h)在槽和通孔中沉积金属;
i)抛光多余金属,其中第一掩膜层作为抛光阻挡层,
其中在图形化第一掩膜层或蚀刻阻挡层期间,第三掩膜层的至少一实质部分被去除,以及其中在蚀刻电介质层期间,第二掩膜层的至少一实质部分被去除。
10.如权利要求9所述的方法,其中所有的层通过溶剂涂覆来施加。
11.如权利要求9所述的方法,其中电介质层在电介质基质材料内,在离散区域中包含热不稳定性的孔隙原,并且在施加了至少一个掩膜层后通过加热去除孔隙原。
12.如权利要求11所述的方法,其中孔隙原或者孔隙原的热分解物扩散通过所述掩膜层中的至少一个。
13.如权利要求9所述的方法,其中第一掩膜层是可光定义的,并且通过成像曝光辐射和显影来图形化。
14.如权利要求9所述的方法,其中在第一掩膜层上形成槽图形的步骤包括在第三掩膜层上施加光刻胶,使用槽图形成像和显影光刻胶,把槽图形蚀刻进第三掩膜层,把槽图形蚀刻进第二掩膜层,以及把槽图形蚀刻进第一掩膜层。
15.如权利要求14所述的方法,其中在把槽图形蚀刻进第一掩膜层之前施加第二光刻胶材料,使用通孔图形成像和显影第二光刻胶,通孔图形被蚀刻进第一掩膜层中,接着被蚀刻进电介质层上部中,接着蚀刻阻挡层和第一掩膜被同时蚀刻,在第一掩膜层中形成槽图形,在蚀刻阻挡层中形成通孔图形。
16.如权利要求9所述的方法,其中第三掩膜层是可光定义的。
17.如权利要求9所述的方法,其中第一和第三掩膜层彼此的蚀刻选择性比率小于5∶1。
18.如权利要求9所述的方法,其中第一掩膜层与电介质层上部的蚀刻选择性比率大于7∶1。
19.如权利要求9所述的方法,其中第一掩膜层与蚀刻阻挡层的蚀刻选择性比率小于3∶1。
20.如权利要求9所述的方法,其中第一和第三掩膜层中的至少一个是可光定义的。
21.如权利要求9所述的方法,其中第三掩膜层不是可光定义的。
22.一种在电介质中形成槽和通孔的方法,包括:
a)提供一衬底,在其一个表面上具有电介质层,电介质层包括一单层,该单层具有将要形成槽的上部和将要形成通孔的下部;
b)施加第一掩膜层,第一掩膜层在抛光步骤中作为阻挡层并且相对于电介质层具有大于5∶1的蚀刻选择性比率;
c)施加第二掩膜层,第二掩膜层相对于第一掩膜层具有大于5∶1的蚀刻选择性比率;
d)施加第三掩膜层,第三掩膜层相对于第二掩膜层具有大于5∶1的蚀刻选择性比率,并且相对于第一掩膜层具有小于3∶1的蚀刻选择性比率;
e)根据槽的图形图形化第二和第三掩膜层;
f)根据通孔图形图形化第一掩膜层;
g)把通孔图形部分蚀刻进电介质层;
h)根据第二和第三掩膜层中的槽的图形图形化第一掩膜层,同时去除第三掩膜层的实质部分;
i)继续电介质层的蚀刻,从而在电介质层下部形成至少一个通孔,在电介质层上部形成至少一个槽;
j)其中在图形化第一掩膜层或蚀刻阻挡层期间,第三掩膜层被充分地去除,在蚀刻电介质层期间,第二掩膜层被充分地去除;
k)在通孔和槽中沉积金属;
l)抛光多余的金属,其中第一掩膜层作为抛光阻挡层。
23.如权利要求22所述的方法,其中所有的层通过溶剂涂覆来施加。
24.如权利要求22所述的方法,其中电介质层在电介质基质材料内,在离散区域中包含热不稳定性的孔隙原,并且在施加了至少一个掩膜层后通过加热去除孔隙原。
25.如权利要求24所述的方法,其中孔隙原或者孔隙原的热分解物扩散通过所述掩膜层中的至少一个。
26.如权利要求22所述的方法,其中第一掩膜层是可光定义的,并且通过成像曝光辐射和显影来图形化。
27.如权利要求22所述的方法,其中第三掩膜层是可光定义的。
28.如权利要求22所述的方法,其中第一和第三掩膜层彼此的蚀刻选择性比率小于5∶1。
29.如权利要求22所述的方法,其中第一掩膜层与电介质层上部的蚀刻选择性比率大于7∶1。
30.如权利要求22所述的方法,其中第一和第三掩膜层中的至少一个是可光定义的。
31.如权利要求22所述的方法,其中槽图形被形成在第一掩膜层中,通孔图形被形成在第二和第三掩膜层中,通孔图形被部分蚀刻进所述电介质层中,接着第三掩膜层被去除,继续所述电介质层的蚀刻,从而在所述电介质层下部形成至少一个通孔,在所述电介质层上部形成至少一个槽,其中在蚀刻所述电介质层的过程中第二掩膜层被充分去除。
32.如权利要求31所述的方法,其中第一掩膜层是可光定义的,并且槽图形是通过把该层暴露在辐射的活性波长下并使该层显影而形成的。
33.如权利要求31所述的方法,其中所述电介质层在电介质基质材料内,在离散区域中包含热不稳定性的孔隙原,在施加了至少一个掩膜层后通过加热去除孔隙原,以至于孔隙原或孔隙原的热分解物扩散通过所述掩膜层中的至少一个。
34.如权利要求22所述的方法,其中第三掩膜层不是可光定义的。
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- 2003-03-28 JP JP2003582809A patent/JP4546094B2/ja not_active Expired - Fee Related
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Also Published As
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US20030219973A1 (en) | 2003-11-27 |
JP2005522053A (ja) | 2005-07-21 |
KR20040099390A (ko) | 2004-11-26 |
EP1493182B1 (en) | 2013-01-23 |
WO2003085724A8 (en) | 2004-11-04 |
WO2003085724A1 (en) | 2003-10-16 |
EP1493182A1 (en) | 2005-01-05 |
JP4546094B2 (ja) | 2010-09-15 |
US6815333B2 (en) | 2004-11-09 |
KR101051276B1 (ko) | 2011-07-22 |
CN1647263A (zh) | 2005-07-27 |
AU2003222115A1 (en) | 2003-10-20 |
TWI335047B (en) | 2010-12-21 |
TW200306616A (en) | 2003-11-16 |
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