CN100375265C - 用于图形化双波纹互连的三层掩膜结构 - Google Patents

用于图形化双波纹互连的三层掩膜结构 Download PDF

Info

Publication number
CN100375265C
CN100375265C CNB038077574A CN03807757A CN100375265C CN 100375265 C CN100375265 C CN 100375265C CN B038077574 A CNB038077574 A CN B038077574A CN 03807757 A CN03807757 A CN 03807757A CN 100375265 C CN100375265 C CN 100375265C
Authority
CN
China
Prior art keywords
layer
mask layer
dielectric
etching
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB038077574A
Other languages
English (en)
Chinese (zh)
Other versions
CN1647263A (zh
Inventor
P·H·汤森三世
L·K·米尔斯
J·J·M·维特卢斯
R·J·斯特利特马特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dow Global Technologies LLC
Original Assignee
Dow Global Technologies LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dow Global Technologies LLC filed Critical Dow Global Technologies LLC
Publication of CN1647263A publication Critical patent/CN1647263A/zh
Application granted granted Critical
Publication of CN100375265C publication Critical patent/CN100375265C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/665—Porous materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6506—Formation of intermediate materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6508—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
CNB038077574A 2002-04-02 2003-03-28 用于图形化双波纹互连的三层掩膜结构 Expired - Fee Related CN100375265C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US36948902P 2002-04-02 2002-04-02
US36949002P 2002-04-02 2002-04-02
US60/369,489 2002-04-02
US60/369,490 2002-04-02

Publications (2)

Publication Number Publication Date
CN1647263A CN1647263A (zh) 2005-07-27
CN100375265C true CN100375265C (zh) 2008-03-12

Family

ID=28794365

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038077574A Expired - Fee Related CN100375265C (zh) 2002-04-02 2003-03-28 用于图形化双波纹互连的三层掩膜结构

Country Status (8)

Country Link
US (1) US6815333B2 (https=)
EP (1) EP1493182B1 (https=)
JP (1) JP4546094B2 (https=)
KR (1) KR101051276B1 (https=)
CN (1) CN100375265C (https=)
AU (1) AU2003222115A1 (https=)
TW (1) TWI335047B (https=)
WO (1) WO2003085724A1 (https=)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6251770B1 (en) * 1999-06-30 2001-06-26 Lam Research Corp. Dual-damascene dielectric structures and methods for making the same
US6933586B2 (en) * 2001-12-13 2005-08-23 International Business Machines Corporation Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
TWI335615B (en) * 2002-12-27 2011-01-01 Hynix Semiconductor Inc Method for fabricating semiconductor device using arf photolithography capable of protecting tapered profile of hard mask
WO2004073018A2 (en) * 2003-02-05 2004-08-26 Dow Global Technologies Inc. Sacrificial benzocyclobutene/norbornene polymers for making air gaps within semiconductor devices
US20060264065A1 (en) * 2003-02-05 2006-11-23 So Ying H Sacrificial styrene benzocyclobutene copolymers for making air gap semiconductor devices
US7585785B2 (en) * 2003-02-05 2009-09-08 Dow Global Technologies Sacrificial benzocyclobutene copolymers for making air gap semiconductor devices
TW200505966A (en) * 2003-04-02 2005-02-16 Dow Global Technologies Inc Organosilicate resin formulation for use in microelectronic devices
ITMI20031591A1 (it) * 2003-08-01 2005-02-02 St Microelectronics Srl Metodo per fabbricare strutture di isolamento
US7323113B2 (en) * 2003-11-20 2008-01-29 Uchicago Argonne, Llc Pattern transfer with self-similar sacrificial mask layer and vector magnetic field sensor
US7078350B2 (en) * 2004-03-19 2006-07-18 Lam Research Corporation Methods for the optimization of substrate etching in a plasma processing system
TW200609118A (en) * 2004-05-21 2006-03-16 Jsr Corp Laminated body and semiconductor device
KR100714284B1 (ko) * 2004-06-25 2007-05-02 주식회사 하이닉스반도체 워드라인 스트래핑 구조를 갖는 반도체 메모리 소자의메탈라인 형성 방법
US7129159B2 (en) * 2004-08-17 2006-10-31 International Business Machines Corporation Integrated dual damascene RIE process with organic patterning layer
WO2006058150A2 (en) * 2004-11-23 2006-06-01 Massachusetts Institute Of Technology Multilevel fabrication processing by functional regrouping of material deposition, lithography, and etching
US7790630B2 (en) * 2005-04-12 2010-09-07 Intel Corporation Silicon-doped carbon dielectrics
KR100703559B1 (ko) * 2005-12-28 2007-04-03 동부일렉트로닉스 주식회사 듀얼다마신 구조를 가지는 반도체 소자 및 그 제조방법
US7602068B2 (en) 2006-01-19 2009-10-13 International Machines Corporation Dual-damascene process to fabricate thick wire structure
US8071487B2 (en) * 2006-08-15 2011-12-06 United Microelectronics Corp. Patterning method using stacked structure
US7732936B2 (en) * 2006-09-06 2010-06-08 Intel Corporation Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer
US7687395B2 (en) * 2006-11-02 2010-03-30 International Business Machines Corporation Contact aperture and contact via with stepped sidewall and methods for fabrication thereof
KR100828029B1 (ko) * 2006-12-11 2008-05-08 삼성전자주식회사 스택형 반도체 장치의 제조 방법
US7947565B2 (en) * 2007-02-07 2011-05-24 United Microelectronics Corp. Forming method of porous low-k layer and interconnect process
US7884019B2 (en) * 2007-06-07 2011-02-08 Texas Instruments Incorporated Poison-free and low ULK damage integration scheme for damascene interconnects
US7709370B2 (en) 2007-09-20 2010-05-04 International Business Machines Corporation Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures
US8084862B2 (en) * 2007-09-20 2011-12-27 International Business Machines Corporation Interconnect structures with patternable low-k dielectrics and method of fabricating same
US8618663B2 (en) * 2007-09-20 2013-12-31 International Business Machines Corporation Patternable dielectric film structure with improved lithography and method of fabricating same
KR101036803B1 (ko) * 2009-07-20 2011-05-25 서울대학교산학협력단 전자빔 리소그라피용 레지스트 및 전자빔 리소그라피용 레지스트 현상방법
JP2013520841A (ja) * 2010-02-25 2013-06-06 アプライド マテリアルズ インコーポレイテッド プラズマ化学気相堆積による、有機官能基と共にシリコンを含有するハイブリッド前駆体を使用する超低誘電材料
JP5568340B2 (ja) 2010-03-12 2014-08-06 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
CN102194736B (zh) * 2010-03-15 2014-01-01 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
TWI396482B (zh) * 2010-07-30 2013-05-11 光明電子股份有限公司 線路基板製程及線路基板結構
US9111994B2 (en) * 2010-11-01 2015-08-18 Magnachip Semiconductor, Ltd. Semiconductor device and method of fabricating the same
CN102487036B (zh) * 2010-12-01 2014-09-03 中芯国际集成电路制造(北京)有限公司 互连结构的制造方法
JP6061610B2 (ja) * 2012-10-18 2017-01-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN104183538B (zh) * 2013-05-21 2018-03-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
US9034748B2 (en) 2013-09-04 2015-05-19 International Business Machines Corporation Process variability tolerant hard mask for replacement metal gate finFET devices
US9412581B2 (en) * 2014-07-16 2016-08-09 Applied Materials, Inc. Low-K dielectric gapfill by flowable deposition
US20160133572A1 (en) * 2014-11-07 2016-05-12 Globalfoundries Inc. Methods of forming a protective layer on an insulating layer for protection during formation of conductive structures
KR102399345B1 (ko) * 2014-11-12 2022-05-19 삼성전자주식회사 반도체 장치의 제조 방법
CN106356330B (zh) * 2015-07-17 2019-03-29 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9659874B2 (en) * 2015-10-14 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming deep trench and deep trench isolation structure
US10242872B2 (en) * 2017-03-21 2019-03-26 International Business Machines Corporation Rework of patterned dielectric and metal hardmask films
US10643858B2 (en) 2017-10-11 2020-05-05 Samsung Electronics Co., Ltd. Method of etching substrate
US12334398B2 (en) 2021-08-23 2025-06-17 International Business Machines Corporation Multilayer dielectric stack for damascene top-via integration

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275695A (en) * 1992-12-18 1994-01-04 International Business Machines Corporation Process for generating beveled edges
CN1131817A (zh) * 1994-11-22 1996-09-25 日本电气株式会社 半导体器件中多层互连的形成方法
CN1233853A (zh) * 1998-04-30 1999-11-03 日本电气株式会社 形成多级互连结构的方法
US6140226A (en) * 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
US6218078B1 (en) * 1997-09-24 2001-04-17 Advanced Micro Devices, Inc. Creation of an etch hardmask by spin-on technique
US20010023990A1 (en) * 1999-12-20 2001-09-27 Takashi Yokoyama Semiconductor device and method for fabricating same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550405A (en) * 1994-12-21 1996-08-27 Advanced Micro Devices, Incorporated Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS
US6071809A (en) 1998-09-25 2000-06-06 Rockwell Semiconductor Systems, Inc. Methods for forming high-performing dual-damascene interconnect structures
US6312874B1 (en) * 1998-11-06 2001-11-06 Advanced Micro Devices, Inc. Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials
US6140023A (en) * 1998-12-01 2000-10-31 Advanced Micro Devices, Inc. Method for transferring patterns created by lithography
US6475904B2 (en) * 1998-12-03 2002-11-05 Advanced Micro Devices, Inc. Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques
US6218317B1 (en) * 1999-04-19 2001-04-17 National Semiconductor Corp. Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration
US6509259B1 (en) 1999-06-09 2003-01-21 Alliedsignal Inc. Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices
US6265319B1 (en) 1999-09-01 2001-07-24 Taiwan Semiconductor Manufacturing Company Dual damascene method employing spin-on polymer (SOP) etch stop layer
US6498399B2 (en) 1999-09-08 2002-12-24 Alliedsignal Inc. Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits
JP2001077196A (ja) 1999-09-08 2001-03-23 Sony Corp 半導体装置の製造方法
US6309962B1 (en) * 1999-09-15 2001-10-30 Taiwan Semiconductor Manufacturing Company Film stack and etching sequence for dual damascene
US6559070B1 (en) * 2000-04-11 2003-05-06 Applied Materials, Inc. Mesoporous silica films with mobile ion gettering and accelerated processing
US6720249B1 (en) * 2000-04-17 2004-04-13 International Business Machines Corporation Protective hardmask for producing interconnect structures
JP2002026122A (ja) * 2000-07-04 2002-01-25 Sony Corp 半導体装置の製造方法
US7115531B2 (en) * 2000-08-21 2006-10-03 Dow Global Technologies Inc. Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices
US6383912B1 (en) * 2000-10-23 2002-05-07 Honeywell International, Inc. Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics
US6451712B1 (en) * 2000-12-18 2002-09-17 International Business Machines Corporation Method for forming a porous dielectric material layer in a semiconductor device and device formed
WO2002083327A1 (en) 2001-04-16 2002-10-24 Honeywell International Inc. Layered stacks and methods of production thereof
US20030119305A1 (en) * 2001-12-21 2003-06-26 Huang Robert Y. S. Mask layer and dual damascene interconnect structure in a semiconductor device
US7764602B2 (en) 2004-05-07 2010-07-27 France Telecom Method and system for protecting a communication network, said communication network including a transport network

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275695A (en) * 1992-12-18 1994-01-04 International Business Machines Corporation Process for generating beveled edges
CN1131817A (zh) * 1994-11-22 1996-09-25 日本电气株式会社 半导体器件中多层互连的形成方法
US6218078B1 (en) * 1997-09-24 2001-04-17 Advanced Micro Devices, Inc. Creation of an etch hardmask by spin-on technique
US6140226A (en) * 1998-01-16 2000-10-31 International Business Machines Corporation Dual damascene processing for semiconductor chip interconnects
CN1233853A (zh) * 1998-04-30 1999-11-03 日本电气株式会社 形成多级互连结构的方法
US20010023990A1 (en) * 1999-12-20 2001-09-27 Takashi Yokoyama Semiconductor device and method for fabricating same

Also Published As

Publication number Publication date
TW200306616A (en) 2003-11-16
TWI335047B (en) 2010-12-21
JP4546094B2 (ja) 2010-09-15
US6815333B2 (en) 2004-11-09
WO2003085724A1 (en) 2003-10-16
JP2005522053A (ja) 2005-07-21
WO2003085724A8 (en) 2004-11-04
EP1493182B1 (en) 2013-01-23
US20030219973A1 (en) 2003-11-27
AU2003222115A1 (en) 2003-10-20
KR20040099390A (ko) 2004-11-26
KR101051276B1 (ko) 2011-07-22
EP1493182A1 (en) 2005-01-05
CN1647263A (zh) 2005-07-27

Similar Documents

Publication Publication Date Title
CN100375265C (zh) 用于图形化双波纹互连的三层掩膜结构
TW543116B (en) Mechanically reinforced highly porous low dielectric constant films
JP5350571B2 (ja) マイクロ電子デバイス製造に使用する有機ポリマー絶縁膜用ハードマスクとしての有機シリケート樹脂
TW554442B (en) Low-dielectric silicon nitride film and method of forming the same, semiconductor device and fabrication process thereof
CN102549736B (zh) 具有渐变帽盖层的能图案化低k电介质互连结构体和制造方法
KR100751990B1 (ko) 극저 유전 상수를 갖는 박막을 캡핑하는 방법 및 이로부터 제조된 기판
US8450854B2 (en) Interconnect structures with patternable low-k dielectrics and method of fabricating same
US8916978B2 (en) Interconnect structure and method of fabricating
US8659115B2 (en) Airgap-containing interconnect structure with improved patternable low-K material and method of fabricating
US8373271B2 (en) Interconnect structure with an oxygen-doped SiC antireflective coating and method of fabrication
CN101483171A (zh) 具有能图案化低k材料的含空气隙的互连结构体及其制法
US7557035B1 (en) Method of forming semiconductor devices by microwave curing of low-k dielectric films
WO2009037119A1 (en) Patternable dielectric film structure with improved lithography and method of fabricating same
KR20050013492A (ko) 구리/낮은 ｋ 상호 접속 구조를 위해 개선된 화학적평탄화 성능
KR20010082057A (ko) 반도체장치 및 그 제조방법
WO2007126956A2 (en) Damascene interconnection having porous low k layer with improved mechanical properties
TWI743199B (zh) 半導體裝置的形成方法
US7300868B2 (en) Damascene interconnection having porous low k layer with a hard mask reduced in thickness
US20070232047A1 (en) Damage recovery method for low K layer in a damascene interconnection
US20070232062A1 (en) Damascene interconnection having porous low k layer followed by a nonporous low k layer

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080312

Termination date: 20210328

CF01 Termination of patent right due to non-payment of annual fee