KR101051276B1 - 이중 다마신 배선의 패터닝을 위한 3층 마스킹 구조물 - Google Patents
이중 다마신 배선의 패터닝을 위한 3층 마스킹 구조물 Download PDFInfo
- Publication number
- KR101051276B1 KR101051276B1 KR1020047015692A KR20047015692A KR101051276B1 KR 101051276 B1 KR101051276 B1 KR 101051276B1 KR 1020047015692 A KR1020047015692 A KR 1020047015692A KR 20047015692 A KR20047015692 A KR 20047015692A KR 101051276 B1 KR101051276 B1 KR 101051276B1
- Authority
- KR
- South Korea
- Prior art keywords
- mask layer
- layer
- dielectric
- inorganic
- organic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/665—Porous materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
- H10P14/6506—Formation of intermediate materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
- H10P14/6508—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a liquid
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/68—Organic materials, e.g. photoresists
- H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
- H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
- H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
- H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
- H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
- H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
- H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
- H10P76/2041—Photolithographic processes
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36948902P | 2002-04-02 | 2002-04-02 | |
| US36949002P | 2002-04-02 | 2002-04-02 | |
| US60/369,489 | 2002-04-02 | ||
| US60/369,490 | 2002-04-02 | ||
| PCT/US2003/009700 WO2003085724A1 (en) | 2002-04-02 | 2003-03-28 | Tri-layer masking architecture for patterning dual damascene interconnects |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040099390A KR20040099390A (ko) | 2004-11-26 |
| KR101051276B1 true KR101051276B1 (ko) | 2011-07-22 |
Family
ID=28794365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020047015692A Expired - Fee Related KR101051276B1 (ko) | 2002-04-02 | 2003-03-28 | 이중 다마신 배선의 패터닝을 위한 3층 마스킹 구조물 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6815333B2 (https=) |
| EP (1) | EP1493182B1 (https=) |
| JP (1) | JP4546094B2 (https=) |
| KR (1) | KR101051276B1 (https=) |
| CN (1) | CN100375265C (https=) |
| AU (1) | AU2003222115A1 (https=) |
| TW (1) | TWI335047B (https=) |
| WO (1) | WO2003085724A1 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10643858B2 (en) | 2017-10-11 | 2020-05-05 | Samsung Electronics Co., Ltd. | Method of etching substrate |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6251770B1 (en) * | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
| US6933586B2 (en) * | 2001-12-13 | 2005-08-23 | International Business Machines Corporation | Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens |
| TWI335615B (en) * | 2002-12-27 | 2011-01-01 | Hynix Semiconductor Inc | Method for fabricating semiconductor device using arf photolithography capable of protecting tapered profile of hard mask |
| WO2004073018A2 (en) * | 2003-02-05 | 2004-08-26 | Dow Global Technologies Inc. | Sacrificial benzocyclobutene/norbornene polymers for making air gaps within semiconductor devices |
| US20060264065A1 (en) * | 2003-02-05 | 2006-11-23 | So Ying H | Sacrificial styrene benzocyclobutene copolymers for making air gap semiconductor devices |
| US7585785B2 (en) * | 2003-02-05 | 2009-09-08 | Dow Global Technologies | Sacrificial benzocyclobutene copolymers for making air gap semiconductor devices |
| TW200505966A (en) * | 2003-04-02 | 2005-02-16 | Dow Global Technologies Inc | Organosilicate resin formulation for use in microelectronic devices |
| ITMI20031591A1 (it) * | 2003-08-01 | 2005-02-02 | St Microelectronics Srl | Metodo per fabbricare strutture di isolamento |
| US7323113B2 (en) * | 2003-11-20 | 2008-01-29 | Uchicago Argonne, Llc | Pattern transfer with self-similar sacrificial mask layer and vector magnetic field sensor |
| US7078350B2 (en) * | 2004-03-19 | 2006-07-18 | Lam Research Corporation | Methods for the optimization of substrate etching in a plasma processing system |
| TW200609118A (en) * | 2004-05-21 | 2006-03-16 | Jsr Corp | Laminated body and semiconductor device |
| KR100714284B1 (ko) * | 2004-06-25 | 2007-05-02 | 주식회사 하이닉스반도체 | 워드라인 스트래핑 구조를 갖는 반도체 메모리 소자의메탈라인 형성 방법 |
| US7129159B2 (en) * | 2004-08-17 | 2006-10-31 | International Business Machines Corporation | Integrated dual damascene RIE process with organic patterning layer |
| WO2006058150A2 (en) * | 2004-11-23 | 2006-06-01 | Massachusetts Institute Of Technology | Multilevel fabrication processing by functional regrouping of material deposition, lithography, and etching |
| US7790630B2 (en) * | 2005-04-12 | 2010-09-07 | Intel Corporation | Silicon-doped carbon dielectrics |
| KR100703559B1 (ko) * | 2005-12-28 | 2007-04-03 | 동부일렉트로닉스 주식회사 | 듀얼다마신 구조를 가지는 반도체 소자 및 그 제조방법 |
| US7602068B2 (en) | 2006-01-19 | 2009-10-13 | International Machines Corporation | Dual-damascene process to fabricate thick wire structure |
| US8071487B2 (en) * | 2006-08-15 | 2011-12-06 | United Microelectronics Corp. | Patterning method using stacked structure |
| US7732936B2 (en) * | 2006-09-06 | 2010-06-08 | Intel Corporation | Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer |
| US7687395B2 (en) * | 2006-11-02 | 2010-03-30 | International Business Machines Corporation | Contact aperture and contact via with stepped sidewall and methods for fabrication thereof |
| KR100828029B1 (ko) * | 2006-12-11 | 2008-05-08 | 삼성전자주식회사 | 스택형 반도체 장치의 제조 방법 |
| US7947565B2 (en) * | 2007-02-07 | 2011-05-24 | United Microelectronics Corp. | Forming method of porous low-k layer and interconnect process |
| US7884019B2 (en) * | 2007-06-07 | 2011-02-08 | Texas Instruments Incorporated | Poison-free and low ULK damage integration scheme for damascene interconnects |
| US7709370B2 (en) | 2007-09-20 | 2010-05-04 | International Business Machines Corporation | Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures |
| US8084862B2 (en) * | 2007-09-20 | 2011-12-27 | International Business Machines Corporation | Interconnect structures with patternable low-k dielectrics and method of fabricating same |
| US8618663B2 (en) * | 2007-09-20 | 2013-12-31 | International Business Machines Corporation | Patternable dielectric film structure with improved lithography and method of fabricating same |
| KR101036803B1 (ko) * | 2009-07-20 | 2011-05-25 | 서울대학교산학협력단 | 전자빔 리소그라피용 레지스트 및 전자빔 리소그라피용 레지스트 현상방법 |
| JP2013520841A (ja) * | 2010-02-25 | 2013-06-06 | アプライド マテリアルズ インコーポレイテッド | プラズマ化学気相堆積による、有機官能基と共にシリコンを含有するハイブリッド前駆体を使用する超低誘電材料 |
| JP5568340B2 (ja) | 2010-03-12 | 2014-08-06 | 東京エレクトロン株式会社 | プラズマエッチング方法及びプラズマエッチング装置 |
| CN102194736B (zh) * | 2010-03-15 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制作方法 |
| TWI396482B (zh) * | 2010-07-30 | 2013-05-11 | 光明電子股份有限公司 | 線路基板製程及線路基板結構 |
| US9111994B2 (en) * | 2010-11-01 | 2015-08-18 | Magnachip Semiconductor, Ltd. | Semiconductor device and method of fabricating the same |
| CN102487036B (zh) * | 2010-12-01 | 2014-09-03 | 中芯国际集成电路制造(北京)有限公司 | 互连结构的制造方法 |
| JP6061610B2 (ja) * | 2012-10-18 | 2017-01-18 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| CN104183538B (zh) * | 2013-05-21 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
| US9034748B2 (en) | 2013-09-04 | 2015-05-19 | International Business Machines Corporation | Process variability tolerant hard mask for replacement metal gate finFET devices |
| US9412581B2 (en) * | 2014-07-16 | 2016-08-09 | Applied Materials, Inc. | Low-K dielectric gapfill by flowable deposition |
| US20160133572A1 (en) * | 2014-11-07 | 2016-05-12 | Globalfoundries Inc. | Methods of forming a protective layer on an insulating layer for protection during formation of conductive structures |
| KR102399345B1 (ko) * | 2014-11-12 | 2022-05-19 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
| CN106356330B (zh) * | 2015-07-17 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
| US9659874B2 (en) * | 2015-10-14 | 2017-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming deep trench and deep trench isolation structure |
| US10242872B2 (en) * | 2017-03-21 | 2019-03-26 | International Business Machines Corporation | Rework of patterned dielectric and metal hardmask films |
| US12334398B2 (en) | 2021-08-23 | 2025-06-17 | International Business Machines Corporation | Multilayer dielectric stack for damascene top-via integration |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001077196A (ja) | 1999-09-08 | 2001-03-23 | Sony Corp | 半導体装置の製造方法 |
| US20010023990A1 (en) | 1999-12-20 | 2001-09-27 | Takashi Yokoyama | Semiconductor device and method for fabricating same |
| US6309962B1 (en) | 1999-09-15 | 2001-10-30 | Taiwan Semiconductor Manufacturing Company | Film stack and etching sequence for dual damascene |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5275695A (en) * | 1992-12-18 | 1994-01-04 | International Business Machines Corporation | Process for generating beveled edges |
| JPH08148563A (ja) * | 1994-11-22 | 1996-06-07 | Nec Corp | 半導体装置の多層配線構造体の形成方法 |
| US5550405A (en) * | 1994-12-21 | 1996-08-27 | Advanced Micro Devices, Incorporated | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
| US6218078B1 (en) * | 1997-09-24 | 2001-04-17 | Advanced Micro Devices, Inc. | Creation of an etch hardmask by spin-on technique |
| US6140226A (en) * | 1998-01-16 | 2000-10-31 | International Business Machines Corporation | Dual damascene processing for semiconductor chip interconnects |
| JP3102409B2 (ja) * | 1998-04-30 | 2000-10-23 | 日本電気株式会社 | 配線の形成方法及びプラズマアッシング装置 |
| US6071809A (en) | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
| US6312874B1 (en) * | 1998-11-06 | 2001-11-06 | Advanced Micro Devices, Inc. | Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials |
| US6140023A (en) * | 1998-12-01 | 2000-10-31 | Advanced Micro Devices, Inc. | Method for transferring patterns created by lithography |
| US6475904B2 (en) * | 1998-12-03 | 2002-11-05 | Advanced Micro Devices, Inc. | Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques |
| US6218317B1 (en) * | 1999-04-19 | 2001-04-17 | National Semiconductor Corp. | Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration |
| US6509259B1 (en) | 1999-06-09 | 2003-01-21 | Alliedsignal Inc. | Process of using siloxane dielectric films in the integration of organic dielectric films in electronic devices |
| US6265319B1 (en) | 1999-09-01 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Dual damascene method employing spin-on polymer (SOP) etch stop layer |
| US6498399B2 (en) | 1999-09-08 | 2002-12-24 | Alliedsignal Inc. | Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits |
| US6559070B1 (en) * | 2000-04-11 | 2003-05-06 | Applied Materials, Inc. | Mesoporous silica films with mobile ion gettering and accelerated processing |
| US6720249B1 (en) * | 2000-04-17 | 2004-04-13 | International Business Machines Corporation | Protective hardmask for producing interconnect structures |
| JP2002026122A (ja) * | 2000-07-04 | 2002-01-25 | Sony Corp | 半導体装置の製造方法 |
| US7115531B2 (en) * | 2000-08-21 | 2006-10-03 | Dow Global Technologies Inc. | Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices |
| US6383912B1 (en) * | 2000-10-23 | 2002-05-07 | Honeywell International, Inc. | Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics |
| US6451712B1 (en) * | 2000-12-18 | 2002-09-17 | International Business Machines Corporation | Method for forming a porous dielectric material layer in a semiconductor device and device formed |
| WO2002083327A1 (en) | 2001-04-16 | 2002-10-24 | Honeywell International Inc. | Layered stacks and methods of production thereof |
| US20030119305A1 (en) * | 2001-12-21 | 2003-06-26 | Huang Robert Y. S. | Mask layer and dual damascene interconnect structure in a semiconductor device |
| US7764602B2 (en) | 2004-05-07 | 2010-07-27 | France Telecom | Method and system for protecting a communication network, said communication network including a transport network |
-
2003
- 2003-03-28 JP JP2003582809A patent/JP4546094B2/ja not_active Expired - Fee Related
- 2003-03-28 AU AU2003222115A patent/AU2003222115A1/en not_active Abandoned
- 2003-03-28 EP EP03718102A patent/EP1493182B1/en not_active Expired - Lifetime
- 2003-03-28 CN CNB038077574A patent/CN100375265C/zh not_active Expired - Fee Related
- 2003-03-28 KR KR1020047015692A patent/KR101051276B1/ko not_active Expired - Fee Related
- 2003-03-28 WO PCT/US2003/009700 patent/WO2003085724A1/en not_active Ceased
- 2003-03-28 US US10/402,073 patent/US6815333B2/en not_active Expired - Lifetime
- 2003-04-01 TW TW092107415A patent/TWI335047B/zh not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001077196A (ja) | 1999-09-08 | 2001-03-23 | Sony Corp | 半導体装置の製造方法 |
| US6309962B1 (en) | 1999-09-15 | 2001-10-30 | Taiwan Semiconductor Manufacturing Company | Film stack and etching sequence for dual damascene |
| US20010023990A1 (en) | 1999-12-20 | 2001-09-27 | Takashi Yokoyama | Semiconductor device and method for fabricating same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10643858B2 (en) | 2017-10-11 | 2020-05-05 | Samsung Electronics Co., Ltd. | Method of etching substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200306616A (en) | 2003-11-16 |
| TWI335047B (en) | 2010-12-21 |
| JP4546094B2 (ja) | 2010-09-15 |
| US6815333B2 (en) | 2004-11-09 |
| CN100375265C (zh) | 2008-03-12 |
| WO2003085724A1 (en) | 2003-10-16 |
| JP2005522053A (ja) | 2005-07-21 |
| WO2003085724A8 (en) | 2004-11-04 |
| EP1493182B1 (en) | 2013-01-23 |
| US20030219973A1 (en) | 2003-11-27 |
| AU2003222115A1 (en) | 2003-10-20 |
| KR20040099390A (ko) | 2004-11-26 |
| EP1493182A1 (en) | 2005-01-05 |
| CN1647263A (zh) | 2005-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101051276B1 (ko) | 이중 다마신 배선의 패터닝을 위한 3층 마스킹 구조물 | |
| JP5350571B2 (ja) | マイクロ電子デバイス製造に使用する有機ポリマー絶縁膜用ハードマスクとしての有機シリケート樹脂 | |
| JP4988335B2 (ja) | 相互接続構造及びこれの製造方法 | |
| US8637395B2 (en) | Methods for photo-patternable low-k (PPLK) integration with curing after pattern transfer | |
| US7879717B2 (en) | Polycarbosilane buried etch stops in interconnect structures | |
| KR20110014540A (ko) | 전자 디바이스 제조 | |
| KR20050013492A (ko) | 구리/낮은 k 상호 접속 구조를 위해 개선된 화학적평탄화 성능 | |
| WO2007126956A2 (en) | Damascene interconnection having porous low k layer with improved mechanical properties | |
| KR100656225B1 (ko) | 스핀-온 세라믹 막으로 구성된 패터닝층 | |
| JP2004253626A (ja) | 多孔性絶縁膜、電子装置及びそれらの製造方法 | |
| KR20070019748A (ko) | 상호접속 구조물의 제조방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
|
| A201 | Request for examination | ||
| AMND | Amendment | ||
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| AMND | Amendment | ||
| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
St.27 status event code: A-1-2-D10-D21-exm-PE0902 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| T11-X000 | Administrative time limit extension requested |
St.27 status event code: U-3-3-T10-T11-oth-X000 |
|
| AMND | Amendment | ||
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-3-3-R10-R13-asn-PN2301 St.27 status event code: A-3-3-R10-R11-asn-PN2301 |
|
| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
St.27 status event code: N-2-6-B10-B15-exm-PE0601 |
|
| J201 | Request for trial against refusal decision | ||
| PJ0201 | Trial against decision of rejection |
St.27 status event code: A-3-3-V10-V11-apl-PJ0201 |
|
| A107 | Divisional application of patent | ||
| AMND | Amendment | ||
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0104 | Divisional application for international application |
St.27 status event code: A-0-1-A10-A17-div-PA0104 St.27 status event code: A-0-1-A10-A16-div-PA0104 |
|
| PB0901 | Examination by re-examination before a trial |
St.27 status event code: A-6-3-E10-E12-rex-PB0901 |
|
| B701 | Decision to grant | ||
| PB0701 | Decision of registration after re-examination before a trial |
St.27 status event code: A-3-4-F10-F13-rex-PB0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U12-oth-PR1002 Fee payment year number: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| FPAY | Annual fee payment |
Payment date: 20140702 Year of fee payment: 4 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20150619 Year of fee payment: 5 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
|
| FPAY | Annual fee payment |
Payment date: 20160616 Year of fee payment: 6 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| FPAY | Annual fee payment |
Payment date: 20170616 Year of fee payment: 7 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 7 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20190617 Year of fee payment: 9 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 9 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-5-5-R10-R18-oth-X000 |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20200719 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE |
|
| PC1903 | Unpaid annual fee |
St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20200719 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |