JP2005522053A5 - - Google Patents

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Publication number
JP2005522053A5
JP2005522053A5 JP2003582809A JP2003582809A JP2005522053A5 JP 2005522053 A5 JP2005522053 A5 JP 2005522053A5 JP 2003582809 A JP2003582809 A JP 2003582809A JP 2003582809 A JP2003582809 A JP 2003582809A JP 2005522053 A5 JP2005522053 A5 JP 2005522053A5
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JP
Japan
Prior art keywords
mask layer
layer
dielectric
etch
hard mask
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JP2003582809A
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English (en)
Japanese (ja)
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JP4546094B2 (ja
JP2005522053A (ja
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Priority claimed from PCT/US2003/009700 external-priority patent/WO2003085724A1/en
Publication of JP2005522053A publication Critical patent/JP2005522053A/ja
Publication of JP2005522053A5 publication Critical patent/JP2005522053A5/ja
Application granted granted Critical
Publication of JP4546094B2 publication Critical patent/JP4546094B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2003582809A 2002-04-02 2003-03-28 デュアルダマシン配線をパターン形成する三層マスキングアーキテクチャ Expired - Fee Related JP4546094B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US36948902P 2002-04-02 2002-04-02
US36949002P 2002-04-02 2002-04-02
PCT/US2003/009700 WO2003085724A1 (en) 2002-04-02 2003-03-28 Tri-layer masking architecture for patterning dual damascene interconnects

Publications (3)

Publication Number Publication Date
JP2005522053A JP2005522053A (ja) 2005-07-21
JP2005522053A5 true JP2005522053A5 (https=) 2006-05-25
JP4546094B2 JP4546094B2 (ja) 2010-09-15

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Family Applications (1)

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JP2003582809A Expired - Fee Related JP4546094B2 (ja) 2002-04-02 2003-03-28 デュアルダマシン配線をパターン形成する三層マスキングアーキテクチャ

Country Status (8)

Country Link
US (1) US6815333B2 (https=)
EP (1) EP1493182B1 (https=)
JP (1) JP4546094B2 (https=)
KR (1) KR101051276B1 (https=)
CN (1) CN100375265C (https=)
AU (1) AU2003222115A1 (https=)
TW (1) TWI335047B (https=)
WO (1) WO2003085724A1 (https=)

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