JP4529319B2 - Semiconductor chip and manufacturing method thereof - Google Patents

Semiconductor chip and manufacturing method thereof Download PDF

Info

Publication number
JP4529319B2
JP4529319B2 JP2001195072A JP2001195072A JP4529319B2 JP 4529319 B2 JP4529319 B2 JP 4529319B2 JP 2001195072 A JP2001195072 A JP 2001195072A JP 2001195072 A JP2001195072 A JP 2001195072A JP 4529319 B2 JP4529319 B2 JP 4529319B2
Authority
JP
Japan
Prior art keywords
resin
electrode
nitride semiconductor
substrate
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001195072A
Other languages
Japanese (ja)
Other versions
JP2003007929A (en
Inventor
和浩 永峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nichia Corp
Original Assignee
Nichia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nichia Corp filed Critical Nichia Corp
Priority to JP2001195072A priority Critical patent/JP4529319B2/en
Publication of JP2003007929A publication Critical patent/JP2003007929A/en
Application granted granted Critical
Publication of JP4529319B2 publication Critical patent/JP4529319B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は樹脂封止された半導体チップとその製造方法に関する。
【0002】
【従来の技術】
半導体チップは通常、ウエハ上に各素子を形成した後、ウエハを切断することにより製造され、実装された後、樹脂封止されて使用される。
また、このウエハを切断する方法には、例えば、ダイヤモンドカッターなどでウエハ表面に傷をつけ、そこからへき開性を利用して割る方法(スクライブ方法)、例えば、金属円盤の表面にダイヤモンド砥粒を固着させたダイシングソーを用いてウエハを途中までカット(ハーフカット)して割る方法、又はダイシングソーを用いて最後までカット(フルカット)する方法等がある。
【0003】
【発明が解決しようとする課題】
しかしながら、従来の半導体チップは実装時に素子を傷つけないように取り扱いを慎重にする必要があり、取り扱いが容易でなかった。
また、スクライブ方法を用いて製造工程では、半導体チップの隅が欠けるチッピングやクラックが発生する恐れがあり、それを避けるためにはダイヤモンドカッターの荷重やスクライブの深さ等のパラメーターの微妙な調整を必要とするという製造工程上の問題点があった。
特に高い硬度のウエハを用いた場合にはより慎重なパラメータの微調整を必要とし、これらの微調整は人間の感覚や経験に頼る所が大きく、切断工程の自動化が困難であるという問題点があった。
また、ダイシングソーを用いてサファイア基板をフルカットすることはできないという問題点があった。
【0004】
そこで、本発明は、取り扱いが容易な半導体チップを提供することを第1の目的とする。
また、本発明は、チッピングやクラックの発生を容易に防止でき、容易に自動化することができる半導体チップの製造方法を提供することを第2の目的とする。
【0005】
【課題を解決するための手段】
以上の目的を達成するために、本発明に係る窒化物半導体発光素子は、基板上に、n電極が形成されたn型半導体層と、窒化物半導体からなる発光層と、p電極が形成されたp型半導体層と、を備え、上記n電極上及びp電極上にそれぞれバンプが形成されてなる窒化物半導体発光素子において、
上記バンプの先端部分と基板の下面を除いて上記チップを実質的に覆うように蛍光体を含みかつ透光性を有する樹脂からなる樹脂封止体が形成され、かつ該樹脂封止体は上記基板に垂直な側面を有することを特徴とする。
このように構成することにより、半導体層により発光された光と蛍光体により発光された光との混色により所望の発光色を実現できる。
また、以上のように構成された本発明に係る窒化物半導体発光素子は、上記バンプの先端部分と基板の下面を除いて樹脂封止体が形成されているので、上記n型とp型半導体層及び各電極を保護することができるので、実装時における取り扱いを容易にできる。ここで、本明細書において上面とは、実装されたときの上下ではなく、窒化物半導体発光素子において半導体層及び電極層が形成された側の面をいい、下面とは半導体層が形成されている面とは逆の面をいう。
【0006】
また、本発明の窒化物半導体発光素子において、上記n型半導体層は1又は2以上の窒化物半導体層を含み、上記p型半導体層は1又は2以上の窒化物半導体層を含んでいてもよい。
【0007】
さらに、本発明の窒化物半導体発光素子において、上記樹脂封止体は、上記基板の下面の外側に該下面と実質的に同一平面上に位置する底面を有することが好ましく、これにより上記基板の側面の外側に比較的厚い樹脂封止体を形成することができるので、より効果的に上記n型とp型半導体層及び各電極を保護することができる。
【0009】
また、本発明の窒化物半導体発光素子において、上記樹脂封止体は、反射散乱粒子を含むようにしてもよく、このように構成すると特に基板の下面から光を放出するように実装した場合に、発光した光の取りだし効率を向上させることができる。
【0010】
また、本発明に係る窒化物半導体発光素子の製造方法は、ウエハ上に形成された複数の素子を素子毎に分離することにより窒化物半導体発光素子を製造する方法であって、
上記ウエハの素子間に分離溝を形成する溝形成工程と、
上記分離溝が形成されたウエハ上に上記分離溝に樹脂が充填されるように透光性を有する樹脂を形成してその樹脂を硬化する樹脂形成工程と、
上記ウエハの下面を、上記分離溝の硬化された樹脂が露出するまで研磨する研磨工程と、
上記分離溝の硬化された樹脂を切断する切断工程とを含み、
上記窒化物半導体発光素子は、上記ウエハが切断されてなる基板上に、n電極が形成されたn型半導体層と、窒化物半導体からなる発光層と、p電極が形成されたp型半導体層と、を備え、
上記n電極上及びp電極上にそれぞれバンプが形成されてなり、
上記樹脂形成工程において、上記樹脂に蛍光体を含有させて、当該樹脂を上記バンプの先端部分を除いて実質的に各素子を覆うように形成することを特徴とする。
以上のように構成された窒化物半導体発光素子の製造方法は、樹脂を硬化させた後に研磨及び切断により樹脂封止体の形状加工を施しているので、寸法精度よく樹脂封止体を加工でき、外形の寸法バラツキの少ない窒化物半導体発光素子を製造することができる。
【0012】
【発明の実施の形態】
以下、図面を参照しながら本発明に係る実施の形態について説明する。
実施の形態1.
本発明に係る実施の形態1の半導体チップは、図1及び図2に示すように、サファイアからなる基板1の上に、例えばSiがドープされたn型窒化物半導体からなるn型半導体層2、窒化物半導体からなる発光層(図示せず)及びMgがドープされたp型窒化物半導体からなるp型半導体層3が積層されてなる窒化物半導体発光素子であって、以下のように構成されている。
【0013】
(電極部の構成)
p型半導体層3の一部を除去して露出させたn型半導体層2の上にnパッド電極22が形成されかつp型半導体層のほぼ全面にp全面電極31が形成されそのn全面電極31上の一部にpパッド電極32が形成されている。
ここで、基板1上において、nパッド電極22とpパッド電極32の上面を除いて、n型半導体層2、p型半導体層3及びp全面電極31を覆うようにSiO2からなる保護膜4が形成されその上に、例えばポリイミドからなる保護膜5が形成されている。
そして、nパッド電極22とpパッド電極32の上には、それぞれバンプ23及びバンプ33がその上端面がそれぞれ平坦でかつ互いにほぼ同一の高さになるように形成されている。
【0014】
(樹脂封止体)
本実施の形態1の半導体チップにおいて、樹脂封止体7はバンプ23の上端部分、バンプ33の上端部分、基板1の下面とを除いて、素子全体を覆うように形成されている。
ここで、本実施の形態1の半導体チップにおいて、樹脂封止体7は基板1に垂直な側面7aを有するように形成され、これにより本実施の形態1の半導体チップの外形形状は直方体とされる。
また、図2において、7bの符号を付して示す部分は基板1の下面を取り囲むように形成されている樹脂封止体7の底面であって、基板1の底面と実質的に同一平面上に位置するように形成されている。
尚、本実施の形態1の半導体チップでは、図1に示すように、樹脂封止体7の上面において、露出された2つのバンプ23を互いに接続するように電極層24が形成され、樹脂封止体7の上面において、露出された2つのバンプ33を互いに接続するように電極層34が形成される。
【0015】
以上のように構成された実施の形態1の半導体チップは、基板1と樹脂封止体7とによって、素子を構成している部分が保護されているので、例えば実装時における素子の破壊を防止でき、また、電極面にダイボンド樹脂が付着するのを防止できる。
【0016】
以下、本実施の形態1の半導体チップの製造方法について説明する。
尚、以下の図3〜図4においては、p型及びn型半導体層及びn及びp電極等の各電極は省略して描いている。
【0017】
(各素子領域の形成工程)
本製造方法ではまず、サファイアからなるウエハ100上に、各半導体チップにそれぞれ対応する複数の素子を形成する。
具体的には、ウエハ100の上にn型半導体層とp型半導体層とを形成して、素子間に位置するn型半導体層及びp型半導体層をエッチングにより除去して各素子毎に分離する。
以下、この素子間においてエッチングにより除去した部分を素子分離領域といい、図5において41及び42の符号を付して示す。
ここで、素子分離領域41同士は互いに平行になるように形成され、素子分離領域42同士は互いに平行になるように形成される。
また、素子分離領域41と素子分離領域42とは互いに直交するように形成される。
【0018】
次に、各素子領域においてそれぞれp型半導体層3の一部を除去してn型半導体層2を露出させて露出させたn型半導体層2の上にnパッド電極22を形成する。
さらに、p型半導体層3のほぼ全面にp全面電極31を形成して、そのn全面電極31上の一部にpパッド電極32を形成する。
次に、nパッド電極22とpパッド電極32の上面を除いて、n型半導体層2、p型半導体層3及びp全面電極31を覆うようにSiO2からなる保護膜4を形成し、その上にポリイミドからなる保護膜5を形成する。
そして、nパッド電極22とpパッド電極32の上に、それぞれバンプ23及びバンプ33を形成する。
【0019】
(分離溝の形成工程)
次に、図3(b)及び図5に示すように、各素子分離領域41,42に露出したウエハの表面に、例えばダイシングソーを用いて、所定の形状の分離溝51を形成する。
ここで、分離溝51は、例えば、深さ200μm、幅100に設定される。
この分離幅51の幅を200μより浅くすると、ダイシングの時間は短縮することができかつダイシングブレード(ダイシングソーの刃)の磨耗量を減らすことができる。この場合、後述の基板研磨工程において基板の研磨量が大きくなるので研磨時間は長くなるが、ウエハの研磨は一度に大量(多数枚)に処理できるので、特に問題にはならない。
しかしながら、研磨後にチップを保持する樹脂の強度が低下するので、一定の保持強度を保つことができるように、分離溝51の深さを設定する必要がある。
また、逆にこの分離幅51の幅を200μより深く設定すると、ダイシングブレードの磨耗量が大きくなり、またダイシングの時間は長くなるが、研磨後にチップを保持する強度が向上する。
従って、分離溝51の深さは樹脂の強度等を考慮して最適な値に設定される。
尚、分離溝に充填される樹脂はフィラーを含み、これにより樹脂を柔らかくでき、研磨する工程で熱収縮を抑えることができ、サファイア基板が割れにくくなるという効果がある。
また、分離溝の形成工程において使用されるダイシングソーは、後述の切断工程に用いられるダイシングソーより刃の厚さが厚いものが用いられる。
【0020】
(封止樹脂層の形成工程)
次に、図3(c)に示すように、ウエハの上面全体を覆うように封止樹脂層70を形成して、硬化させる。
そして、図4(a)に示すように、硬化させた封止樹脂層70を上面から各バンプ23,33の各上端面が露出するまで研磨する。これにより、バンプ23とバンプ33の上端面はそれぞれ平坦でかつほぼ同一の高さにそろえられる。
【0021】
次に、図4(b)に示すように、露出させたバンプ23,33にそれぞれ電極層24,34を形成する。
本実施の形態1では、図6に示すように露出させた2つのバンプ23を接続するように電極層24を形成し、2つのバンプ33を接続するように電極層34を形成している。
このように本実施の形態1の半導体チップでは、電極層24,34を大きく形成することにより外部回路との接続を容易にしている。
具体的には、例えば、図6に示す電極層24,34に対応する形状の開口部を有するレジストを樹脂封止体70の上に形成して、その上からスパッタリングにより全面に金属層を形成した後、レジストをその上に形成された金属層とともに除去(リフトオフ)することにより、所定の形状の電極層24,34を形成することができる。
【0022】
(基板研磨工程)
次に、基板1の下面から分離溝51,52の底部に達するまで基板1を研磨して、図4(c)に示すように、基板の下面に分離溝51,52に充填された樹脂封止体70を露出させる。
(切断工程)
次に、図4(d)に示すように、分離溝51,52に充填された樹脂封止体70を、例えば、刃の厚さが20μmのダイシングソー等を用いて各分離溝の中央部で分離溝に沿って切断する。
【0023】
以上のような工程により、図1及び図2に示す実施の形態1の半導体チップが作製される。
【0024】
以上のように構成された本実施の形態1の製造方法では、ウエハ100において素子間に分離溝51を形成して、その分離溝51に樹脂を充填して硬化し、ウエハ100の下面を分離溝51において硬化された樹脂が露出するまで研磨した後、その分離溝51の部分で硬化した樹脂を切断するようにしているので、その樹脂のみを切断することによりサファイアを切断することなく個々の素子に分離することができる。
尚、本製造方法においては、分離溝を形成する工程と基板の下面を研磨する工程とを必要とするが、サファイア基板をカットする場合に比較して切断が容易であり、また、研磨工程は自動化が容易である。
【0025】
また、本実施の形態1の製造方法では、分離溝を形成する工程以外では直接サファイア基板を切断する必要がないので、チッピングやクラックを発生させることなく各素子に分離でき、信頼性の高い半導体チップを歩留まりよく製造することができる。
【0026】
また、本実施の形態1の製造方法によれば、樹脂封止体を直交する分離溝51,52においてそれぞれ、ウエハ100と垂直に切断しているので、容易に方形の半導体チップを製造することができる。
また、本実施の形態2の半導体チップでは樹脂を硬化させた後に研磨及び切断により樹脂封止体7の形状加工を施しているので、例えば個々の素子に分割した後に樹脂層を形成して樹脂封止した場合に比較して、寸法精度よく樹脂封止体を加工できるので、外形の寸法バラツキの少ない半導体チップを製造することができる。
以上説明したように、上記製造方法によって作製された実施の形態1の半導体チップは、方形形状を有しかつ外形の寸法のバラツキを少なくできるので、安定した実装を容易に実現できる。
【0027】
実施の形態2.
本発明に係る実施の形態2の半導体チップは、樹脂封止体70として透光性を有する樹脂を用いかつその樹脂の中に蛍光体を含有させた発光素子チップである。
すなわち、本実施の形態2の半導体チップは、以下のように構成している。
(1)p全面電極31を例えば薄い金属膜からなる透光性を有する電極として、発光層で発光した光を電極が形成された側から光を取り出すように構成している。
(2)また、樹脂封止体70の中に、発光層で発光した光を吸収して吸収した光とは異なる波長の光を発生する蛍光体を含有させている。
(3)上記(1)(2)以外は実施の形態1と同様に構成される。
【0028】
尚、本実施の形態2の半導体チップの製造方法は、樹脂封止体70の樹脂として蛍光体を含有させた樹脂を用いる以外は、実施の形態1の製造方法と同様である。
【0029】
以上のように構成された本実施の形態2の半導体チップにおいて、例えば、n型半導体層及びp型半導体層としてそれぞれ窒化物半導体を用い発光層において青色光を発光させ、蛍光体として例えば、セリウムで付活されたイットリウム・アルミニウム・ガーネット系蛍光体等の蛍光体を用いることにより、発光層で発光した光と蛍光体により発光された光との混色により白色の光が観測される。
【0030】
以上のように構成された実施の形態2の半導体チップは、基板1の下面を除いて全て樹脂封止体70で覆っているので、色度のバラツキを小さくできる。
例えば、基板1の側面(又はその一部)が蛍光体を含む樹脂により覆われていないと、その部分から発光層で発光した光が直接出射され、全体としては青みががった白色となるが、実施の形態2の半導体チップでは基板1の側面を露出させることなく蛍光体を含む樹脂により覆うことができるので、かかる不都合を防止できる。
【0031】
以下、本発明に係る実施の形態1又は2の半導体チップの実装例について説明する。
実装例1.
実装例1は、本発明に係る半導体チップをフリップチップボンディングした場合の実装例である(図7)。
すなわち、本実装例では、図7に示すように、実装基板90に形成された電極(図示せず)に半導体チップの電極層24,34を対向させハンダ80により接続している。
この例では、発光した光は基板の下面から放射される。
このようにフリップチップボンディングされて使用される場合には、半導体チップの樹脂封止体7には、例えば酸化チタン等の反射散乱粒子を含有させることが好ましく、このように樹脂封止体7に反射散乱粒子を含有させると基板の側面及び基板の電極側から放射される光をその反射散乱粒子により反射して基板の下面から出射することができるので、光の取りだし効率を向上させることができる。
【0032】
また、フリップチップボンディングされて使用される場合には、半導体チップの樹脂封止体7にAlN等の熱伝導性の良好な粒子を含有させてもよく、このようにすると樹脂封止体7の熱伝導性を向上させることができるので、放熱特性を良好にできる。
さらに、フリップチップボンディングされて使用される場合には、半導体チップの樹脂封止体7の材料として、耐熱性に優れた樹脂を用いることが好ましく、これによりリフローハンダ付けを可能にしかつそれによる劣化を防止できる。
【0033】
実装例2.
本実装例2は、図8に示すように、基板1の上面、すなわち基板1の電極が形成された側から光を取り出すことを意図して、例えば、AuやAlからなるワイヤー82を用いてワイヤーボンディングにより接続した例である。
例えば、実施の形態2の半導体チップではこのような実装方法が用いられる。
このような実装方法で本発明に係る素子は略垂直な側面を有する樹脂封止体7によって覆われているので、ダイボンド樹脂83が樹脂封止体7の上面に廻り込んで付着するのを(バンプ上に付着するのを)防止できる。
ここで、本実装例において、ダイボンド樹脂としてエポキシ樹脂や銀ペーストを用いることができる。
【0034】
以上の実施の形態1及び2では、窒化物半導体を用いた発光素子チップについて説明したが、本発明はこれに限られるものではなく、他の半導体材料を用いた素子についても適用することができる。
また、本発明は発光素子チップに限られるものではなく、受光素子さらには光関連素子以外のダイオードやトランジスタについても適用することができる。
【0035】
【発明の効果】
以上、詳細に説明したように、本発明に係る半導体チップは、上記バンプの先端部分と基板の下面を除いて上記チップを実質的に覆うように樹脂封止体が形成され、かつ該樹脂封止体は上記基板に垂直な側面を有しているので、上記各半導体層及び各電極を保護することができ、実装時における取り扱いを容易にでき、かつ、上記樹脂封止体は上記基板に垂直な側面を有しているので、実装時における取り扱いを容易にできる。
従って、本発明によれば、取り扱いが容易な半導体チップを提供することができる。
【0036】
また、本発明に係る半導体チップの製造方法は、上記ウエハの素子間に分離溝を形成する溝形成工程と、上記分離溝に樹脂が充填されるように樹脂を形成する樹脂形成工程と、上記ウエハを上記分離溝の硬化された樹脂が露出するまで研磨する研磨工程と、上記分離溝の硬化された樹脂を切断する切断工程とを含むことにより、樹脂を硬化させた後に研磨及び切断により樹脂封止体の形状加工を施しているので、寸法精度よく樹脂封止体を加工でき、外形の寸法バラツキの少ない半導体チップを製造することができかつ、チッピングやクラックの発生を容易に防止でき、しかも容易に自動化することができる。
【図面の簡単な説明】
【図1】 本発明に係る実施の形態1の半導体チップ(発光素子チップ)の平面図である。
【図2】 図1のA−A’線についての断面図である。
【図3】 実施の形態1の半導体チップの製造方法における、素子部分を構成した後の断面図(a)、分離溝を形成した後の断面図(b)、樹脂層を形成した後の断面図(c)である。
【図4】 実施の形態1の半導体チップの製造方法における、樹脂層を研磨した後の断面図(a)、バンプ間を接続する電極層を形成した後の断面図(b)、基板を研磨した後の断面図(c)、分離溝において樹脂層を切断した後の断面図(d)である。
【図5】 実施の形態1の半導体チップの製造方法において、分離溝を形成した後の平面図である。
【図6】 実施の形態1の半導体チップの製造方法において、樹脂層を研磨して、バンプ間を接続する電極層を形成した後の平面図である。
【図7】 本発明に係る半導体チップをフリップチップ実装した時の様子を示す断面図である。
【図8】 本発明に係る半導体チップをワイヤーボンディングを用いて実装した時の様子を示す断面図である。
【符号の説明】
1…基板、
2…n型半導体層、
3…p型半導体層、
4,5…保護膜、
7…樹脂封止体、
7a…樹脂封止体の側面、
7b…樹脂封止体7の底面、
22…nパッド電極
23,33…バンプ、
24,34…電極層、
31…p全面電極、
32…pパッド電極、
41,42…素子分離領域、
51,52…分離溝、
80…ハンダ、
82…ワイヤー、
90…実装基板、
100…ウエハ。
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a resin-encapsulated semiconductor chip and a manufacturing method thereof.
[0002]
[Prior art]
A semiconductor chip is usually used by forming each element on a wafer, then cutting the wafer, mounting, and then sealing with a resin.
In addition, as a method of cutting the wafer, for example, the surface of the wafer is scratched with a diamond cutter or the like, and the wafer is cleaved using a cleavage (scribe method). For example, diamond abrasive grains are applied to the surface of a metal disk. There are a method of cutting the wafer halfway (half-cut) using a fixed dicing saw, and a method of cutting to the end using a dicing saw (full cut).
[0003]
[Problems to be solved by the invention]
However, the conventional semiconductor chip needs to be handled with care so as not to damage the element during mounting, and is not easy to handle.
In addition, in the manufacturing process using the scribing method, chipping and cracks may occur where the corners of the semiconductor chip are chipped. There was a problem in the manufacturing process that it was necessary.
Especially when using high-hardness wafers, more careful parameter fine adjustments are required, and these fine adjustments rely heavily on human senses and experience, making it difficult to automate the cutting process. there were.
Further, there is a problem that the sapphire substrate cannot be fully cut using a dicing saw.
[0004]
Therefore, a first object of the present invention is to provide a semiconductor chip that can be easily handled.
A second object of the present invention is to provide a semiconductor chip manufacturing method that can easily prevent chipping and cracks and can be easily automated.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, a nitride semiconductor light emitting device according to the present invention includes an n-type semiconductor layer in which an n electrode is formed, a light emitting layer made of a nitride semiconductor, and a p electrode formed on a substrate. A nitride semiconductor light emitting device comprising a bump formed on each of the n electrode and the p electrode.
Formed resin sealing body made of a resin having a containing Mikatsu translucent phosphor to substantially cover said chip except for the tip portion and the lower surface of the substrate of the bump, and the resin sealing body It has a side surface perpendicular to the substrate.
By configuring in this way, a desired emission color can be realized by mixing the light emitted by the semiconductor layer and the light emitted by the phosphor.
In the nitride semiconductor light emitting device according to the present invention configured as described above, since the resin sealing body is formed except for the tip portion of the bump and the lower surface of the substrate, the n-type and p-type semiconductors are formed. Since the layer and each electrode can be protected, handling during mounting can be facilitated. Here, in this specification, the upper surface means not the upper and lower sides when mounted, but the surface on the side where the semiconductor layer and the electrode layer are formed in the nitride semiconductor light emitting device, and the lower surface means the semiconductor layer is formed. This is the opposite of the surface.
[0006]
In the nitride semiconductor light emitting device of the present invention, the n-type semiconductor layer may include one or more nitride semiconductor layers, and the p-type semiconductor layer may include one or more nitride semiconductor layers. Good.
[0007]
Furthermore, in the nitride semiconductor light emitting device of the present invention, it is preferable that the resin encapsulant has a bottom surface located substantially on the same plane as the lower surface outside the lower surface of the substrate. Since a relatively thick resin sealing body can be formed outside the side surface, the n-type and p-type semiconductor layers and the electrodes can be more effectively protected.
[0009]
In the nitride semiconductor light emitting device of the present invention, the resin encapsulant may include reflection / scattering particles. When configured in this manner, the resin sealing body emits light particularly when mounted so as to emit light from the lower surface of the substrate. The light extraction efficiency can be improved.
[0010]
A method for manufacturing a nitride semiconductor light emitting device according to the present invention is a method for manufacturing a nitride semiconductor light emitting device by separating a plurality of devices formed on a wafer for each device,
A groove forming step of forming a separation groove between the elements of the wafer;
A resin forming step of forming a translucent resin on the wafer on which the separation groove is formed and filling the separation groove with resin, and curing the resin;
A polishing step of polishing the lower surface of the wafer until the cured resin of the separation groove is exposed;
A cutting step of cutting the cured resin of the separation groove,
The nitride semiconductor light emitting device includes an n-type semiconductor layer in which an n-electrode is formed, a light-emitting layer made of a nitride semiconductor, and a p-type semiconductor layer in which a p-electrode is formed on a substrate obtained by cutting the wafer. And comprising
Bumps are respectively formed on the n electrode and the p electrode,
In the resin forming step, a phosphor is contained in the resin, and the resin is formed so as to substantially cover each element except for a tip portion of the bump.
In the method of manufacturing a nitride semiconductor light emitting device configured as described above, since the resin sealing body is shaped by polishing and cutting after the resin is cured, the resin sealing body can be processed with high dimensional accuracy. Thus, a nitride semiconductor light emitting device with little variation in dimension of the outer shape can be manufactured.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments according to the present invention will be described below with reference to the drawings.
Embodiment 1 FIG.
As shown in FIGS. 1 and 2, the semiconductor chip according to the first embodiment of the present invention has an n-type semiconductor layer 2 made of, for example, an n-type nitride semiconductor doped with Si on a substrate 1 made of sapphire. A nitride semiconductor light-emitting device in which a light-emitting layer (not shown) made of a nitride semiconductor and a p-type semiconductor layer 3 made of a p-type nitride semiconductor doped with Mg are laminated, and has the following configuration Has been.
[0013]
(Configuration of electrode part)
An n pad electrode 22 is formed on the n type semiconductor layer 2 exposed by removing a part of the p type semiconductor layer 3, and a p full surface electrode 31 is formed on almost the entire surface of the p type semiconductor layer. A p-pad electrode 32 is formed on a part of 31.
Here, on the substrate 1, the protective film 4 made of SiO 2 is formed so as to cover the n-type semiconductor layer 2, the p-type semiconductor layer 3 and the p-full-surface electrode 31 except for the upper surfaces of the n-pad electrode 22 and the p-pad electrode 32. A protective film 5 made of polyimide, for example, is formed thereon.
Bumps 23 and 33 are formed on the n pad electrode 22 and the p pad electrode 32 so that the upper end surfaces thereof are flat and have almost the same height.
[0014]
(Resin encapsulant)
In the semiconductor chip of the first embodiment, the resin sealing body 7 is formed so as to cover the entire element except for the upper end portion of the bump 23, the upper end portion of the bump 33, and the lower surface of the substrate 1.
Here, in the semiconductor chip of the first embodiment, the resin sealing body 7 is formed so as to have the side surface 7a perpendicular to the substrate 1, and thereby the outer shape of the semiconductor chip of the first embodiment is a rectangular parallelepiped. The
In FIG. 2, a portion denoted by reference numeral 7 b is a bottom surface of the resin sealing body 7 formed so as to surround the lower surface of the substrate 1, and is substantially flush with the bottom surface of the substrate 1. It is formed so that it may be located in.
In the semiconductor chip of the first embodiment, as shown in FIG. 1, an electrode layer 24 is formed on the upper surface of the resin sealing body 7 so as to connect the two exposed bumps 23 to each other, and the resin sealing is performed. An electrode layer 34 is formed on the upper surface of the stopper 7 so as to connect the two exposed bumps 33 to each other.
[0015]
In the semiconductor chip according to the first embodiment configured as described above, since the portion constituting the element is protected by the substrate 1 and the resin sealing body 7, for example, destruction of the element during mounting is prevented. It is also possible to prevent the die bond resin from adhering to the electrode surface.
[0016]
Hereinafter, a method for manufacturing the semiconductor chip according to the first embodiment will be described.
In the following FIGS. 3 to 4, the p-type and n-type semiconductor layers and the electrodes such as the n and p electrodes are omitted.
[0017]
(Process for forming each element region)
In this manufacturing method, first, a plurality of elements corresponding to the respective semiconductor chips are formed on a wafer 100 made of sapphire.
Specifically, an n-type semiconductor layer and a p-type semiconductor layer are formed on the wafer 100, and the n-type semiconductor layer and the p-type semiconductor layer located between the elements are removed by etching to separate each element. To do.
Hereinafter, a portion removed by etching between the elements is referred to as an element isolation region, and is denoted by reference numerals 41 and 42 in FIG.
Here, the element isolation regions 41 are formed to be parallel to each other, and the element isolation regions 42 are formed to be parallel to each other.
The element isolation region 41 and the element isolation region 42 are formed so as to be orthogonal to each other.
[0018]
Next, an n-pad electrode 22 is formed on the n-type semiconductor layer 2 exposed by removing a part of the p-type semiconductor layer 3 in each element region to expose the n-type semiconductor layer 2.
Further, a p full surface electrode 31 is formed on almost the entire surface of the p type semiconductor layer 3, and a p pad electrode 32 is formed on a part of the n full surface electrode 31.
Next, a protective film 4 made of SiO 2 is formed so as to cover the n-type semiconductor layer 2, the p-type semiconductor layer 3, and the p-full-surface electrode 31 except for the upper surfaces of the n-pad electrode 22 and the p-pad electrode 32. A protective film 5 made of polyimide is formed.
Then, bumps 23 and 33 are formed on the n pad electrode 22 and the p pad electrode 32, respectively.
[0019]
(Separation groove forming process)
Next, as shown in FIGS. 3B and 5, a separation groove 51 having a predetermined shape is formed on the surface of the wafer exposed in the element isolation regions 41 and 42 using, for example, a dicing saw.
Here, the separation groove 51 is set to a depth of 200 μm and a width of 100, for example.
When the width of the separation width 51 is shallower than 200 μm, the time for dicing can be shortened and the amount of wear of the dicing blade (dicing saw blade) can be reduced. In this case, in the substrate polishing step described later, the polishing amount of the substrate becomes large, so that the polishing time becomes long. However, since the polishing of the wafer can be processed in a large amount (a large number) at a time, there is no particular problem.
However, since the strength of the resin that holds the chip after polishing decreases, it is necessary to set the depth of the separation groove 51 so that a constant holding strength can be maintained.
Conversely, when the width of the separation width 51 is set deeper than 200 μm, the amount of wear of the dicing blade increases and the time for dicing increases, but the strength for holding the chip after polishing improves.
Accordingly, the depth of the separation groove 51 is set to an optimum value in consideration of the strength of the resin and the like.
The resin filled in the separation groove contains a filler, which can soften the resin, suppress thermal shrinkage in the polishing step, and has an effect of making the sapphire substrate difficult to break.
Further, the dicing saw used in the separation groove forming step has a blade thickness larger than that of the dicing saw used in the cutting step described later.
[0020]
(Encapsulation resin layer formation process)
Next, as shown in FIG. 3C, a sealing resin layer 70 is formed so as to cover the entire top surface of the wafer and cured.
Then, as shown in FIG. 4A, the cured sealing resin layer 70 is polished from the upper surface until the upper end surfaces of the bumps 23 and 33 are exposed. As a result, the upper end surfaces of the bump 23 and the bump 33 are flat and have substantially the same height.
[0021]
Next, as shown in FIG. 4B, electrode layers 24 and 34 are formed on the exposed bumps 23 and 33, respectively.
In the first embodiment, as shown in FIG. 6, the electrode layer 24 is formed so as to connect the two exposed bumps 23, and the electrode layer 34 is formed so as to connect the two bumps 33.
As described above, in the semiconductor chip according to the first embodiment, the electrode layers 24 and 34 are formed large to facilitate connection with an external circuit.
Specifically, for example, a resist having openings having shapes corresponding to the electrode layers 24 and 34 shown in FIG. 6 is formed on the resin sealing body 70, and a metal layer is formed on the entire surface by sputtering from thereover. Thereafter, the resist is removed (lifted off) together with the metal layer formed thereon, whereby the electrode layers 24 and 34 having a predetermined shape can be formed.
[0022]
(Substrate polishing process)
Next, the substrate 1 is polished from the lower surface of the substrate 1 until it reaches the bottoms of the separation grooves 51 and 52, and as shown in FIG. 4C, the resin seal filled in the separation grooves 51 and 52 on the lower surface of the substrate. The stop body 70 is exposed.
(Cutting process)
Next, as shown in FIG. 4D, the resin sealing body 70 filled in the separation grooves 51 and 52 is, for example, a central portion of each separation groove using a dicing saw having a blade thickness of 20 μm. And cut along the separation groove.
[0023]
The semiconductor chip according to the first embodiment shown in FIGS. 1 and 2 is manufactured through the steps as described above.
[0024]
In the manufacturing method according to the first embodiment configured as described above, the separation grooves 51 are formed between the elements in the wafer 100, the separation grooves 51 are filled with resin and cured, and the lower surface of the wafer 100 is separated. After polishing until the cured resin is exposed in the groove 51, the cured resin is cut at the portion of the separation groove 51, so that the individual sapphire is cut without cutting the sapphire by cutting only the resin. It can be separated into elements.
In this manufacturing method, a step of forming a separation groove and a step of polishing the lower surface of the substrate are required, but cutting is easier than when a sapphire substrate is cut. Easy to automate.
[0025]
Further, in the manufacturing method of the first embodiment, since it is not necessary to cut the sapphire substrate directly except in the step of forming the separation groove, the semiconductor device can be separated into each element without causing chipping or cracking, and has high reliability. Chips can be manufactured with high yield.
[0026]
Further, according to the manufacturing method of the first embodiment, since the resin sealing body is cut perpendicularly to the wafer 100 in the separation grooves 51 and 52 orthogonal to each other, a rectangular semiconductor chip can be easily manufactured. Can do.
Further, in the semiconductor chip of the second embodiment, since the resin sealing body 7 is processed by polishing and cutting after the resin is cured, for example, the resin layer is formed after being divided into individual elements to form the resin Since the resin sealing body can be processed with high dimensional accuracy as compared with the case of sealing, a semiconductor chip with less dimensional variation of the outer shape can be manufactured.
As described above, the semiconductor chip of the first embodiment manufactured by the above manufacturing method has a square shape and can reduce variations in the dimensions of the outer shape, so that stable mounting can be easily realized.
[0027]
Embodiment 2. FIG.
The semiconductor chip according to the second embodiment of the present invention is a light-emitting element chip using a light-transmitting resin as the resin sealing body 70 and containing a phosphor in the resin.
That is, the semiconductor chip of the second embodiment is configured as follows.
(1) The p whole surface electrode 31 is made of a light-transmitting electrode made of, for example, a thin metal film so that light emitted from the light emitting layer is extracted from the side on which the electrode is formed.
(2) Moreover, the resin sealing body 70 contains a phosphor that generates light having a wavelength different from that of the light absorbed and absorbed by the light emitting layer.
(3) The configuration other than the above (1) and (2) is the same as in the first embodiment.
[0028]
The semiconductor chip manufacturing method of the second embodiment is the same as the manufacturing method of the first embodiment except that a resin containing a phosphor is used as the resin of the resin sealing body 70.
[0029]
In the semiconductor chip of the second embodiment configured as described above, for example, a nitride semiconductor is used as an n-type semiconductor layer and a p-type semiconductor layer, respectively, and blue light is emitted in the light-emitting layer, and as a phosphor, for example, cerium. By using a phosphor such as yttrium / aluminum / garnet phosphor activated in step 1, white light is observed due to color mixture of light emitted from the light emitting layer and light emitted from the phosphor.
[0030]
Since the semiconductor chip of the second embodiment configured as described above is entirely covered with the resin sealing body 70 except for the lower surface of the substrate 1, the chromaticity variation can be reduced.
For example, if the side surface (or part thereof) of the substrate 1 is not covered with a resin containing a phosphor, light emitted from the light emitting layer is directly emitted from that part, and the whole becomes bluish white. However, since the semiconductor chip of the second embodiment can be covered with the resin containing the phosphor without exposing the side surface of the substrate 1, such inconvenience can be prevented.
[0031]
Hereinafter, a mounting example of the semiconductor chip according to the first or second embodiment of the present invention will be described.
Implementation Example 1
Mounting Example 1 is a mounting example when the semiconductor chip according to the present invention is flip-chip bonded (FIG. 7).
That is, in this mounting example, as shown in FIG. 7, the electrode layers 24, 34 of the semiconductor chip are opposed to electrodes (not shown) formed on the mounting substrate 90 and connected by solder 80.
In this example, the emitted light is emitted from the lower surface of the substrate.
When flip-chip bonding is used as described above, the resin sealing body 7 of the semiconductor chip preferably contains, for example, reflective scattering particles such as titanium oxide. When the reflection / scattering particles are contained, light emitted from the side surface of the substrate and the electrode side of the substrate can be reflected by the reflection / scattering particles and emitted from the lower surface of the substrate, so that the light extraction efficiency can be improved. .
[0032]
Further, when used by flip-chip bonding, particles having good thermal conductivity such as AlN may be contained in the resin sealing body 7 of the semiconductor chip. Since heat conductivity can be improved, heat dissipation characteristics can be improved.
Further, when used by flip-chip bonding, it is preferable to use a resin having excellent heat resistance as the material of the resin sealing body 7 of the semiconductor chip, thereby enabling reflow soldering and deterioration caused thereby. Can be prevented.
[0033]
Implementation example 2
As shown in FIG. 8, this mounting example 2 uses a wire 82 made of, for example, Au or Al in order to extract light from the upper surface of the substrate 1, that is, the side on which the electrode of the substrate 1 is formed. It is the example connected by wire bonding.
For example, such a mounting method is used in the semiconductor chip of the second embodiment.
With such a mounting method, the element according to the present invention is covered with the resin sealing body 7 having a substantially vertical side surface, so that the die bond resin 83 wraps around and adheres to the upper surface of the resin sealing body 7 ( Can be prevented).
Here, in this mounting example, an epoxy resin or a silver paste can be used as the die bond resin.
[0034]
In the first and second embodiments, the light emitting element chip using the nitride semiconductor has been described. However, the present invention is not limited to this, and the present invention can also be applied to elements using other semiconductor materials. .
Further, the present invention is not limited to the light emitting element chip, but can be applied to a light receiving element and further to a diode and a transistor other than the light-related element.
[0035]
【The invention's effect】
As described above in detail, in the semiconductor chip according to the present invention, a resin sealing body is formed so as to substantially cover the chip except for the tip portion of the bump and the lower surface of the substrate, and the resin sealing is performed. Since the stationary body has a side surface perpendicular to the substrate, each semiconductor layer and each electrode can be protected, handling at the time of mounting can be facilitated, and the resin-sealed body is attached to the substrate. Since it has a vertical side surface, handling during mounting can be facilitated.
Therefore, according to the present invention, a semiconductor chip that is easy to handle can be provided.
[0036]
Further, a semiconductor chip manufacturing method according to the present invention includes a groove forming step of forming a separation groove between elements of the wafer, a resin formation step of forming a resin so that the separation groove is filled with resin, A polishing step of polishing the wafer until the cured resin of the separation groove is exposed; and a cutting step of cutting the cured resin of the separation groove, thereby polishing and cutting the resin after curing the resin. Since the shape processing of the sealing body is performed, the resin sealing body can be processed with high dimensional accuracy, a semiconductor chip with less dimensional variation in the outer shape can be manufactured, and chipping and cracking can be easily prevented, Moreover, it can be easily automated.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor chip (light emitting element chip) according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line AA ′ in FIG.
3A is a cross-sectional view after forming an element portion, FIG. 3B is a cross-sectional view after forming a separation groove, and FIG. 3B is a cross-sectional view after forming a resin layer in the semiconductor chip manufacturing method of the first embodiment; It is a figure (c).
4A is a cross-sectional view after polishing a resin layer, FIG. 4B is a cross-sectional view after forming an electrode layer for connecting bumps, and a substrate is polished in the method for manufacturing a semiconductor chip of Embodiment 1. FIG. It is sectional drawing (c) after having performed, and sectional drawing (d) after cut | disconnecting the resin layer in a separation groove.
5 is a plan view after forming a separation groove in the method for manufacturing a semiconductor chip according to the first embodiment; FIG.
6 is a plan view after a resin layer is polished and an electrode layer for connecting bumps is formed in the method for manufacturing a semiconductor chip according to the first embodiment; FIG.
FIG. 7 is a cross-sectional view showing a state when the semiconductor chip according to the present invention is flip-chip mounted.
FIG. 8 is a cross-sectional view showing a state when a semiconductor chip according to the present invention is mounted using wire bonding.
[Explanation of symbols]
1 ... substrate,
2 ... n-type semiconductor layer,
3 ... p-type semiconductor layer,
4, 5 ... Protective film,
7 ... Resin sealing body,
7a: side surface of the resin sealing body,
7b: bottom surface of the resin sealing body 7,
22 ... n pad electrodes 23, 33 ... bumps,
24, 34 ... electrode layers,
31 ... p full surface electrode,
32 ... p pad electrode,
41, 42 ... element isolation region,
51, 52 ... separation groove,
80 ... Solder,
82 ... Wire,
90 ... Mounting board,
100: Wafer.

Claims (5)

基板上に、n電極が形成されたn型半導体層と、窒化物半導体からなる発光層と、p電極が形成されたp型半導体層と、を備え、
上記n電極上及びp電極上にそれぞれバンプが形成されてなる窒化物半導体発光素子において、
上記バンプの先端部分と基板の下面を除いて上記チップを実質的に覆うように蛍光体を含みかつ透光性を有する樹脂からなる樹脂封止体が形成され、かつ該樹脂封止体は上記基板に垂直な側面を有することを特徴とする窒化物半導体発光素子。
An n-type semiconductor layer in which an n-electrode is formed on a substrate, a light-emitting layer made of a nitride semiconductor, and a p-type semiconductor layer in which a p-electrode is formed,
In the nitride semiconductor light emitting device in which bumps are respectively formed on the n electrode and the p electrode,
A resin sealing body made of a resin including a phosphor and having a light-transmitting property is formed so as to substantially cover the chip except for the tip portion of the bump and the lower surface of the substrate, and the resin sealing body is the above-mentioned A nitride semiconductor light emitting device having a side surface perpendicular to a substrate.
上記n型半導体層は1又は2以上の窒化物半導体層を含んでなり、上記p型半導体層は1又は2以上の窒化物半導体層を含んでなる請求項1記載の窒化物半導体発光素子。  2. The nitride semiconductor light emitting device according to claim 1, wherein the n-type semiconductor layer includes one or more nitride semiconductor layers, and the p-type semiconductor layer includes one or more nitride semiconductor layers. 上記樹脂封止体は、上記基板の下面の外側に該下面と実質的に同一平面上に位置する底面を有する請求項1又は2記載の窒化物半導体発光素子。  3. The nitride semiconductor light emitting element according to claim 1, wherein the resin sealing body has a bottom surface that is positioned substantially on the same plane as the lower surface outside the lower surface of the substrate. 上記樹脂封止体は、反射散乱粒子を含む請求項1〜3のうちのいずれか1つに記載の窒化物半導体発光素子。  The nitride resin light-emitting element according to claim 1, wherein the resin sealing body includes reflective scattering particles. ウエハ上に形成された複数の素子を素子毎に分離することにより窒化物半導体発光素子を製造する方法であって、
上記ウエハの素子間に分離溝を形成する溝形成工程と、
上記分離溝が形成されたウエハ上に上記分離溝に樹脂が充填されるように透光性を有する樹脂を形成してその樹脂を硬化する樹脂形成工程と、
上記ウエハの下面を、上記分離溝の硬化された樹脂が露出するまで研磨する研磨工程と、
上記分離溝の硬化された樹脂を切断する切断工程とを含み、
上記窒化物半導体発光素子は、上記ウエハが切断されてなる基板上に、n電極が形成されたn型半導体層と、窒化物半導体からなる発光層と、p電極が形成されたp型半導体層と、を備え、
上記n電極上及びp電極上にそれぞれバンプが形成されてなり、
上記樹脂形成工程において、上記樹脂に蛍光体を含有させて、当該樹脂を上記バンプの先端部分を除いて実質的に各素子を覆うように形成することを特徴とする窒化物半導体発光素子の製造方法。
A method for manufacturing a nitride semiconductor light emitting device by separating a plurality of devices formed on a wafer for each device,
A groove forming step of forming a separation groove between the elements of the wafer;
A resin forming step of forming a translucent resin on the wafer on which the separation groove is formed and filling the separation groove with resin, and curing the resin;
A polishing step of polishing the lower surface of the wafer until the cured resin of the separation groove is exposed;
A cutting step of cutting the cured resin of the separation groove,
The nitride semiconductor light emitting device includes an n-type semiconductor layer in which an n-electrode is formed, a light-emitting layer made of a nitride semiconductor, and a p-type semiconductor layer in which a p-electrode is formed on a substrate obtained by cutting the wafer. And comprising
Bumps are respectively formed on the n electrode and the p electrode,
In the resin forming step, a phosphor is contained in the resin, and the resin is formed so as to substantially cover each element except for the tip portion of the bump. Method.
JP2001195072A 2001-06-27 2001-06-27 Semiconductor chip and manufacturing method thereof Expired - Fee Related JP4529319B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001195072A JP4529319B2 (en) 2001-06-27 2001-06-27 Semiconductor chip and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001195072A JP4529319B2 (en) 2001-06-27 2001-06-27 Semiconductor chip and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2003007929A JP2003007929A (en) 2003-01-10
JP4529319B2 true JP4529319B2 (en) 2010-08-25

Family

ID=19033109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001195072A Expired - Fee Related JP4529319B2 (en) 2001-06-27 2001-06-27 Semiconductor chip and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4529319B2 (en)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004040661A2 (en) * 2002-10-30 2004-05-13 Osram Opto Semiconductors Gmbh Method for producing a light source provided with electroluminescent diodes and comprising a luminescence conversion element
US7915085B2 (en) 2003-09-18 2011-03-29 Cree, Inc. Molded chip fabrication method
KR100723247B1 (en) * 2006-01-10 2007-05-29 삼성전기주식회사 Chip coating type light emitting diode package and fabrication method thereof
US9196799B2 (en) 2007-01-22 2015-11-24 Cree, Inc. LED chips having fluorescent substrates with microholes and methods for fabricating
US9024349B2 (en) 2007-01-22 2015-05-05 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9159888B2 (en) * 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
US9041285B2 (en) 2007-12-14 2015-05-26 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8167674B2 (en) 2007-12-14 2012-05-01 Cree, Inc. Phosphor distribution in LED lamps using centrifugal force
US8878219B2 (en) 2008-01-11 2014-11-04 Cree, Inc. Flip-chip phosphor coating method and devices fabricated utilizing method
JP4799606B2 (en) 2008-12-08 2011-10-26 株式会社東芝 Optical semiconductor device and method for manufacturing optical semiconductor device
JP4724222B2 (en) 2008-12-12 2011-07-13 株式会社東芝 Method for manufacturing light emitting device
US7897419B2 (en) * 2008-12-23 2011-03-01 Cree, Inc. Color correction for wafer level white LEDs
US7989824B2 (en) * 2009-06-03 2011-08-02 Koninklijke Philips Electronics N.V. Method of forming a dielectric layer on a semiconductor light emitting device
JP2011009572A (en) * 2009-06-26 2011-01-13 Citizen Electronics Co Ltd Flip-chip packaging type led and method for manufacturing flip-chip packaging type led
DE102009036621B4 (en) 2009-08-07 2023-12-21 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelectronic semiconductor component
JP2011071272A (en) 2009-09-25 2011-04-07 Toshiba Corp Semiconductor light-emitting device and method for manufacturing the same
WO2011099384A1 (en) * 2010-02-09 2011-08-18 日亜化学工業株式会社 Light emitting device and method for manufacturing light emitting device
EP2363749B1 (en) 2010-03-05 2015-08-19 Rohm and Haas Electronic Materials, L.L.C. Methods of forming photolithographic patterns
WO2011145794A1 (en) 2010-05-18 2011-11-24 서울반도체 주식회사 Light emitting diode chip having wavelength conversion layer and manufacturing method thereof, and package including same and manufacturing method thereof
CN103003966B (en) * 2010-05-18 2016-08-10 首尔半导体株式会社 There is light emitting diode chip and the manufacture method thereof of wavelength conversion layer, and include its packaging part and manufacture method thereof
JP4875185B2 (en) 2010-06-07 2012-02-15 株式会社東芝 Optical semiconductor device
JP5414627B2 (en) 2010-06-07 2014-02-12 株式会社東芝 Semiconductor light emitting device and manufacturing method thereof
JP5759790B2 (en) * 2010-06-07 2015-08-05 株式会社東芝 Manufacturing method of semiconductor light emitting device
US10546846B2 (en) 2010-07-23 2020-01-28 Cree, Inc. Light transmission control for masking appearance of solid state light sources
JP5882332B2 (en) 2010-09-06 2016-03-09 ヘレーウス ノーブルライト ゲゼルシャフト ミット ベシュレンクテルハフツングHeraeus Noblelight GmbH Coating methods for optoelectronic chip-on-board modules
US9166126B2 (en) 2011-01-31 2015-10-20 Cree, Inc. Conformally coated light emitting devices and methods for providing the same
JP5763365B2 (en) * 2011-02-24 2015-08-12 日東電工株式会社 Light emitting diode element and light emitting diode device
JP2012175069A (en) * 2011-02-24 2012-09-10 Nitto Denko Corp Manufacturing method of light emitting diode device
JP2012216712A (en) * 2011-03-28 2012-11-08 Nitto Denko Corp Method for manufacturing light-emitting diode device and light-emitting element
JP5953386B2 (en) * 2011-03-28 2016-07-20 日東電工株式会社 Method for manufacturing light emitting diode device
US9269878B2 (en) 2011-05-27 2016-02-23 Lg Innotek Co., Ltd. Light emitting device and light emitting apparatus
JP2013012559A (en) * 2011-06-29 2013-01-17 Nichia Chem Ind Ltd Manufacturing method of light emitting element
JP2013077679A (en) * 2011-09-30 2013-04-25 Citizen Electronics Co Ltd Semiconductor light-emitting device and manufacturing method of the same
JP5364771B2 (en) * 2011-10-17 2013-12-11 株式会社東芝 Optical semiconductor device and manufacturing method thereof
KR101969334B1 (en) 2011-11-16 2019-04-17 엘지이노텍 주식회사 Light emitting device and light emitting apparatus having the same
JP2013140942A (en) * 2011-12-07 2013-07-18 Toshiba Corp Semiconductor light-emitting device
US9172001B2 (en) * 2011-12-08 2015-10-27 Koninklijke Philips N.V. Semiconductor light emitting device with thick metal layers
TWI447975B (en) * 2012-01-05 2014-08-01 矽品精密工業股份有限公司 Led chip structure, led package substrate, led package structure and method of forming same
JP5946311B2 (en) * 2012-04-11 2016-07-06 シチズンホールディングス株式会社 LED module
JP6307907B2 (en) 2013-02-12 2018-04-11 日亜化学工業株式会社 Method for manufacturing light emitting device
JP2014157991A (en) * 2013-02-18 2014-08-28 Toshiba Corp Semiconductor light-emitting device and method of manufacturing the same
JP6394052B2 (en) * 2013-05-13 2018-09-26 日亜化学工業株式会社 Light emitting device and manufacturing method thereof
JP5537700B2 (en) * 2013-05-23 2014-07-02 株式会社東芝 Semiconductor light emitting device
JP5931006B2 (en) * 2013-06-03 2016-06-08 日亜化学工業株式会社 Light emitting device
JP5837006B2 (en) * 2013-07-16 2015-12-24 株式会社東芝 Manufacturing method of optical semiconductor device
WO2015008243A1 (en) * 2013-07-19 2015-01-22 Koninklijke Philips N.V. Pc led with optical element and without substrate carrier
WO2015011583A1 (en) 2013-07-22 2015-01-29 Koninklijke Philips N.V. Method of separating light emitting devices formed on a substrate wafer
JP6098439B2 (en) 2013-08-28 2017-03-22 日亜化学工業株式会社 Wavelength conversion member, light emitting device, and method of manufacturing light emitting device
JP5834109B2 (en) * 2014-05-14 2015-12-16 株式会社東芝 Semiconductor light emitting device, method for manufacturing semiconductor light emitting device, and method for manufacturing light emitting device
JP5721894B2 (en) * 2014-09-25 2015-05-20 株式会社東芝 Optical semiconductor device
KR102263065B1 (en) * 2014-09-26 2021-06-10 서울바이오시스 주식회사 Light emitting device and method of fabricating the same
TWI677113B (en) * 2014-12-24 2019-11-11 晶元光電股份有限公司 Light-emitting device and manufacturing method thereof
JP6387973B2 (en) 2016-01-27 2018-09-12 日亜化学工業株式会社 Light emitting device
CN106374020B (en) * 2016-11-02 2019-05-03 厦门市三安光电科技有限公司 A kind of production method and its thin film chip of thin film chip
JP6760356B2 (en) * 2018-12-04 2020-09-23 日亜化学工業株式会社 Light emitting device and manufacturing method of light emitting device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177434A (en) * 1992-12-08 1994-06-24 Nichia Chem Ind Ltd Blue color light-emitting device and its manufacture
JPH1079362A (en) * 1996-07-12 1998-03-24 Fujitsu Ltd Manufacture of semiconductor device, mold for manufacturing semiconductor device, semiconductor device and mounting method thereof
JP2000031548A (en) * 1998-07-09 2000-01-28 Stanley Electric Co Ltd Surface mount light-emitting diode and its manufacture
JP2000068401A (en) * 1998-08-18 2000-03-03 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2001085747A (en) * 1999-09-13 2001-03-30 Sanken Electric Co Ltd Semiconductor light-emitting device
JP2001093926A (en) * 1999-07-16 2001-04-06 Matsushita Electric Ind Co Ltd Semiconductor element package and manufacturing method
JP2001144213A (en) * 1999-11-16 2001-05-25 Hitachi Ltd Method for manufacturing semiconductor device and semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177434A (en) * 1992-12-08 1994-06-24 Nichia Chem Ind Ltd Blue color light-emitting device and its manufacture
JPH1079362A (en) * 1996-07-12 1998-03-24 Fujitsu Ltd Manufacture of semiconductor device, mold for manufacturing semiconductor device, semiconductor device and mounting method thereof
JP2000031548A (en) * 1998-07-09 2000-01-28 Stanley Electric Co Ltd Surface mount light-emitting diode and its manufacture
JP2000068401A (en) * 1998-08-18 2000-03-03 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2001093926A (en) * 1999-07-16 2001-04-06 Matsushita Electric Ind Co Ltd Semiconductor element package and manufacturing method
JP2001085747A (en) * 1999-09-13 2001-03-30 Sanken Electric Co Ltd Semiconductor light-emitting device
JP2001144213A (en) * 1999-11-16 2001-05-25 Hitachi Ltd Method for manufacturing semiconductor device and semiconductor device

Also Published As

Publication number Publication date
JP2003007929A (en) 2003-01-10

Similar Documents

Publication Publication Date Title
JP4529319B2 (en) Semiconductor chip and manufacturing method thereof
US9793448B2 (en) Light emitting diode chip having wavelength converting layer and method of fabricating the same, and package having the light emitting diode chip and method of fabricating the same
US10283670B2 (en) Method for manufacturing light emitting device
EP2325906B1 (en) Semiconductor light-emitting device and method for manufacturing same
JP6545981B2 (en) Semiconductor light emitting device
KR101158242B1 (en) Semiconductor light emitting device and method of fabricating semiconductor light emitting device
JP5918221B2 (en) LED chip manufacturing method
TWI637537B (en) Light emitting device and method of manufacturing the same
JP3399440B2 (en) Composite light emitting element, light emitting device and method of manufacturing the same
KR101092063B1 (en) Light emitting device package and method for fabricating the same
US8946749B2 (en) Semiconductor light emitting device
US10461227B2 (en) Method for manufacturing light emitting device, and light emitting device
TWI590495B (en) Phosphor separated from led by transparent spacer
JP2008505508A (en) Chip scale method for packaging light emitting device and light emitting device packaged on chip scale
JP6185415B2 (en) Semiconductor light emitting device
JP4590994B2 (en) Light emitting device and manufacturing method thereof
US12057535B2 (en) Flip chip LED with side reflectors encasing side surfaces of a semiconductor structure and phosphor
JP2016171188A (en) Semiconductor light emission device and manufacturing method for the same
WO2017154975A1 (en) Semiconductor light emitting device
JP3509740B2 (en) Method of manufacturing semiconductor light emitting device and semiconductor light emitting device
KR101893701B1 (en) Uv led package
US20050161779A1 (en) Flip chip assemblies and lamps of high power GaN LEDs, wafer level flip chip package process, and method of fabricating the same
JP2006173197A (en) Optical semiconductor element, manufacturing method thereof, and optical semiconductor device
JP2002100813A (en) Wavelength-converting paste material, semiconductor light-emitting device and its manufacturing method
KR101461153B1 (en) Method of manufacutruing semiconductor device structure

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20051104

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20051104

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060206

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070531

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20080131

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090511

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090519

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090716

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090818

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091118

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20100114

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100223

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100423

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100518

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100531

R150 Certificate of patent or registration of utility model

Ref document number: 4529319

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130618

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130618

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130618

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees