JP4458584B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

Info

Publication number
JP4458584B2
JP4458584B2 JP25336499A JP25336499A JP4458584B2 JP 4458584 B2 JP4458584 B2 JP 4458584B2 JP 25336499 A JP25336499 A JP 25336499A JP 25336499 A JP25336499 A JP 25336499A JP 4458584 B2 JP4458584 B2 JP 4458584B2
Authority
JP
Japan
Prior art keywords
read
column
signal
circuit
read data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP25336499A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001076482A (ja
JP2001076482A5 (enExample
Inventor
彰 山崎
直也 渡邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP25336499A priority Critical patent/JP4458584B2/ja
Priority to US09/654,876 priority patent/US6249476B1/en
Publication of JP2001076482A publication Critical patent/JP2001076482A/ja
Publication of JP2001076482A5 publication Critical patent/JP2001076482A5/ja
Application granted granted Critical
Publication of JP4458584B2 publication Critical patent/JP4458584B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
JP25336499A 1999-09-07 1999-09-07 半導体記憶装置 Expired - Fee Related JP4458584B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP25336499A JP4458584B2 (ja) 1999-09-07 1999-09-07 半導体記憶装置
US09/654,876 US6249476B1 (en) 1999-09-07 2000-09-05 Semiconductor memory device suitable for mounting mixed with logic circuit, having short cycle time in reading operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25336499A JP4458584B2 (ja) 1999-09-07 1999-09-07 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2001076482A JP2001076482A (ja) 2001-03-23
JP2001076482A5 JP2001076482A5 (enExample) 2006-10-05
JP4458584B2 true JP4458584B2 (ja) 2010-04-28

Family

ID=17250330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25336499A Expired - Fee Related JP4458584B2 (ja) 1999-09-07 1999-09-07 半導体記憶装置

Country Status (2)

Country Link
US (1) US6249476B1 (enExample)
JP (1) JP4458584B2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002184188A (ja) * 2000-12-18 2002-06-28 Mitsubishi Electric Corp 半導体記憶装置
US6512683B2 (en) * 2001-04-05 2003-01-28 International Business Machines Corporation System and method for increasing the speed of memories
US20030058698A1 (en) * 2001-09-26 2003-03-27 Gerhard Mueller Memory with high performance unit architecture
JPWO2004042821A1 (ja) * 2002-11-08 2006-03-09 株式会社日立製作所 半導体記憶装置
JP2006216693A (ja) * 2005-02-02 2006-08-17 Toshiba Corp 半導体記憶装置
TWI326456B (en) * 2007-03-30 2010-06-21 Nanya Technology Corp Memory and operation method thereof
US9177631B2 (en) * 2009-09-22 2015-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit with switch between sense amplifier and data line and method for operating the same
US8891305B2 (en) 2012-08-21 2014-11-18 Micron Technology, Inc. Apparatuses and methods involving accessing distributed sub-blocks of memory cells
JP2015118724A (ja) * 2013-11-13 2015-06-25 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の駆動方法
KR102498988B1 (ko) 2018-06-11 2023-02-14 삼성전자주식회사 페일 어드레스들을 저장하는 레지스터들의 위치들이 병합된 메모리 장치
CN113760173B (zh) * 2020-06-05 2025-05-02 长鑫存储技术(上海)有限公司 读写转换电路以及存储器
US12299296B2 (en) * 2022-03-10 2025-05-13 Samsung Electronics Co., Ltd. Semiconductor memory device and method of adjusting operation condition of the same
US12014797B2 (en) 2022-04-27 2024-06-18 Micron Technology, Inc. Apparatuses, systems, and methods for managing metadata storage at a memory
CN119923690A (zh) 2022-11-15 2025-05-02 美光科技公司 用于ecc信息、元数据信息或其组合的单遍次存取的设备及方法
JP2025537503A (ja) 2022-11-15 2025-11-18 マイクロン テクノロジー，インク． 構成可能なｅｃｃモードのための装置および方法
US20250077424A1 (en) * 2023-09-05 2025-03-06 Micron Technology, Inc. Apparatuses and methods for half-page modes of memory devices
US20250077103A1 (en) * 2023-09-05 2025-03-06 Micron Technology, Inc. Apparatuses and methods for half-page modes of memory devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204842A (en) * 1987-08-05 1993-04-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory with memory unit comprising a plurality of memory blocks

Also Published As

Publication number Publication date
US6249476B1 (en) 2001-06-19
JP2001076482A (ja) 2001-03-23

Similar Documents

Publication Publication Date Title
JP4458584B2 (ja) 半導体記憶装置
US7035150B2 (en) Memory device with column select being variably delayed
US6314042B1 (en) Fast accessible semiconductor memory device
US8149645B2 (en) Synchronous global controller for enhanced pipelining
US6147925A (en) Semiconductor device allowing fast sensing with a low power supply voltage
US20140204692A1 (en) Semiconductor memory device and method with auxiliary i/o line assist circuit and functionality
US8036049B2 (en) Semiconductor memory device including a global input/output line of a data transfer path and its surrounding circuits
KR100311328B1 (ko) 메모리와 논리 회로를 혼재하고 내부 버스폭을 매우 크게 취한 반도체 집적 회로 장치
JP2001006359A (ja) 半導体記憶装置
US9530459B2 (en) Semiconductor memory device including a repeater circuit on main data lines
US6449198B1 (en) Semiconductor memory device
US6768692B2 (en) Multiple subarray DRAM having a single shared sense amplifier
JP2005032426A (ja) 高速データアクセスメモリアレイ
US6023437A (en) Semiconductor memory device capable of reducing a precharge time
KR100920829B1 (ko) 반도체 메모리 장치
US5715209A (en) Integrated circuit memory devices including a dual transistor column selection switch and related methods
JP2009134840A (ja) 半導体記憶装置
US20030206457A1 (en) Semiconductor device having mechanism capable of high-speed operation
JP2001143470A (ja) 半導体記憶装置
KR100813526B1 (ko) 반도체 메모리 장치
KR100442225B1 (ko) 고속 판독이 가능한 반도체 기억 장치
JP4756581B2 (ja) 半導体記憶装置
JP5442562B2 (ja) 半導体記憶装置
JP2003077277A (ja) 半導体記憶装置
JP5431066B2 (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060822

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060822

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090730

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090818

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091015

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100202

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100209

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130219

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130219

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130219

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140219

Year of fee payment: 4

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees