JP2001076482A5 - - Google Patents
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- JP2001076482A5 JP2001076482A5 JP1999253364A JP25336499A JP2001076482A5 JP 2001076482 A5 JP2001076482 A5 JP 2001076482A5 JP 1999253364 A JP1999253364 A JP 1999253364A JP 25336499 A JP25336499 A JP 25336499A JP 2001076482 A5 JP2001076482 A5 JP 2001076482A5
- Authority
- JP
- Japan
- Prior art keywords
- signal
- read
- read data
- circuit
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000004065 semiconductor Substances 0.000 description 12
- 230000004913 activation Effects 0.000 description 6
- 238000003491 array Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25336499A JP4458584B2 (ja) | 1999-09-07 | 1999-09-07 | 半導体記憶装置 |
| US09/654,876 US6249476B1 (en) | 1999-09-07 | 2000-09-05 | Semiconductor memory device suitable for mounting mixed with logic circuit, having short cycle time in reading operation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25336499A JP4458584B2 (ja) | 1999-09-07 | 1999-09-07 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001076482A JP2001076482A (ja) | 2001-03-23 |
| JP2001076482A5 true JP2001076482A5 (enExample) | 2006-10-05 |
| JP4458584B2 JP4458584B2 (ja) | 2010-04-28 |
Family
ID=17250330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25336499A Expired - Fee Related JP4458584B2 (ja) | 1999-09-07 | 1999-09-07 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6249476B1 (enExample) |
| JP (1) | JP4458584B2 (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002184188A (ja) * | 2000-12-18 | 2002-06-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US6512683B2 (en) * | 2001-04-05 | 2003-01-28 | International Business Machines Corporation | System and method for increasing the speed of memories |
| US20030058698A1 (en) * | 2001-09-26 | 2003-03-27 | Gerhard Mueller | Memory with high performance unit architecture |
| JPWO2004042821A1 (ja) * | 2002-11-08 | 2006-03-09 | 株式会社日立製作所 | 半導体記憶装置 |
| JP2006216693A (ja) * | 2005-02-02 | 2006-08-17 | Toshiba Corp | 半導体記憶装置 |
| TWI326456B (en) * | 2007-03-30 | 2010-06-21 | Nanya Technology Corp | Memory and operation method thereof |
| US9177631B2 (en) * | 2009-09-22 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit with switch between sense amplifier and data line and method for operating the same |
| US8891305B2 (en) | 2012-08-21 | 2014-11-18 | Micron Technology, Inc. | Apparatuses and methods involving accessing distributed sub-blocks of memory cells |
| JP2015118724A (ja) * | 2013-11-13 | 2015-06-25 | 株式会社半導体エネルギー研究所 | 半導体装置及び半導体装置の駆動方法 |
| KR102498988B1 (ko) | 2018-06-11 | 2023-02-14 | 삼성전자주식회사 | 페일 어드레스들을 저장하는 레지스터들의 위치들이 병합된 메모리 장치 |
| CN113760173B (zh) * | 2020-06-05 | 2025-05-02 | 长鑫存储技术(上海)有限公司 | 读写转换电路以及存储器 |
| US12299296B2 (en) * | 2022-03-10 | 2025-05-13 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of adjusting operation condition of the same |
| US12014797B2 (en) | 2022-04-27 | 2024-06-18 | Micron Technology, Inc. | Apparatuses, systems, and methods for managing metadata storage at a memory |
| CN119923690A (zh) | 2022-11-15 | 2025-05-02 | 美光科技公司 | 用于ecc信息、元数据信息或其组合的单遍次存取的设备及方法 |
| JP2025537503A (ja) | 2022-11-15 | 2025-11-18 | マイクロン テクノロジー,インク. | 構成可能なeccモードのための装置および方法 |
| US20250077424A1 (en) * | 2023-09-05 | 2025-03-06 | Micron Technology, Inc. | Apparatuses and methods for half-page modes of memory devices |
| US20250077103A1 (en) * | 2023-09-05 | 2025-03-06 | Micron Technology, Inc. | Apparatuses and methods for half-page modes of memory devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5204842A (en) * | 1987-08-05 | 1993-04-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory with memory unit comprising a plurality of memory blocks |
-
1999
- 1999-09-07 JP JP25336499A patent/JP4458584B2/ja not_active Expired - Fee Related
-
2000
- 2000-09-05 US US09/654,876 patent/US6249476B1/en not_active Expired - Lifetime
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