JP4454399B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4454399B2
JP4454399B2 JP2004173745A JP2004173745A JP4454399B2 JP 4454399 B2 JP4454399 B2 JP 4454399B2 JP 2004173745 A JP2004173745 A JP 2004173745A JP 2004173745 A JP2004173745 A JP 2004173745A JP 4454399 B2 JP4454399 B2 JP 4454399B2
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Japan
Prior art keywords
resin
lead frame
runner
mold
gate
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Expired - Fee Related
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JP2004173745A
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Japanese (ja)
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JP2005353878A (ja
JP2005353878A5 (https=
Inventor
文司 倉冨
洋一 河田
福美 清水
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Renesas Technology Corp
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Renesas Technology Corp
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Publication of JP2005353878A5 publication Critical patent/JP2005353878A5/ja
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Publication of JP4454399B2 publication Critical patent/JP4454399B2/ja
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  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2004173745A 2004-06-11 2004-06-11 半導体装置の製造方法 Expired - Fee Related JP4454399B2 (ja)

Priority Applications (1)

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JP2004173745A JP4454399B2 (ja) 2004-06-11 2004-06-11 半導体装置の製造方法

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Application Number Priority Date Filing Date Title
JP2004173745A JP4454399B2 (ja) 2004-06-11 2004-06-11 半導体装置の製造方法

Publications (3)

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JP2005353878A JP2005353878A (ja) 2005-12-22
JP2005353878A5 JP2005353878A5 (https=) 2007-07-26
JP4454399B2 true JP4454399B2 (ja) 2010-04-21

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JP2004173745A Expired - Fee Related JP4454399B2 (ja) 2004-06-11 2004-06-11 半導体装置の製造方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240006064A (ko) 2021-06-25 2024-01-12 토와 가부시기가이샤 수지 성형 장치, 및 수지 성형품의 제조 방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5054923B2 (ja) * 2006-01-23 2012-10-24 Towa株式会社 電子部品の樹脂封止成形方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240006064A (ko) 2021-06-25 2024-01-12 토와 가부시기가이샤 수지 성형 장치, 및 수지 성형품의 제조 방법

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JP2005353878A (ja) 2005-12-22

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