JP4443315B2 - データ出力バッファ及びこれを用いた半導体メモリ装置 - Google Patents
データ出力バッファ及びこれを用いた半導体メモリ装置 Download PDFInfo
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- JP4443315B2 JP4443315B2 JP2004176541A JP2004176541A JP4443315B2 JP 4443315 B2 JP4443315 B2 JP 4443315B2 JP 2004176541 A JP2004176541 A JP 2004176541A JP 2004176541 A JP2004176541 A JP 2004176541A JP 4443315 B2 JP4443315 B2 JP 4443315B2
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- Prior art keywords
- switching element
- data
- signal
- nmos transistor
- low
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
- Logic Circuits (AREA)
Description
120 ローデコーダ
130 ページバッファ
140 カラムデコーダ
150 カラムマルチプレクサ
160 データ出力バッファ
161 ラッチ
Claims (6)
- カラムマルチプレクサのスイッチング素子を経由した信号を入力とするインバータと、
前記インバータの出力を格納するためのラッチと、
を含み、
前記インバータは、
前記スイッチング素子を経由した信号がローレベルである時、ハイレベルを出力するためのPMOSトランジスタと、
前記スイッチング素子を経由した信号が正常のハイレベル、または正常のハイレベルよりも前記スイッチング素子のしきい値電圧だけ低くなったレベルである時、ローレベルを出力するための低電圧動作NMOSトランジスタと、
前記低電圧動作NMOSトランジスタと接地電源端子との間にデータ出力の時に限り、出力イネーブル信号によってターンオンされるスイッチング素子と、
を含むことを特徴とするデータ出力バッファ。 - 前記低電圧動作NMOSトランジスタのしきい値電圧は、0Vであることを特徴とする請求項1に記載のデータ出力バッファ。
- 前記スイッチング素子は、NMOSトランジスタを含むことを特徴とする請求項1に記載のデータ出力バッファ。
- メモリセルアレイと、
ローアドレス信号に応じて前記メモリセルアレイの特定ページを選択するためのローデコーダと、
前記ローデコーダによって選択されたページに格納されたデータを格納するページバッファと、
カラムアドレス信号によってビットライン選択信号を生成するためのカラムデコーダと、
前記ビットライン選択信号によって前記ページバッファに格納されたデータのうち、いずれか一つを選択して出力するスイッチング素子を含むカラムマルチプレクサと、
前記カラムマルチプレクサのスイッチング素子を経由した信号を入力とするインバータと、
前記インバータの出力を格納するためのラッチと、
を含み、
前記インバータは、
前記スイッチング素子を経由した信号がローレベルである時、ハイレベルを出力するためのPMOSトランジスタと、
前記スイッチング素子を経由した信号が正常のハイレベル、または正常のハイレベルよりも前記スイッチング素子のしきい値電圧だけ低くなったレベルである時、ローレベルを出力するための低電圧動作NMOSトランジスタと、
前記低電圧動作NMOSトランジスタと接地電源端子との間にデータ出力の時に限り、出力イネーブル信号によってターンオンされるスイッチング素子と、
を含むデータ出力バッファと、
を含むことを特徴とする半導体メモリ装置。 - 前記低電圧動作NMOSトランジスタのしきい値電圧は、0Vであることを特徴とする請求項4に記載の半導体メモリ装置。
- 前記スイッチング素子は、NMOSトランジスタを含むことを特徴とする請求項4に記載の半導体メモリ装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030081959A KR100560936B1 (ko) | 2003-11-19 | 2003-11-19 | 데이터 입출력 버퍼 및 이를 이용한 반도체 메모리 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005149694A JP2005149694A (ja) | 2005-06-09 |
JP4443315B2 true JP4443315B2 (ja) | 2010-03-31 |
Family
ID=34567814
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004176541A Expired - Fee Related JP4443315B2 (ja) | 2003-11-19 | 2004-06-15 | データ出力バッファ及びこれを用いた半導体メモリ装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6998873B2 (ja) |
JP (1) | JP4443315B2 (ja) |
KR (1) | KR100560936B1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100933859B1 (ko) * | 2007-11-29 | 2009-12-24 | 주식회사 하이닉스반도체 | 플래시 메모리 소자 및 그것의 프로그램 방법 |
JP5183336B2 (ja) * | 2008-07-15 | 2013-04-17 | 富士フイルム株式会社 | 表示装置 |
JP2010066331A (ja) * | 2008-09-09 | 2010-03-25 | Fujifilm Corp | 表示装置 |
KR102420014B1 (ko) | 2015-09-18 | 2022-07-12 | 삼성전자주식회사 | 비휘발성 인버터 |
US11393845B2 (en) * | 2020-08-28 | 2022-07-19 | Micron Technology, Inc. | Microelectronic devices, and related memory devices and electronic systems |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3568115B2 (ja) * | 2000-05-23 | 2004-09-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体集積回路装置および半導体集積回路装置内のレシーバ回路 |
JP2003308698A (ja) * | 2002-04-12 | 2003-10-31 | Toshiba Corp | 不揮発性半導体メモリ装置 |
US6650168B1 (en) * | 2002-09-30 | 2003-11-18 | Taiwan Semiconductor Manufacturing Company | High-speed level shifter using zero-threshold MOSFETS |
-
2003
- 2003-11-19 KR KR1020030081959A patent/KR100560936B1/ko not_active IP Right Cessation
- 2003-12-23 US US10/743,934 patent/US6998873B2/en not_active Expired - Fee Related
-
2004
- 2004-06-15 JP JP2004176541A patent/JP4443315B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6998873B2 (en) | 2006-02-14 |
JP2005149694A (ja) | 2005-06-09 |
KR20050048115A (ko) | 2005-05-24 |
KR100560936B1 (ko) | 2006-03-14 |
US20050104625A1 (en) | 2005-05-19 |
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