JP4440928B2 - 発光素子とその製造方法 - Google Patents
発光素子とその製造方法 Download PDFInfo
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Description
以下、本発明の一実施形態に係る発光素子とその製造方法について、図面を参照して説明する。FIG.1,FIG.2は、本発明の発光素子1を示す。発光素子1は、p型及びn型窒化物半導体層からなる半導体層2,3を積層し、各半導体層2,3に電流を注入するための半導体面電極21,31と、各半導体層2,3を保持するための絶縁層4と、絶縁層4の半導体層2,3がある面とは反対側(図の上方)の面に設けた実装用の実装面電極5と、を備えている。また、一方の半導体層2は他方の半導体層3と、一部に積層していない非積層部20を持ち、一方の半導体層2に積層された半導体面電極21は非積層部20に積層されている。実装面電極5と半導体面電極21,31とは、絶縁層4に形成したVIA用開口41の内面の導体51によって導通されている。半導体面電極21,31、絶縁層4、及び実装面電極5は、積層された半導体層2,3の一方の面に順に積層されている。
次に、発光素子1の製造工程について説明する。FIG.3Aは、製造工程の概要フローを示す。以下、FIG.2を適宜参照する。発光素子1の製造の最初の基板形成工程(S1)において、透明結晶基板上にp型及びn型窒化物半導体層2,3を積層し、一部に非積層部20を設け、これらの半導体層2,3上に各半導体層2,3に電流を注入するための半導体面電極21,31をそれぞれの電極表面を同一方向に露出した状態で設けてなる半導体基板が形成される。
次に、発光素子1の具体的な製造方法について説明する。FIG.4A〜4Eは主要な製造工程における時系列での素子断面を示し、FIG.5A〜5Eはそれらに対応した発光素子外形を示す。まず、FIG.4A,5Aに示すように、透明結晶基板6の上に、n型窒化物半導体層2を形成し、さらにp型窒化物半導体層3を積層し、一部半導体層2が露出する状態とする。続いて、半導体層2が大きく露出した非積層部20に半導体層2用の半導体面電極21、また、半導体層3の上に半導体面電極31を形成する。以上で、上述の半導体基板が形成される。
次に、絶縁層4を除去してVIA用開口41を形成する一連の方法について説明する。FIG.6は、VIA用開口41をレーザ光L1により加工する状況を示す。絶縁層4を銅箔付樹脂で形成した場合について述べる。半導体面電極21,31の上に積層された絶縁層4を除去してVIA用開口41を形成する方法としてレーザ光L1を用いることができる。レーザとしては、炭酸ガスレーザや高調波YAGレーザ、エキシマレーザなどを用いることができる。加工穴径がφ50μm以上であれば、炭酸ガスレーザが適しており、φ50μm以下では、高調波YAGレーザが適する。
次に、VIAによる放熱性向上について説明する。FIG.9は、内部を充填したVIAを示す。VIA用開口41に導体51を形成する際に、開口内部すべてを熱の良導体である導電性材料で充填した構造とすることで発光部である半導体層2,3の放熱性を向上させることができる。導電性材料の充填は、VIA用開口41の内表面に厚付けメッキを行うことにより可能となる。また、導電性ペーストをVIA用開口41に充填する方法でもよい。充填する材料として、熱伝導率の高いものが望ましい。例えば、銅(403W/m/K)、銀(428W/m/K)、アルミニウム(236W/m/K)などがあげられる。このとき、VIA用開口形状をできるだけ大面積にすると、より放熱性を向上できる。放熱性が向上することによって、発光素子への熱負荷が低減でき、安定な発光が得られる。
次に、発光素子1から透明結晶基板6を分離する方法を説明する。FIG.11A,11Bは、レーザ光照射による基板分離工程を示す。レーザ光L4を透明結晶基板6を透過して半導体層2の表面に照射すると、従来技術に関連して述べたように、半導体層2の表面の窒化物半導体、例えばGaN層がGaメタルとN2に分解して、FIG.11Bに示すように、透明結晶基板6が半導体層2、従って発光素子1から分離される。基板分離に用いられるレーザとしては、エキシマレーザ(XeCl,KrF,ArF,F2など)、THG−YAGレーザ(第3高調波レーザ)、FHG−YAGレーザ(第4高調波レーザ)などの紫外線レーザやパルス幅が1ps以下の超短パルスレーザ(Ti:サファイアレーザやその高調波レーザ、エキシマレーザなど)が挙げられる。
以下において、半導体表面(発光面)のいくつかの処理について説明する。FIG.12A、12Bはレーザ光による凹凸構造を形成を示す。レーザ光L5により透明結晶基板6を分離加工する際に、透明結晶基板6に面している窒化物半導体層2の表面に凹凸構造22を形成する。凹凸構造22の形成は、入射レーザ光と拡散反射レーザ光との干渉を利用したり、複数の光束を干渉させた加工などにより行うことが可能である。この凹凸構造22によって光を取り出す効率を向上できる。
次に、発光素子1の他の製造方法の例を、FIG.16を参照して説明する。この製造方法は、前述同様にVIA形成工程(A)を用いるものであり、半導体基板上に絶縁層4を形成した後、絶縁層にVIA用開口を形成する。ここでは、絶縁層4の材料として、上述の樹脂や銅箔付樹脂と異なり、セラミックスやシリコンを用いる場合について説明する。セラミックス又はシリコンの薄板を半導体基板の半導体層2,3及び半導体面電極21,31上に接合する。セラミックスとしてアルミナを用いることができる。これらは、接合面を清浄化及び活性化した状態で圧力をかけることにより接合することができる。
次に、発光素子1のさらに他の製造方法について、FIG.17A〜17Dを参照して説明する。この製造方法では、前出のFIG.3Cに示したVIA形成工程(B)を用いる。すなわち、FIG.17Aに示すように、半導体面電極21,31に面するVIA用開口41を予め形成した絶縁層4を、半導体基板の半導体層2,3及び半導体面電極21,31上に接合して積層する。
次に、発光素子1のさらに他の製造方法について、FIG.18A〜18Cを参照して説明する。この製造方法では、前出のFIG.7Aに示した方法と同様に絶縁層4にVIA用開口41を予め形成することに加え、絶縁層4に実装面電極5とVIA用開口41内面の導体51をも予め形成する。また、新たに、VIA電極52が、半導体面電極21,31に面する絶縁層4の面であってVIA用開口41の周囲に形成されている。このVIA電極52は、導体51と半導体面電極21,31とを確実に電気接続するために形成されている。以上まとめると、この絶縁層4は、VIA10及び実装面電極5が最終状態で備わっているものである。
2,3 半導体層
4 絶縁層
5 実装面電極
6 透明結晶基板
7 導体層
10 VIA
20 非積層部
21,31 半導体面電極
41 VIA用開口
L1〜L8 レーザ光
Claims (18)
- p型及びn型窒化物半導体層を積層して形成した発光素子において、
前記各半導体層に電流を注入するための半導体面電極と、
前記各半導体層を保持するための絶縁層と、
前記絶縁層の前記半導体層がある面とは反対側の面に設けた、発光素子をはんだで基板に実装するための実装面電極と、を備え、
一方の半導体層は他方の半導体層が積層していない非積層部を持ち、
前記一方の半導体層に積層された半導体面電極は前記非積層部に積層されており、
前記実装面電極と前記半導体面電極とを導通させるVIAが前記絶縁層に形成され、前記半導体面電極、絶縁層、及び実装面電極は、前記積層された半導体層の一方の面に順に積層され、
前記積層された半導体層の他方の面は光取出し面であって当該半導体層面には介在物がなく、その面の外形が前記絶縁層の外形と一致していることを特徴とする発光素子。 - 前記絶縁層は、樹脂、セラミックス、及びシリコンのいずれか1つからなることを特徴とする請求項1に記載の発光素子。
- 前記VIA内部を導電性材料により埋めていることを特徴とする請求項1に記載の発光素子。
- 前記半導体層の表面又は内部に蛍光体を配置していることを特徴とする請求項1に記載の発光素子。
- 発光素子の製造方法において、
透明結晶基板上にp型及びn型窒化物半導体層を積層し、前記透明基板側に設けられる前記半導体層の一部に他方の半導体層が積層していない非積層部を設け、これらの半導体層上に各半導体層に電流を注入するための半導体面電極をそれぞれの電極表面を同一方向に露出した状態で設けてなる半導体基板を形成する基板形成工程と、
前記形成された半導体基板の半導体面電極側の面に絶縁層を形成し、前記半導体面電極上の一部の絶縁層を除去してVIA用開口を設け、この除去により露出した半導体面電極上及び前記VIA用開口の内面に導体を設けてVIAを形成するとともに、このVIAを介して前記半導体面電極に電気接続される実装面電極であって発光素子をはんだで基板に実装するための実装面電極を前記絶縁層の前記半導体層がある面とは反対側の表面に形成するVIA形成工程と、
前記VIA形成工程の後に、前記透明結晶基板を前記半導体層から分離する基板分離工程と、
前記透明結晶基板を分離され平面的に配列して一括製造された発光素子集合体を切断することにより、前記透明結晶基板を分離された半導体層面の外形が前記絶縁層の外形と一致している単一素子又は所定個数の発光素子集合体とする工程と、を備えたことを特徴とする発光素子の製造方法。 - 前記VIA形成工程において形成される絶縁層は、樹脂、セラミックス、及びシリコンのいずれか1つからなることを特徴とする請求項5に記載の発光素子の製造方法。
- 前記VIA形成工程において形成される絶縁層は、絶縁層材料として銅箔付樹脂を用いて形成されることを特徴とする請求項5に記載の発光素子の製造方法。
- 前記VIA形成工程における半導体面電極上の樹脂の除去加工に際し、前記銅箔付樹脂における樹脂除去加工予定位置の銅箔を除去し、残った銅箔を樹脂の除去加工用マスクとして用いることを特徴とする請求項7に記載の発光素子の製造方法。
- 前記VIA形成工程における半導体面電極上の絶縁層の除去加工をレーザ光又はプラズマの照射により行うことを特徴とする請求項5に記載の発光素子の製造方法。
- 前記基板分離工程における透明結晶基板の分離にレーザ光を用いることを特徴とする請求項5に記載の発光素子の製造方法。
- 前記レーザ光による半導体層からの透明結晶基板の分離と同時に該半導体層表面の分離面に凹凸を形成することを特徴とする請求項10に記載の発光素子の製造方法。
- 前記半導体層表面の凹凸形成は、透明結晶基板を分離するための分離用レーザ光の照射と同時に凹凸形成用レーザ光を照射して行うことを特徴とする請求項11に記載の発光素子の製造方法。
- 発光素子の製造方法において、
透明結晶基板上にp型及びn型窒化物半導体層を積層し、前記透明基板側に設けられる前記半導体層の一部に他方の半導体層が積層していない非積層部を設け、これらの半導体層上に各半導体層に電流を注入するための半導体面電極をそれぞれの電極表面を同一方向に露出した状態で設けてなる半導体基板を形成する基板形成工程と、
前記半導体面電極に対応するVIA用開口を予め形成した絶縁層を前記形成された半導体基板の半導体面電極側の面に積層し、前記半導体面電極上及び前記VIA用開口内面に導体を設けてVIAを形成するとともに、このVIAを介して前記半導体面電極に電気接続される実装面電極であって発光素子をはんだで基板に実装するための実装面電極を前記絶縁層の前記半導体層がある面とは反対側の表面に形成するVIA形成工程と、
前記VIA形成工程の後に、前記透明結晶基板を前記半導体層から分離する基板分離工程と、
前記透明結晶基板を分離され平面的に配列して一括製造された発光素子集合体を切断することにより、前記透明結晶基板を分離された半導体層面の外形が前記絶縁層の外形と一致している単一素子又は所定個数の発光素子集合体とする工程と、を備えたことを特徴とする発光素子の製造方法。 - 前記VIA形成工程において積層される絶縁層は、樹脂、セラミックス、及びシリコンのいずれか1つからなることを特徴とする請求項13に記載の発光素子の製造方法。
- 前記絶縁層の開口の形成を絶縁層へのレーザ光又はプラズマの照射により行うことを特徴とする請求項13に記載の発光素子の製造方法。
- 前記基板分離工程における透明結晶基板の分離にレーザ光を用いることを特徴とする請求項13に記載の発光素子の製造方法。
- 前記レーザ光による半導体層からの透明結晶基板の分離と同時に該半導体層表面の分離面に凹凸を形成することを特徴とする請求項16に記載の発光素子の製造方法。
- 前記半導体層表面の凹凸形成は、透明結晶基板を分離するための分離用レーザ光の照射と同時に凹凸形成用レーザ光を照射して行うことを特徴とする請求項17に記載の発光素子の製造方法。
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JP6072192B2 (ja) * | 2015-10-22 | 2017-02-01 | 株式会社東芝 | 半導体発光装置、半導体発光装置の製造方法、発光装置の製造方法 |
JP7253489B2 (ja) | 2016-10-24 | 2023-04-06 | インブイティ・インコーポレイテッド | 照明要素 |
JP7430990B2 (ja) * | 2019-06-26 | 2024-02-14 | 新光電気工業株式会社 | 配線基板の製造方法 |
JP2021158303A (ja) * | 2020-03-30 | 2021-10-07 | 株式会社ディスコ | レーザー加工装置 |
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US5693963A (en) | 1994-09-19 | 1997-12-02 | Kabushiki Kaisha Toshiba | Compound semiconductor device with nitride |
EP0921577A4 (en) | 1997-01-31 | 2007-10-31 | Matsushita Electric Ind Co Ltd | ELECTROLUMINESCENT ELEMENT, SEMICONDUCTOR ELECTROLUMINESCENT DEVICE, AND PROCESS FOR PRODUCING THE SAME |
EP0924966A1 (en) * | 1997-06-30 | 1999-06-23 | Aventis Research & Technologies GmbH & Co. KG | Thin film electrode for planar organic light-emitting devices and method for its production |
JP3592553B2 (ja) | 1998-10-15 | 2004-11-24 | 株式会社東芝 | 窒化ガリウム系半導体装置 |
JP2000196197A (ja) * | 1998-12-30 | 2000-07-14 | Xerox Corp | 成長基板が除去された窒化物レ―ザダイオ―ドの構造及び窒化物レ―ザダイオ―ドアレイ構造の製造方法 |
US6744800B1 (en) | 1998-12-30 | 2004-06-01 | Xerox Corporation | Method and structure for nitride based laser diode arrays on an insulating substrate |
JP4362905B2 (ja) * | 1999-09-21 | 2009-11-11 | 富士ゼロックス株式会社 | 自己走査型発光装置、書き込み用光源および光プリンタ |
WO2001061804A1 (en) * | 2000-02-16 | 2001-08-23 | Nichia Corporation | Nitride semiconductor laser device |
US6878973B2 (en) * | 2001-08-23 | 2005-04-12 | Lumileds Lighting U.S., Llc | Reduction of contamination of light emitting devices |
KR20050044518A (ko) | 2001-11-19 | 2005-05-12 | 산요덴키가부시키가이샤 | 화합물 반도체 발광 소자 및 그 제조 방법 |
JP4055405B2 (ja) | 2001-12-03 | 2008-03-05 | ソニー株式会社 | 電子部品及びその製造方法 |
TW554553B (en) * | 2002-08-09 | 2003-09-21 | United Epitaxy Co Ltd | Sub-mount for high power light emitting diode |
TWI246783B (en) | 2003-09-24 | 2006-01-01 | Matsushita Electric Works Ltd | Light-emitting device and its manufacturing method |
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CN1830097A (zh) | 2006-09-06 |
EP1665400B1 (en) | 2009-05-06 |
KR20060032208A (ko) | 2006-04-14 |
TW200522393A (en) | 2005-07-01 |
JP2007503718A (ja) | 2007-02-22 |
KR100728693B1 (ko) | 2007-06-14 |
CN100446280C (zh) | 2008-12-24 |
US7956377B2 (en) | 2011-06-07 |
US20090186431A1 (en) | 2009-07-23 |
WO2005029599A2 (en) | 2005-03-31 |
US20060231853A1 (en) | 2006-10-19 |
TWI246783B (en) | 2006-01-01 |
WO2005029599A3 (en) | 2005-11-17 |
EP1665400A2 (en) | 2006-06-07 |
US7923270B2 (en) | 2011-04-12 |
ATE430993T1 (de) | 2009-05-15 |
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