JP4434754B2 - 電子デバイス及びその中間製品 - Google Patents
電子デバイス及びその中間製品 Download PDFInfo
- Publication number
- JP4434754B2 JP4434754B2 JP2004007346A JP2004007346A JP4434754B2 JP 4434754 B2 JP4434754 B2 JP 4434754B2 JP 2004007346 A JP2004007346 A JP 2004007346A JP 2004007346 A JP2004007346 A JP 2004007346A JP 4434754 B2 JP4434754 B2 JP 4434754B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- base
- electronic device
- circuit board
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09154—Bevelled, chamferred or tapered edge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
該積層型複合デバイスにおいては、図10に示す如く複数のセラミック層(61)を積層して積層型の基体(6)が構成されており、最上層のセラミック層(61)の表面には複数のチップ部品(7)が投搭載されると共に、中間層のセラミック層(61)の表面にはインダクターパターンやコンデンサパターン等の回路素子が形成され、これらの回路素子と複数のチップ部品(7)とが互いに接続されて、アンテナ共用回路が構成されている。
しかしながら、図7(a)に示す如く積層型複合デバイスを回路基板上に表面実装した場合、半田フィレット(30)が基体(6)の側面(60)から外側へ大きく突出することになるため、その分だけ実装面積Aが拡大する問題があった。
前記基体(1)は、複数のセラミック層を積層してなる積層セラミック基板によって形成され、或いは、合成樹脂若しくはセラミックからなる単層の基板によって形成されている。
本発明に係る電子デバイスは、図1に示す如く、基体(1)の表面に複数のチップ部品(7)を搭載して構成され、基体(1)の両端部にはそれぞれ、複数の外部電極(2)が配備されている。又、基体(1)の両端部にはそれぞれ、側面(10)と裏面(19)に交差する斜面(11)が形成され、該斜面(11)には、外部電極(2)の表面が露出しており(図5(c)参照)、回路基板上に表面実装された状態では、図1の如く斜面(11)に露出する外部電極(2)の表面を覆って、半田フィレット(3)が形成されている。
図2(a)(b)(c)の何れの場合においても、半田フィレット(3)は、基体(1)の斜面(11)と回路基板(9)の表面との間に挟まれた楔状空間に、略全体が収容されており、基体(1)の側面(10)から外側への突出量は零若しくは極く僅かである。
尚、基体基板(15)が複数のセラミック層を積層して形成されている場合、各セラミック層の表面には予めインダクターパターン等の電子回路要素(図示省略)が形成され、これらの電子回路要素がビアホール等(図示省略)によって互いに接続されている。
その後、基体基板(15)をV字状溝(16)の最も深い位置で切断することによって、図5(c)に示す如く、側面(10)に複数の外部電極(2)が配備された基体(1)が得られる。該基体(1)において、側面(10)には、V字状溝(16)の内面によって斜面(11)が形成され、該斜面(11)には、導体充填部(21)が2分割されて形成された外部電極(2)の表面が露出している。
該半田フィレット(3)は、基体(1)の斜面(11)と回路基板(9)の表面との間に形成された楔状空間に略全体が収容されている。
基体(1)の両端部にはそれぞれ、基体(1)の側面(10)と裏面(19)に交差する斜面(11)が形成され、該斜面(11)と回路基板(9)の表面との間に形成された楔状空間に、半田フィレット(3)の略全体が収容されている。
基体(1)の両端部にはそれぞれ、基体(1)の側面(10)と裏面(19)に交差する斜面(11)が形成され、該斜面(11)と回路基板(9)の表面との間に形成された楔状空間に、半田フィレット(3)の略全体が収容されている。
又、図6に示す基体基板(15)において、基体単位部(17)間の境界線の両側に複数の導体充填部(21)が2列に形成されると共に、該境界線に沿ってV字状溝(16)が凹設されている構成も採用可能であり、該基体基板(15)を基体単位部(17)間の境界線に沿って切断することにより、図8(a)に示す基体(1)が得られる。
(10) 側面
(11) 斜面
(15) 基体基板
(16) V字状溝
(17) 基体単位部
(19) 裏面
(2) 外部電極
(21) 導体充填部
(3) 半田フィレット
(7) チップ部品
(9) 回路基板
Claims (4)
- 回路基板上に表面実装されるべき基体を具えた電子デバイスであって、基体には、その表面及び/又は内部に1或いは複数の電子部品要素が搭載されると共に、前記1或いは複数の電子部品要素を前記回路基板に接続するための外部電極が、基体裏面に対して垂直な柱状に形成されて基体裏面に露出している電子デバイスにおいて、基体の端部には、基体の側面及び裏面と交差する斜面が形成され、該斜面と裏面と基体側面に前記電極が露出しており、前記電極露出面は、斜面と基体裏面との連結部から斜面と基体側面との連結部を越えて、基体側面と基体表面の連結部まで延在していることを特徴とする電子デバイス。
- 前記斜面は、平面、多角面、曲面、若しくはこれらの面の組み合わせから形成されている請求項1に記載の電子デバイス。
- 前記基体は、複数のセラミック層を積層してなる積層セラミック基板によって形成されている請求項1又は請求項2に記載の電子デバイス。
- 前記基体は、合成樹脂若しくはセラミックからなる単層の基板によって形成されている請求項1又は請求項2に記載の電子デバイス。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004007346A JP4434754B2 (ja) | 2004-01-14 | 2004-01-14 | 電子デバイス及びその中間製品 |
US11/030,288 US7218002B2 (en) | 2004-01-14 | 2005-01-07 | Electronic device and intermediate product of electronic device |
CNA2005100042081A CN1642406A (zh) | 2004-01-14 | 2005-01-14 | 电子器件及其中间制品 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004007346A JP4434754B2 (ja) | 2004-01-14 | 2004-01-14 | 電子デバイス及びその中間製品 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005203521A JP2005203521A (ja) | 2005-07-28 |
JP4434754B2 true JP4434754B2 (ja) | 2010-03-17 |
Family
ID=34737309
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004007346A Expired - Fee Related JP4434754B2 (ja) | 2004-01-14 | 2004-01-14 | 電子デバイス及びその中間製品 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7218002B2 (ja) |
JP (1) | JP4434754B2 (ja) |
CN (1) | CN1642406A (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4792726B2 (ja) * | 2003-10-30 | 2011-10-12 | 日亜化学工業株式会社 | 半導体素子用支持体の製造方法 |
EP2361000A1 (en) * | 2010-02-11 | 2011-08-24 | Nxp B.V. | Leadless chip package mounting method and carrier |
DE102016105581A1 (de) * | 2016-03-24 | 2017-09-28 | Infineon Technologies Ag | Umleiten von Lotmaterial zu einer visuell prüfbaren Packungsoberfläche |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2976049B2 (ja) | 1992-07-27 | 1999-11-10 | 株式会社村田製作所 | 積層電子部品 |
US6693358B2 (en) * | 2000-10-23 | 2004-02-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
JP3736387B2 (ja) | 2001-05-25 | 2006-01-18 | 株式会社村田製作所 | 複合電子部品及びその製造方法 |
-
2004
- 2004-01-14 JP JP2004007346A patent/JP4434754B2/ja not_active Expired - Fee Related
-
2005
- 2005-01-07 US US11/030,288 patent/US7218002B2/en not_active Expired - Fee Related
- 2005-01-14 CN CNA2005100042081A patent/CN1642406A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US20050151247A1 (en) | 2005-07-14 |
US7218002B2 (en) | 2007-05-15 |
CN1642406A (zh) | 2005-07-20 |
JP2005203521A (ja) | 2005-07-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7777314B2 (en) | Electronic component mounting package and package assembled substrate | |
JP5459445B2 (ja) | 電子部品 | |
KR101529900B1 (ko) | 전자부품 | |
US7362586B2 (en) | Electronic component with shielding case and method of manufacturing the same | |
JP6648689B2 (ja) | 積層型電子部品の製造方法および積層型電子部品 | |
JP4984912B2 (ja) | 高周波用チューナモジュール | |
US7660132B2 (en) | Covered multilayer module | |
JP2005072095A (ja) | 電子回路ユニットおよびその製造方法 | |
JP6648690B2 (ja) | 積層型電子部品の製造方法および積層型電子部品 | |
JP3736387B2 (ja) | 複合電子部品及びその製造方法 | |
JP4434754B2 (ja) | 電子デバイス及びその中間製品 | |
US6151775A (en) | Multilayer circuit board and method of producing the same | |
JP3855798B2 (ja) | 積層セラミック電子部品およびその製造方法 | |
JP6428764B2 (ja) | チップ型電子部品 | |
JP2014225504A (ja) | 樹脂多層基板の製造方法 | |
AU2002217176B2 (en) | A method for manufaacturing a crystal oscillator and a crystal oscillator | |
JP2004343072A (ja) | 多数個取り配線基板 | |
JP2007096097A (ja) | 電子部品素子及びその集合基板並びに電子部品素子の製造方法 | |
JP6321477B2 (ja) | 電子部品収納用パッケージ、パッケージ集合体および電子部品収納用パッケージの製造方法 | |
JP4457739B2 (ja) | 電子部品およびその製造方法 | |
US20050029008A1 (en) | Surface mounted electronic circuit module | |
JP2005166931A (ja) | 回路基板装置 | |
JP4140631B2 (ja) | 電子部品の製造方法 | |
JP5460002B2 (ja) | 多数個取り配線基板および配線基板ならびに電子装置 | |
KR101025448B1 (ko) | 칩 안테나 및 칩 안테나 고착 모듈 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060718 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20071221 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080108 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080220 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090903 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091030 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091125 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091222 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130108 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |