JP4427108B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP4427108B2
JP4427108B2 JP08106898A JP8106898A JP4427108B2 JP 4427108 B2 JP4427108 B2 JP 4427108B2 JP 08106898 A JP08106898 A JP 08106898A JP 8106898 A JP8106898 A JP 8106898A JP 4427108 B2 JP4427108 B2 JP 4427108B2
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JP
Japan
Prior art keywords
memory cell
cell array
region
layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP08106898A
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English (en)
Japanese (ja)
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JPH11284151A (ja
JPH11284151A5 (enExample
Inventor
誠一 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP08106898A priority Critical patent/JP4427108B2/ja
Priority to US09/271,209 priority patent/US6501127B2/en
Publication of JPH11284151A publication Critical patent/JPH11284151A/ja
Publication of JPH11284151A5 publication Critical patent/JPH11284151A5/ja
Application granted granted Critical
Publication of JP4427108B2 publication Critical patent/JP4427108B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Dram (AREA)
JP08106898A 1998-03-27 1998-03-27 半導体装置及びその製造方法 Expired - Fee Related JP4427108B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP08106898A JP4427108B2 (ja) 1998-03-27 1998-03-27 半導体装置及びその製造方法
US09/271,209 US6501127B2 (en) 1998-03-27 1999-03-17 Semiconductor device including a nonvolatile memory-cell array, and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP08106898A JP4427108B2 (ja) 1998-03-27 1998-03-27 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JPH11284151A JPH11284151A (ja) 1999-10-15
JPH11284151A5 JPH11284151A5 (enExample) 2005-02-24
JP4427108B2 true JP4427108B2 (ja) 2010-03-03

Family

ID=13736085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP08106898A Expired - Fee Related JP4427108B2 (ja) 1998-03-27 1998-03-27 半導体装置及びその製造方法

Country Status (2)

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US (1) US6501127B2 (enExample)
JP (1) JP4427108B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000311992A (ja) * 1999-04-26 2000-11-07 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
JP2002057212A (ja) * 2000-08-09 2002-02-22 Mitsubishi Electric Corp 半導体装置、及び半導体装置の製造方法
JP2001267437A (ja) * 2000-03-22 2001-09-28 Sony Corp 不揮発性半導体記憶装置およびその製造方法
JP2003188286A (ja) * 2001-12-14 2003-07-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100549591B1 (ko) * 2003-11-05 2006-02-08 매그나칩 반도체 유한회사 비휘발성 메모리 소자 및 그의 제조 방법
TWI285410B (en) * 2006-01-27 2007-08-11 Ind Tech Res Inst Interlayer interconnect of three-dimensional memory and method for manufacturing the same
US7601998B2 (en) * 2006-09-14 2009-10-13 Samsung Electronics Co., Ltd. Semiconductor memory device having metallization comprising select lines, bit lines and word lines
JP2009021319A (ja) * 2007-07-11 2009-01-29 Panasonic Corp 不揮発性半導体記憶装置及びその製造方法
JP2008113017A (ja) * 2007-12-03 2008-05-15 Toshiba Corp 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60145641A (ja) 1984-01-10 1985-08-01 Toshiba Corp 半導体集積回路装置
JP2504599B2 (ja) * 1990-02-23 1996-06-05 株式会社東芝 不揮発性半導体記憶装置
US5705415A (en) * 1994-10-04 1998-01-06 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
US5814850A (en) * 1995-08-22 1998-09-29 Nippon Steel Corporation Semiconductor device including a capacitor responsible for a power supply voltage to semiconductor device and capable of blocking an increased voltage
JP3853406B2 (ja) 1995-10-27 2006-12-06 エルピーダメモリ株式会社 半導体集積回路装置及び当該装置の製造方法
JPH10135425A (ja) * 1996-11-05 1998-05-22 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH10189579A (ja) 1996-12-27 1998-07-21 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH11284151A (ja) 1999-10-15
US6501127B2 (en) 2002-12-31
US20020050612A1 (en) 2002-05-02

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