JP4420030B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4420030B2 JP4420030B2 JP2007016424A JP2007016424A JP4420030B2 JP 4420030 B2 JP4420030 B2 JP 4420030B2 JP 2007016424 A JP2007016424 A JP 2007016424A JP 2007016424 A JP2007016424 A JP 2007016424A JP 4420030 B2 JP4420030 B2 JP 4420030B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- semiconductor
- region
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 146
- 238000004519 manufacturing process Methods 0.000 title claims description 47
- 239000000758 substrate Substances 0.000 claims description 79
- 238000000034 method Methods 0.000 claims description 62
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 51
- 238000005530 etching Methods 0.000 claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000007772 electrode material Substances 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 164
- 229910004298 SiO 2 Inorganic materials 0.000 description 34
- 229910052581 Si3N4 Inorganic materials 0.000 description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 32
- KRHYYFGTRYWZRS-UHFFFAOYSA-N hydrofluoric acid Substances F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76289—Lateral isolation by air gap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Description
T.Sakai et al."Separation by BondingSi Islands(SBSI) for LSI Application",Second International SiGe Technology and Device Meeting,Meeting Abstract,pp.230−231,May(2004)
そこで、この発明はこのような事情に鑑みてなされたものであって、バックゲート電極を有するSOI構造と、通常のSOI構造とを同一の半導体基板にセルフアラインでかつ通常の半導体プロセスで形成可能な半導体装置の製造方法の提供を目的とする。
発明6の半導体装置の製造方法は、発明1から発明5の何れか一の半導体装置の製造方法において、前記電極材料は、不純物を含むポリシリコン(poly−Si)であることを特徴とするものである。
発明8の半導体装置の製造方法は、発明1から発明7の何れか一の半導体装置の製造方法において、前記電極材料をCVD法で形成することを特徴とするものである。
図1(a)〜図18(a)は、本発明の実施の形態に係る半導体装置の製造方法を示す平面図、図1(b)〜図18(b)は、図1(a)〜図18(a)をA1−A´1〜A18−A´18線でそれぞれ切断したときの断面図、図1(c)〜図18(c)は、図1(a)〜図18(a)をB1−B´1〜B18−B´18線でそれぞれ切断したときの断面図、図1(d)〜図18(d)は、図1(a)〜図18(a)をC1−C´1〜C18−C´18線でそれぞれ切断したときの断面図である。なお、図18(a)では、図面の複雑化を回避するために層間絶縁膜の記入を省略している。
次に、図8(a)〜(d)に示すように、SiGe層13上に単結晶のSi層15を積層する。Si層15は例えば(全面)エピタキシャル成長法で形成する。そして、Si層15を熱酸化してその表面にSiO2膜17を形成する。さらに、CVD法により、SiO2膜17上の全面にSiN膜19を形成する。このSiN膜19は、Si層15の酸化を防止するための酸化防止膜として機能すると共に、後の工程でCMP(化学的機械研磨)を行う際のストッパー層としても機能する。なお、SiO2膜17の形成方法は熱酸化に限られることはなく、例えばCVD法で形成しても良い。
次に、Si基板1を希フッ酸(HF)溶液で洗浄処理する。そして、Si基板1を酸素(O2)等の酸化雰囲気中に配置して熱処理を施す。これにより、図13(a)〜(d)に示すように、Si層15及びSi基板1の各表面においてSiの表面酸化をそれぞれ進行させ、SiO2膜25を形成する。
即ち、従来の方法では困難であったバックゲート電極を有するSOI素子とバックゲート電極を有さない通常のSOI素子とを同一基板上にセルフアラインで、かつ、通常の半導体プロセスで形成することが可能となる。
Claims (8)
- 半導体基板の第1の領域の上に第1の厚みの第1半導体層を形成し、前記半導体基板の第2の領域の上に前記第1半導体層と材質が同じで前記第1の厚みより薄い第2半導体層を形成する工程と、
前記第1半導体層及び前記第2半導体層の上に第3半導体層を形成する工程と、
前記第3半導体層及び前記第1半導体層とを貫く第1溝と、前記第3半導体層及び前記第2半導体層とを貫く第2溝と、を形成する工程と、
前記第3半導体層を支持する支持体を前記第1溝及び前記第2溝の内部に形成する工程と、
前記第1半導体層の側面を露出させる第3溝と、前記第2半導体層の側面を露出させる第4溝と、を形成する工程と、
前記第1半導体層及び前記第2半導体層を除去して前記第3半導体層と前記半導体基板の第1の領域の間に第1の高さを持つ第1空洞部を形成し、さらに前記第3半導体層と前記半導体基板の第2の領域の間に前記第1の高さより低い第2の高さを持つ第2空洞部を形成する工程と、
前記第1空洞部の内部及び前記第2空洞部の内部にそれぞれ絶縁層を形成することにより、前記第1空洞部の内部に前記絶縁層と第3空洞部を形成し、前記第2空洞部を前記絶縁層で埋め込む工程と、
前記第3空洞部に電極材料を埋め込む工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記第3溝は前記第1溝と平面視で交差する方向に延び、前記第4溝は前記第2溝と平面視で交差する方向に延びることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1半導体層及び前記第2半導体層を形成する工程は、
前記半導体基板の前記第1の領域をエッチングして凹部を形成する工程と、
前記第1の領域だけに半導体層Aを形成して前記凹部を埋め込む工程と、
前記半導体層A上及び前記半導体基板の前記第2の領域上にそれぞれ半導体層Bを形成する工程と、を含み、
前記第1半導体層は前記半導体層A及び前記半導体層Bからなり、
前記第2半導体層は前記半導体層Bからなることを特徴とする請求項1又は請求項2に記載の半導体装置の製造方法。 - 前記絶縁層を形成する工程では、
前記第1空洞部に面した前記半導体基板の前記第1の領域の上面及び前記第1空洞部に面した前記第3半導体層の下面と、前記第2空洞部に面した前記半導体基板の前記第2の領域の上面及び前記第2空洞部に面した前記第3半導体層の下面と、をそれぞれ熱酸化することによって、前記絶縁層を形成することを特徴とする請求項1から請求項3の何れか一項に記載の半導体装置の製造方法。 - 前記第1半導体層及び前記第2半導体層はそれぞれシリコンゲルマニウム(SiGe)であり、前記第3半導体層はシリコン(Si)であることを特徴とする請求項1から請求項4の何れか一項に記載の半導体装置の製造方法。
- 前記電極材料は、不純物を含むポリシリコン(poly−Si)であることを特徴とする請求項1から請求項5の何れか一項に記載の半導体装置の製造方法。
- 前記電極材料は、金属、又は金属シリサイド又は金属の窒化物であることを特徴とする請求項1から請求項5の何れか一項に記載の半導体装置の製造方法。
- 前記電極材料をCVD法で形成することを特徴とする請求項1から請求項7の何れか一項に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007016424A JP4420030B2 (ja) | 2007-01-26 | 2007-01-26 | 半導体装置の製造方法 |
US11/970,583 US20080182380A1 (en) | 2007-01-26 | 2008-01-08 | Method for manufacturing semiconductor device |
KR1020080007993A KR20080070584A (ko) | 2007-01-26 | 2008-01-25 | 반도체 장치의 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007016424A JP4420030B2 (ja) | 2007-01-26 | 2007-01-26 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008186827A JP2008186827A (ja) | 2008-08-14 |
JP4420030B2 true JP4420030B2 (ja) | 2010-02-24 |
Family
ID=39668462
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007016424A Expired - Fee Related JP4420030B2 (ja) | 2007-01-26 | 2007-01-26 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20080182380A1 (ja) |
JP (1) | JP4420030B2 (ja) |
KR (1) | KR20080070584A (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100555569B1 (ko) | 2004-08-06 | 2006-03-03 | 삼성전자주식회사 | 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법 |
JP4455618B2 (ja) | 2007-06-26 | 2010-04-21 | 株式会社東芝 | 半導体装置の製造方法 |
EP2599111B1 (en) * | 2010-07-27 | 2015-09-23 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Transistor with counter-electrode connection with the source/drain contact |
CN102456737B (zh) * | 2010-10-27 | 2016-03-30 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
US8492210B2 (en) | 2010-12-17 | 2013-07-23 | Institute of Microelectronics, Chinese Academy of Sciences | Transistor, semiconductor device comprising the transistor and method for manufacturing the same |
CN102569393B (zh) * | 2010-12-17 | 2015-01-14 | 中国科学院微电子研究所 | 晶体管、包括该晶体管的半导体器件及其制造方法 |
CN102867750B (zh) * | 2011-07-07 | 2015-03-25 | 中国科学院微电子研究所 | Mosfet及其制造方法 |
CN102983140B (zh) * | 2011-09-07 | 2015-07-01 | 中国科学院微电子研究所 | 半导体结构及其制造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070126034A1 (en) * | 2003-10-10 | 2007-06-07 | Tokyo Institute Of Technology | Semiconductor substrate, semiconductor device and process for producing semiconductor substrate |
US7034362B2 (en) * | 2003-10-17 | 2006-04-25 | International Business Machines Corporation | Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures |
JP4306724B2 (ja) * | 2006-12-19 | 2009-08-05 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US7575968B2 (en) * | 2007-04-30 | 2009-08-18 | Freescale Semiconductor, Inc. | Inverse slope isolation and dual surface orientation integration |
US7749829B2 (en) * | 2007-05-01 | 2010-07-06 | Freescale Semiconductor, Inc. | Step height reduction between SOI and EPI for DSO and BOS integration |
US7790528B2 (en) * | 2007-05-01 | 2010-09-07 | Freescale Semiconductor, Inc. | Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation |
-
2007
- 2007-01-26 JP JP2007016424A patent/JP4420030B2/ja not_active Expired - Fee Related
-
2008
- 2008-01-08 US US11/970,583 patent/US20080182380A1/en not_active Abandoned
- 2008-01-25 KR KR1020080007993A patent/KR20080070584A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
KR20080070584A (ko) | 2008-07-30 |
JP2008186827A (ja) | 2008-08-14 |
US20080182380A1 (en) | 2008-07-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3762136B2 (ja) | 半導体装置 | |
JP3575596B2 (ja) | ダブルゲート集積回路を作製する方法及びダブルゲート金属酸化物半導体トランジスタを作製する方法 | |
JP4420030B2 (ja) | 半導体装置の製造方法 | |
JP4202563B2 (ja) | 半導体装置 | |
KR100273615B1 (ko) | 반도체장치및그제조방법 | |
KR100611076B1 (ko) | 스택형 반도체 장치 및 그 제조 방법 | |
JPH1131743A (ja) | 半導体装置及びその製造方法 | |
US9099570B2 (en) | Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices | |
JP4360413B2 (ja) | 半導体装置の製造方法 | |
JP4031677B2 (ja) | 半導体装置の製造方法 | |
JP2008244229A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP2005167258A (ja) | 半導体装置およびその製造方法 | |
JP4036341B2 (ja) | 半導体装置及びその製造方法 | |
JP4434832B2 (ja) | 半導体装置、及びその製造方法 | |
JP2005322830A (ja) | 半導体装置の製造方法 | |
JP2009176856A (ja) | 半導体装置の製造方法 | |
KR100876830B1 (ko) | 반도체소자의 형성방법 | |
JP4696518B2 (ja) | 半導体基板の製造方法および半導体装置の製造方法 | |
US7488666B2 (en) | Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device | |
JP4942951B2 (ja) | Mos型トランジスタの製造方法及びmos型トランジスタ | |
JP2006041331A (ja) | 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法 | |
JP2009252814A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP2007266390A (ja) | 半導体装置の製造方法 | |
JP2006066573A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2004247328A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090220 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090310 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090511 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20091110 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091123 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121211 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121211 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131211 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |