JP4401023B2 - 遠紫外線フォトレジストを用いたディープサブミクロンメタライゼーション - Google Patents

遠紫外線フォトレジストを用いたディープサブミクロンメタライゼーション Download PDF

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Publication number
JP4401023B2
JP4401023B2 JP2000545191A JP2000545191A JP4401023B2 JP 4401023 B2 JP4401023 B2 JP 4401023B2 JP 2000545191 A JP2000545191 A JP 2000545191A JP 2000545191 A JP2000545191 A JP 2000545191A JP 4401023 B2 JP4401023 B2 JP 4401023B2
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Japan
Prior art keywords
layer
silicon oxynitride
deep
metallization layer
dielectric layer
Prior art date
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Expired - Fee Related
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JP2000545191A
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English (en)
Japanese (ja)
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JP2002512449A5 (enExample
JP2002512449A (ja
Inventor
リオンズ，クリストファー・エフ
スィン，バーンウォー
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2002512449A5 publication Critical patent/JP2002512449A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/952—Utilizing antireflective layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
JP2000545191A 1998-04-23 1999-04-01 遠紫外線フォトレジストを用いたディープサブミクロンメタライゼーション Expired - Fee Related JP4401023B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/065,352 US6287959B1 (en) 1998-04-23 1998-04-23 Deep submicron metallization using deep UV photoresist
US09/065,352 1998-04-23
PCT/US1999/007361 WO1999054930A1 (en) 1998-04-23 1999-04-01 Deep submicron metallization using deep uv photoresist

Publications (3)

Publication Number Publication Date
JP2002512449A JP2002512449A (ja) 2002-04-23
JP2002512449A5 JP2002512449A5 (enExample) 2006-04-27
JP4401023B2 true JP4401023B2 (ja) 2010-01-20

Family

ID=22062123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000545191A Expired - Fee Related JP4401023B2 (ja) 1998-04-23 1999-04-01 遠紫外線フォトレジストを用いたディープサブミクロンメタライゼーション

Country Status (5)

Country Link
US (1) US6287959B1 (enExample)
EP (1) EP1080494A1 (enExample)
JP (1) JP4401023B2 (enExample)
KR (1) KR100562540B1 (enExample)
WO (1) WO1999054930A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331379B1 (en) * 1999-09-01 2001-12-18 Micron Technology, Inc. Photo-lithography process using multiple anti-reflective coatings
DE10000004A1 (de) * 2000-01-03 2001-05-17 Infineon Technologies Ag Verfahren zur Herstellung von Leitbahnen
US20020197835A1 (en) * 2001-06-06 2002-12-26 Sey-Ping Sun Anti-reflective coating and methods of making the same
JP2003124189A (ja) * 2001-10-10 2003-04-25 Fujitsu Ltd 半導体装置の製造方法
US6613665B1 (en) * 2001-10-26 2003-09-02 Lsi Logic Corporation Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface
JP2003209046A (ja) * 2002-01-16 2003-07-25 Mitsubishi Electric Corp レジストパターン形成方法および半導体装置の製造方法
KR100506943B1 (ko) * 2003-09-09 2005-08-05 삼성전자주식회사 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들
US7611758B2 (en) * 2003-11-06 2009-11-03 Tokyo Electron Limited Method of improving post-develop photoresist profile on a deposited dielectric film
US7101787B1 (en) 2004-04-09 2006-09-05 National Semiconductor Corporation System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition
US10236398B2 (en) 2015-07-06 2019-03-19 Electronics And Telecommunications Research Institute Method for manufacturing transparent electrode
US20170064821A1 (en) * 2015-08-31 2017-03-02 Kristof Darmawikarta Electronic package and method forming an electrical package
US10964653B2 (en) * 2017-09-28 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a semiconductor device comprising top conductive pads

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6010644A (ja) 1983-06-30 1985-01-19 Toshiba Corp 半導体装置の製造方法
JPH05190796A (ja) 1991-07-30 1993-07-30 Internatl Business Mach Corp <Ibm> ダイナミック・ランダム・アクセス・メモリ・セル用誘電体皮膜およびその形成方法
KR960005761A (ko) 1994-07-27 1996-02-23 이데이 노부유끼 반도체장치
US6577007B1 (en) 1996-02-01 2003-06-10 Advanced Micro Devices, Inc. Manufacturing process for borderless vias with respect to underlying metal
US5858870A (en) 1996-12-16 1999-01-12 Chartered Semiconductor Manufacturing, Ltd. Methods for gap fill and planarization of intermetal dielectrics

Also Published As

Publication number Publication date
WO1999054930A1 (en) 1999-10-28
US6287959B1 (en) 2001-09-11
KR100562540B1 (ko) 2006-03-22
KR20010042954A (ko) 2001-05-25
EP1080494A1 (en) 2001-03-07
JP2002512449A (ja) 2002-04-23

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