JP4330670B2 - 不揮発性半導体記憶装置 - Google Patents

不揮発性半導体記憶装置 Download PDF

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Publication number
JP4330670B2
JP4330670B2 JP11341398A JP11341398A JP4330670B2 JP 4330670 B2 JP4330670 B2 JP 4330670B2 JP 11341398 A JP11341398 A JP 11341398A JP 11341398 A JP11341398 A JP 11341398A JP 4330670 B2 JP4330670 B2 JP 4330670B2
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JP
Japan
Prior art keywords
memory cell
writing
cell transistor
potential
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11341398A
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English (en)
Japanese (ja)
Other versions
JPH1154732A5 (enExample
JPH1154732A (ja
Inventor
徹 丸山
理一郎 白田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11341398A priority Critical patent/JP4330670B2/ja
Priority to US09/090,625 priority patent/US6034894A/en
Publication of JPH1154732A publication Critical patent/JPH1154732A/ja
Priority to US09/503,459 priority patent/US6222769B1/en
Publication of JPH1154732A5 publication Critical patent/JPH1154732A5/ja
Application granted granted Critical
Publication of JP4330670B2 publication Critical patent/JP4330670B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP11341398A 1997-06-06 1998-04-23 不揮発性半導体記憶装置 Expired - Fee Related JP4330670B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP11341398A JP4330670B2 (ja) 1997-06-06 1998-04-23 不揮発性半導体記憶装置
US09/090,625 US6034894A (en) 1997-06-06 1998-06-04 Nonvolatile semiconductor storage device having buried electrode within shallow trench
US09/503,459 US6222769B1 (en) 1997-06-06 2000-02-14 Nonvolatile semiconductor storage device having buried electrode within shallow trench

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP14968197 1997-06-06
JP9-149681 1997-06-06
JP11341398A JP4330670B2 (ja) 1997-06-06 1998-04-23 不揮発性半導体記憶装置

Publications (3)

Publication Number Publication Date
JPH1154732A JPH1154732A (ja) 1999-02-26
JPH1154732A5 JPH1154732A5 (enExample) 2005-09-29
JP4330670B2 true JP4330670B2 (ja) 2009-09-16

Family

ID=26452399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11341398A Expired - Fee Related JP4330670B2 (ja) 1997-06-06 1998-04-23 不揮発性半導体記憶装置

Country Status (2)

Country Link
US (1) US6034894A (enExample)
JP (1) JP4330670B2 (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147377A (en) * 1998-03-30 2000-11-14 Advanced Micro Devices, Inc. Fully recessed semiconductor device
FI981301A0 (fi) * 1998-06-08 1998-06-08 Valtion Teknillinen Prosessivaihtelujen eliminointimenetelmä u-MOSFET-rakenteissa
US6091104A (en) 1999-03-24 2000-07-18 Chen; Chiou-Feng Flash memory cell with self-aligned gates and fabrication process
US6281050B1 (en) * 1999-03-15 2001-08-28 Kabushiki Kaisha Toshiba Manufacturing method of a semiconductor device and a nonvolatile semiconductor storage device
US6901006B1 (en) * 1999-07-14 2005-05-31 Hitachi, Ltd. Semiconductor integrated circuit device including first, second and third gates
US6222227B1 (en) * 1999-08-09 2001-04-24 Actrans System Inc. Memory cell with self-aligned floating gate and separate select gate, and fabrication process
US6461915B1 (en) * 1999-09-01 2002-10-08 Micron Technology, Inc. Method and structure for an improved floating gate memory cell
JP3971873B2 (ja) * 1999-09-10 2007-09-05 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
KR20010036336A (ko) * 1999-10-07 2001-05-07 한신혁 반도체 디바이스의 메모리 셀 제조 방법
GB9928285D0 (en) * 1999-11-30 2000-01-26 Koninkl Philips Electronics Nv Manufacture of trench-gate semiconductor devices
US6426896B1 (en) 2000-05-22 2002-07-30 Actrans System Inc. Flash memory cell with contactless bit line, and process of fabrication
US6887753B2 (en) * 2001-02-28 2005-05-03 Micron Technology, Inc. Methods of forming semiconductor circuitry, and semiconductor circuit constructions
US6762092B2 (en) * 2001-08-08 2004-07-13 Sandisk Corporation Scalable self-aligned dual floating gate memory cell array and methods of forming the array
US6551881B1 (en) * 2001-10-01 2003-04-22 Koninklijke Philips Electronics N.V. Self-aligned dual-oxide umosfet device and a method of fabricating same
US6664191B1 (en) 2001-10-09 2003-12-16 Advanced Micro Devices, Inc. Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space
JP4027656B2 (ja) 2001-12-10 2007-12-26 シャープ株式会社 不揮発性半導体記憶装置及びその動作方法
US6894930B2 (en) * 2002-06-19 2005-05-17 Sandisk Corporation Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND
US6885586B2 (en) * 2002-09-19 2005-04-26 Actrans System Inc. Self-aligned split-gate NAND flash memory and fabrication process
JP2004241558A (ja) 2003-02-05 2004-08-26 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法、半導体集積回路及び不揮発性半導体記憶装置システム
DE10321742A1 (de) * 2003-05-14 2004-12-09 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Isoliergraben und Feldeffekttransistor sowie Herstellungsverfahren
JP3854247B2 (ja) * 2003-05-30 2006-12-06 株式会社東芝 不揮発性半導体記憶装置
DE10324612B4 (de) * 2003-05-30 2005-08-11 Infineon Technologies Ag Halbleiterspeicher mit Charge-Trapping-Speicherzellen und Virtual-Ground-Architektur
KR100598108B1 (ko) 2004-09-23 2006-07-07 삼성전자주식회사 측벽 트랜지스터를 가지는 비휘발성 메모리 소자 및 그제조방법
TWI246749B (en) * 2005-03-08 2006-01-01 Powerchip Semiconductor Corp Method of fabricating a non-volatile memory
US7750384B2 (en) * 2005-06-29 2010-07-06 Hynix Semiconductor Inc. Flash memory device having intergated plug
KR100680455B1 (ko) * 2005-06-30 2007-02-08 주식회사 하이닉스반도체 Ｎａｎｄ형 플래쉬 메모리 소자, 그 제조 방법 및 그 구동방법
JP2009059931A (ja) * 2007-08-31 2009-03-19 Toshiba Corp 不揮発性半導体記憶装置
JP4818241B2 (ja) * 2007-10-22 2011-11-16 株式会社東芝 不揮発性半導体記憶装置
US7788550B2 (en) * 2007-12-17 2010-08-31 Atmel Rousset S.A.S. Redundant bit patterns for column defects coding
KR101001257B1 (ko) 2008-10-06 2010-12-14 주식회사 동부하이텍 이이피롬 및 그의 제조방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4979004A (en) * 1988-01-29 1990-12-18 Texas Instruments Incorporated Floating gate memory cell and device
JP3238576B2 (ja) * 1994-08-19 2001-12-17 株式会社東芝 不揮発性半導体記憶装置
JPH08316348A (ja) * 1995-03-14 1996-11-29 Toshiba Corp 半導体装置およびその製造方法
KR100253868B1 (ko) * 1995-11-13 2000-05-01 니시무로 타이죠 불휘발성 반도체기억장치

Also Published As

Publication number Publication date
US6034894A (en) 2000-03-07
JPH1154732A (ja) 1999-02-26

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