JP4324642B2 - 中間値発生器基準を有するmram - Google Patents
中間値発生器基準を有するmram Download PDFInfo
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- JP4324642B2 JP4324642B2 JP2003522938A JP2003522938A JP4324642B2 JP 4324642 B2 JP4324642 B2 JP 4324642B2 JP 2003522938 A JP2003522938 A JP 2003522938A JP 2003522938 A JP2003522938 A JP 2003522938A JP 4324642 B2 JP4324642 B2 JP 4324642B2
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- bit line
- intermediate value
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- 230000015654 memory Effects 0.000 claims description 37
- 230000000694 effects Effects 0.000 description 31
- 238000010586 diagram Methods 0.000 description 16
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000005415 magnetization Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Semiconductor Memories (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
- Permanent Magnet Type Synchronous Machine (AREA)
Description
め、この作業は、CMOS回路のばらつきや、基準バイアス発生器のMTJが対象列及び基準列のMTJを厳密に追跡できないことによる影響を受ける。
Rmid=ΔR/2+Rmin(1)
ここで、ΔR=Rmax−Rminである。
Rmid=(Rmax+Rmin)||(Rmax+Rmin)=RAB
ここで、RABは、入力端子71と出力端子72との間の総抵抗である。
=(Rmax+Rmin)/2
=(ΔR+Rmin+Rmin)/2
RAB=ΔR/2+Rmin(2)
式(2)は、式(1)と等しく、即ち、RABは、Rmidに等しく、従って、発生器70は、中間値Rmidを正常に生成することが分かる。
の磁気抵抗効果素子67と接地線GLとの間に接続された第2制御トランジスタ69は、WL1が論理「0」であるため、オフのままである。基準ビット線60を流れる基準電流(Iref)は、中間値発生器セル58において分流し、その電流の半分が、磁気抵抗効果素子66及び67を流れ、他の半分が磁気抵抗効果素子64及び65を流れる。磁気抵抗効果素子65と67とは直接接続されており、磁気抵抗効果素子66及び67を流れる前記半分の電流は、この直接接続部を介して制御トランジスタ68の上流端子に流れ、ここで、磁気抵抗効果素子64及び65を流れる前記半分の電流と合流する。こうして、全基準電流(Iref)が、制御トランジスタ68を介して接地線GLに流れる。論理「1」にして、他方のメモリセル(磁気抵抗効果素子45及び制御トランジスタ49)に記憶された情報を読出す場合、同じ電流が流れる(但し、直接接続を介して反対方向に流れる)ことが分かる。従って、基準電流(Iref)が、中間値発生器セル58を流れて、あらゆる種類の検出増幅器用の基準電圧として機能する中間値電圧Vdatarefを生成し、例えば、電流コンベア55に用いてVrefを生成する。
に開示されている。
。この構造では、セグメント選択トランジスタが省略されているため、メモリ領域及びセグメント選択トランジスタを介した遅延の無駄が省かれる。しかしながら、全ての制御又は絶縁トランジスタの接合容量が加算され、その結果、ある程度、速度が低下する。
アレイ200の各直列セグメントの各データセルは、グローバルビット線及びデジィット線DL0乃至DL3によって個々にアドレス指定し得ることに留意されたい。各中間値発生器セル208では、磁気抵抗効果素子220及び221が、Rmax状態にプログラムされ、磁気抵抗効果素子222及び223が、Rmin状態にプログラムされる(即ち、状態保持される)。その結果、端子AとBとの間の抵抗は、RAB=ΔR/2+Rminである。
Claims (2)
- 磁気抵抗ランダムアクセスメモリ構造であって、
メモリビット線(42)と、
第1のワード選択線と、
第2のワード選択線と、
接地基準線(GL)と、
基準ビット線(60)と、
情報を記憶するために接続したメモリセルの少なくとも1つのデータ列(40)であって、
Rmax状態とRmin状態の内の一方にプログラム可能な第1の不揮発性磁気抵抗効果素子(44)と、
前記メモリビット線(42)と前記接地基準線(GL)との間に前記第1の不揮発性磁気抵抗効果素子と直列に接続され、かつ前記第1のワード選択線に接続されたゲートを有する第1の作動トランジスタ(48)と、
Rmax状態とRmin状態の内の一方にプログラム可能な第2の不揮発性磁気抵抗効果素子(45)と、
前記メモリビット線(42)と前記接地基準線(GL)との間に前記第2の不揮発性磁気抵抗効果素子と直列に接続され、かつ前記第2のワード選択線に接続されたゲートを有する第2の作動トランジスタ(49)とを含むメモリセルを含む前記少なくとも1つのデータ列(40)と、
少なくとも1つの中間値発生器セル(58、59)を含む少なくとも1つの基準列(41)であって、
前記基準ビット線(60)に接続された第3の不揮発性磁気抵抗効果素子(64)と、
前記第3の不揮発性磁気抵抗効果素子(64)とノードとの間に接続された第4の不揮発性磁気抵抗効果素子(65)と、
前記ノードと前記接地基準線との間に接続され、かつ前記第1のワード選択線に接続されたゲートを有する第3の作動トランジスタ(68)と、
前記基準ビット線(60)に接続された第5の不揮発性磁気抵抗効果素子(66)と、
前記第5の不揮発性磁気抵抗効果素子(66)と前記ノードとの間に接続された第6の不揮発性磁気抵抗効果素子(67)と、
前記ノードと前記接地基準線との間に接続され、かつ前記第2のワード選択線に接続されたゲートを有する第4の作動トランジスタ(69)とを含む中間値発生器セルを含む前記少なくとも1つの基準列(41)と
を備える磁気抵抗ランダムアクセスメモリ構造。 - 請求項1に記載の磁気抵抗ランダムアクセスメモリ構造であって、更に、
前記メモリビット線から生成したデータ電圧を前記中間値発生器セルから生成した基準電圧と差異比較してデータ出力信号を供給するために前記メモリビット線と前記基準ビット線とに接続された差動読出し回路を含む構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/940,320 US6445612B1 (en) | 2001-08-27 | 2001-08-27 | MRAM with midpoint generator reference and method for readout |
PCT/US2002/024629 WO2003019567A1 (en) | 2001-08-27 | 2002-08-02 | Mram with midpoint generator reference |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005501370A JP2005501370A (ja) | 2005-01-13 |
JP4324642B2 true JP4324642B2 (ja) | 2009-09-02 |
Family
ID=25474624
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003522938A Expired - Lifetime JP4324642B2 (ja) | 2001-08-27 | 2002-08-02 | 中間値発生器基準を有するmram |
Country Status (9)
Country | Link |
---|---|
US (1) | US6445612B1 (ja) |
EP (1) | EP1423855B1 (ja) |
JP (1) | JP4324642B2 (ja) |
KR (1) | KR100884497B1 (ja) |
CN (1) | CN100403445C (ja) |
AT (1) | ATE326756T1 (ja) |
DE (1) | DE60211531T2 (ja) |
TW (1) | TWI268508B (ja) |
WO (1) | WO2003019567A1 (ja) |
Families Citing this family (58)
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-
2001
- 2001-08-27 US US09/940,320 patent/US6445612B1/en not_active Expired - Lifetime
-
2002
- 2002-08-02 EP EP02756923A patent/EP1423855B1/en not_active Expired - Lifetime
- 2002-08-02 CN CNB028169239A patent/CN100403445C/zh not_active Expired - Fee Related
- 2002-08-02 AT AT02756923T patent/ATE326756T1/de not_active IP Right Cessation
- 2002-08-02 WO PCT/US2002/024629 patent/WO2003019567A1/en active IP Right Grant
- 2002-08-02 DE DE60211531T patent/DE60211531T2/de not_active Expired - Fee Related
- 2002-08-02 KR KR1020047002917A patent/KR100884497B1/ko not_active IP Right Cessation
- 2002-08-02 JP JP2003522938A patent/JP4324642B2/ja not_active Expired - Lifetime
- 2002-08-15 TW TW091118403A patent/TWI268508B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TWI268508B (en) | 2006-12-11 |
EP1423855B1 (en) | 2006-05-17 |
DE60211531T2 (de) | 2006-09-07 |
KR20040029083A (ko) | 2004-04-03 |
EP1423855A1 (en) | 2004-06-02 |
JP2005501370A (ja) | 2005-01-13 |
DE60211531D1 (de) | 2006-06-22 |
CN1550017A (zh) | 2004-11-24 |
CN100403445C (zh) | 2008-07-16 |
WO2003019567A1 (en) | 2003-03-06 |
ATE326756T1 (de) | 2006-06-15 |
US6445612B1 (en) | 2002-09-03 |
KR100884497B1 (ko) | 2009-02-18 |
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