JP4244003B2 - 素子チップの実装方法 - Google Patents
素子チップの実装方法 Download PDFInfo
- Publication number
- JP4244003B2 JP4244003B2 JP2003356265A JP2003356265A JP4244003B2 JP 4244003 B2 JP4244003 B2 JP 4244003B2 JP 2003356265 A JP2003356265 A JP 2003356265A JP 2003356265 A JP2003356265 A JP 2003356265A JP 4244003 B2 JP4244003 B2 JP 4244003B2
- Authority
- JP
- Japan
- Prior art keywords
- element chip
- chip
- release member
- mounting method
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- Electroluminescent Light Sources (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Thin Film Transistor (AREA)
Description
図1はTFT(薄膜トランジスタ)チップ30上に離型部材40を形成する工程の断面図である。まず、転写元基板20(TFTアレイ基板)上に剥離層21を介して複数のTFTチップ30を形成する(同図(A))。単一のTFTチップ30には一画素分のTFT(例えば、3個)が含まれており、実装基板10(図1参照)と接続するための複数の接続端子(又はバンプ)31を備えている。
Claims (5)
- 転写元基板上に形成された複数の素子チップの中から選択された何れかの素子チップを実装基板に実装するための方法であって、
転写元基板上に形成された複数の素子チップのうち、転写対象として選択された素子チップ以外の素子チップ上に離型部材を形成する工程と、
前記転写対象として選択された素子チップを、接着剤を介して前記実装基板に接着する接着工程であって、
前記実装基板上の一部の領域であって、前記転写対象として選択された素子チップと対向する領域に接着剤を塗布する工程と、
前記接着剤を介して前記転写元基板を対向配置する工程と、
前記接着剤を固化する工程と、を有する接着工程と、
前記接着工程の後、前記転写対象として選択された素子チップを前記転写元基板から剥離する工程を含む、素子チップの実装方法。 - 請求項1に記載の素子チップの実装方法であって、
前記転写元基板上に形成された前記複数の素子チップを被覆するように前記離型部材を形成する工程と、
前記転写対象として選択された素子チップを被覆している前記離型部材を部分的に除去する工程を含む、素子チップの実装方法。 - 請求項2に記載の素子チップの実装方法であって、
レーザ光の照射により前記離型部材を部分的に除去する工程を含む、素子チップの実装方法。 - 請求項1乃至請求項3のうち何れか1項に記載の素子チップの実装方法であって、
前記離型部材のサイズが、前記転写対象として選択されていない素子チップのサイズと略同一以上であること、
を特徴とする素子チップの実装方法。 - 請求項1乃至請求項4のうち何れか1項に記載の素子チップの実装方法であって、
前記離型部材はフッ素系材料又はテフロン(登録商標)系材料から成る、素子チップの実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003356265A JP4244003B2 (ja) | 2003-10-16 | 2003-10-16 | 素子チップの実装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003356265A JP4244003B2 (ja) | 2003-10-16 | 2003-10-16 | 素子チップの実装方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005123381A JP2005123381A (ja) | 2005-05-12 |
JP4244003B2 true JP4244003B2 (ja) | 2009-03-25 |
Family
ID=34613566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003356265A Expired - Fee Related JP4244003B2 (ja) | 2003-10-16 | 2003-10-16 | 素子チップの実装方法 |
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JP (1) | JP4244003B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105448792B (zh) * | 2014-05-29 | 2018-02-06 | 上海和辉光电有限公司 | 柔性显示器件的制造方法 |
JP2018132715A (ja) * | 2017-02-17 | 2018-08-23 | ソニーセミコンダクタソリューションズ株式会社 | アレイ基板、実装素子、アレイ基板を備えたデバイス、アレイ基板の製造方法 |
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2003
- 2003-10-16 JP JP2003356265A patent/JP4244003B2/ja not_active Expired - Fee Related
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JP2005123381A (ja) | 2005-05-12 |
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