TWI230445B - Circuit board and its manufacturing method, transfer chip, transfer source substrate, optoelectronic apparatus, and electronic machine - Google Patents

Circuit board and its manufacturing method, transfer chip, transfer source substrate, optoelectronic apparatus, and electronic machine Download PDF

Info

Publication number
TWI230445B
TWI230445B TW092127693A TW92127693A TWI230445B TW I230445 B TWI230445 B TW I230445B TW 092127693 A TW092127693 A TW 092127693A TW 92127693 A TW92127693 A TW 92127693A TW I230445 B TWI230445 B TW I230445B
Authority
TW
Taiwan
Prior art keywords
transfer
substrate
thin film
pad electrodes
circuit
Prior art date
Application number
TW092127693A
Other languages
Chinese (zh)
Other versions
TW200416966A (en
Inventor
Mutsumi Kimura
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of TW200416966A publication Critical patent/TW200416966A/en
Application granted granted Critical
Publication of TWI230445B publication Critical patent/TWI230445B/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G02F1/136281—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon having a transmissive semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0106—Neodymium [Nd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01064—Gadolinium [Gd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The subject of the present invention is to provide technology such that excellent conducting state can be secured in electrically connecting a body to be transferred and a substrate of transfer destination by providing a pad electrode between both of them. The invented transfer chip is formed on the first substrate as a transfer unit including: at least a thin film circuit formed by laminated films and a plurality of pad electrodes for connecting the thin film circuit and the other circuit, and is transferred onto the second substrate formed with the wiring from the first substrate. Plural pad electrodes (56d, 56f) are arranged on the whole of one face of the transfer chip, the respective pad electrodes (56d and 56f) are formed to cover a thin film element or thin film electric wiring that constitutes the thin film electric circuit presented under the respective pad electrodes, and the heights of the highest parts (56d, 56f) of a protrusion and recess generated on the surface by forming respective pad electrodes (56d and 56f) are substantially equal to one another.

Description

1230445 (1) 玖、發明說明 【發明所屬之技術領域】 本發明係關於電路的基板間轉印技術的改良及使用此1230445 (1) 发明. Description of the invention [Technical field to which the invention belongs] The present invention relates to the improvement of the circuit-to-substrate transfer technology of a circuit and the use thereof

技術的顯示裝置（光電裝置）及其製造方法。 【先前技術】Display device (photoelectric device) and its manufacturing method. [Prior art]

將薄膜電晶體使用於畫素驅動的顯示裝置（光電裝置 )’例如在薄膜電晶體驅動液晶顯示裝置、薄膜電晶體驅 動有機電激發光顯不裝置、薄§吴電晶體驅動發光二極體顯 不裝置、薄膜電晶體驅動電泳動顯不裝置等之中，薄膜電 晶體構成裝置全體的一部分，除此以外的大部分，大多是 由配線或支持基板等所構成。將如此的顯示裝置（薄膜電 晶體驅動顯示裝置），經過使薄膜電晶體和配線或支持基 板等，成爲一體化的相同製造過程，進行製造的情況，由 於需要用來製作薄膜電晶體之高度複雜的製造過程，一般 而言，製造成本變高。然而，若僅是製造配線或支持基板 ，則不需要高度複雜的製造過程，製造成本也變低。若能 夠將薄膜電晶體和配線或支持基板個別地作成，僅在必要 的部分，配置薄膜電晶體的話，則可以降低薄膜電晶體驅 動顯示裝置的製造成本。 對於如此的期望，正在開發一種在轉印來源基材上， 經由剝離層，形成由薄膜電晶體等的元件所構成的被轉印 層，接著整體地接合在轉印來源基材上，然後對剝離層照 射光而產生剝離，藉由使轉印來源基材從剝離層脫離，而 -4- (2) 1230445 在轉印對象基材上的規定位置形成元件的轉印方法。例如 在日本特開平1 0- 1 2 5 93 1號公報中所揭示者（專利文獻1 )。藉由使用上述轉印方法，由於能夠僅在必要的部分， 配置薄膜電晶體，所以全體平均而言，可以降低此薄膜電 日日體驅動顯不裝置的製造成本。 〔專利文獻1〕 曰本日本特開平1 0- 1 25 93 1號公報 【發明內容】 (發明所欲解決之課題） 使用上述轉印方法，在將由含有薄膜電晶體等的電路 所構成的被轉印體（轉印晶片），轉印到所希望的轉印對 象基材（例如構成顯示裝置的基板等）上的情況，經常藉 由使被轉印體和轉印對象基材的各個焊墊電極（擔任電連 接的連接端子），預先互相對應地形成，來進行被包含在 被轉印體中的元件和被包含在轉印對象基材中的配線等之 間的電連接。此情況，確實地進行被設置在被轉印體中的 焊墊電極與被設置在轉印對象基材中的焊墊電極之間的導 通’在謀求由包含轉印對象基板所構成的顯示裝置等的最 終產品的良率的高、成本削減、及耐久性等的性能的提高 方面，係重要的課題。 因此，本發明的目的在於提供一種技術，當在被轉印 體和轉印對象基材之間設置焊墊電極，而將兩者電連接時 ，可以確保良好的導通狀態。 -5- 1230445 (3) (解決課題所用的手段） 爲了達成上述目的，本發明的電路基板之製造方法， 係包含： 轉印晶片形成製程，用於在第1基板上形成轉印晶片 ，該轉印晶片包含：以積層膜形成之薄膜電路，及作爲連 接該薄膜電路與其他電路用之連接端子的多數個第1焊墊 電極； 轉印對象基板形成製程，用於形成包含電路配線及多 數個第2焊墊電極的第2基板，該第2焊墊電極，係連接 於該電路配線之同時，與形成於上述轉印晶片上之上述多 數個第1焊墊電極之各個對應配置於轉印對象區域；及 轉印製程，用於將上述第1基板上之上述轉印晶片轉 印於上述第2基板上之上述轉印對象區域使上述薄膜電路 連接於上述電路配線而形成電路基板； 上述多數個第1焊墊電極，係涵蓋上述轉印晶片之一 面全體被配置，各第1焊墊電極係形成爲覆蓋構成其下側 存在之上述薄膜電路之薄膜元件或薄膜配線，依此而使表 ®產生之凹凸部分之最高部分之高度於各焊墊電極形成爲 大略相同。 在此，本發明中所稱的「轉印晶片」，係在使用上述 般的轉印技術，具體而言，預先在最初成爲轉印來源的基 板上’形成被轉印體，然後將被轉印體轉印至與轉印來源 基板相異的轉印對象基板（例如構成最終產品的基板）之 剝離轉印技術的情況中，成爲作爲被轉印體的最小單位之 -6- 1230445 (4) 狀態者；例如由包含各種元件或這些元件的組合所構成的 電路而構成，並擔任規定的功能者。 經由擔任電連接的焊墊電極，在作爲如此的被轉印體 之轉印晶片及成爲轉印對象的基板（第2基板）之間，進 行電路形成的情況，根據轉印時的定位精度的程度等’希 望能確保焊墊電極的尺寸（接觸面積）大到一定程度。因 此，焊墊電極大多涵蓋轉印晶片之一面（轉印面）全體’ 佔用大面積地被配置。此情況，轉印晶片側的焊墊電極（ 第1焊墊電極）係跨過薄膜電路的各部分而形成，所以表 面產生的凹凸之情況，變成難以避免。如此的焊墊電極之 表面的凹凸，容易成爲招致轉印時的接觸不良的原因。 因此，在本發明中，形成焊墊電極，使得各焊墊電極 中的焊墊電極表面所產生的凹凸部分之最高部分亦即最高 部分的高度，大略相同。依此，由於能夠使要將轉印晶片 轉印至轉印對象基板上的轉印對象區域時的接觸面，其高 度大略相同，所以可以確保良好的導通狀態。 理想爲：上述多數個第1焊墊電極，係於形成上述薄 膜元件或上述薄膜配線時被附加高度調整膜據以調整上述 凹凸部分之最高部分之高度。依此，容易調整凹凸部分之 最高部分的高度。如此的高度調整膜，例如可以利用形成 上述薄膜元件等的時候所使用的半導體膜、導電膜或是設 在這些膜之間的絕緣膜等，來加以形成。於此情況，由於 能夠在形成薄膜元件等的時候，一起形成高度調整膜，所 以不會招致製程的增加或複雜化等，情況佳。再者，也可 1230445 (5) 以與形成薄膜元件等的薄膜分開，而個別地形成高度調整 膜。 理想爲.於上述轉印對象基板形成製程中，上述多數 個第2焊墊電極，係形成爲覆蓋構成其下側存在之上述電 路配線，依此而使表面產生之凹凸部分之最高部分之高度 於各第2焊墊電極形成爲大略相同。依此，即使在轉印對 象基板（第2基板）上的轉印對象區域不是平坦，而在此 所形成的第2焊墊電極的表面產生凹凸之情況，由於在轉 印對象基板上之轉印對象區域中的與轉印晶片的接觸面， 能夠形成一致地形成大略相同的高度，所以成爲可以確保 良好的導通狀態。 理想爲：上述多數個第2焊墊電極，係於形成上述電 路配線時被附加高度調整膜據以調整上述凹凸部分之最高 部分之高度。依此，容易調整凹凸部分之最高部分的高度 。如此的高度調整膜，例如可以利用形成上述電路配線時 所使用的導電膜、絕緣膜等，來加以形成。於此情況，由 於能夠在形成電路配線時，一起形成高度調整膜，所以不 會招致製程的增加或複雜化等，情況佳。再者，也可以與 形成電路配線的薄膜分開，而個別地形成高度調整膜。 理想爲：上述多數個第1焊墊電極之各個，其於上述 最高部分對應區域中之上述積層膜之膜構成爲相同。又’ 理想爲：上述多數個第2焊墊電極之各個，其於上述最高 部分對應區域中之下側之上述積層膜之膜構成爲相同。在 此，在本發明中稱爲「膜構成爲相同」’係指膜厚、膜材 -8- 1230445 (6) 料、製膜方法等的任一個或全部相同而言。如此，藉由使 最高部分的膜構成作成相同，由於能夠使各焊墊電極的最 高部分的各種特性（例如導電率或機械強度等），更加地 均質化，所以能夠更進一步地提昇導通狀態和提高可靠度 等。 又，本發明的電路基板之製造方法，係包含： 轉印晶片形成製程，用於在第1基板上形成轉印晶片 ，該轉印晶片包含：以積層膜形成之薄膜電路，及作爲連 接該薄膜電路與其他電路用之連接端子的多數個第1焊墊 電極； 轉印對象基板形成製程，用於形成包含電路配線及多 數個第2焊墊電極的第2基板，該第2焊墊電極，係連接 於該電路配線之同時，與形成於上述轉印晶片上之上述多 數個第1焊墊電極之各個對應配置於轉印對象區域；及 轉印製程，用於將上述第1基板上之上述轉印晶片轉 印於上述第2基板上之上述轉印對象區域使上述薄膜電路 連接於上述電路配線而形成電路基板； 上述多數個第1焊墊電極，係涵蓋上述轉印晶片之一 面全體被配置，各第1焊墊電極係形成爲覆蓋構成其下側 存在之上述薄膜電路之薄膜元件或薄膜配線， 上述多數個第2焊墊電極，係和上述多數個第1焊墊 電極之配置對應地涵蓋上述轉印對象區域全體被配置，各 第2焊墊電極係形成爲覆蓋構成其下側存在之上述電路配 線， -9- (7) 1230445 上述第1焊墊電極與第2焊墊電極之各個係形成於， 可使呈對向配置而構成對之一組第1及第2焊墊電極之各 個之表面產生之凹凸部分之最局部分之局度合S十成爲大略 一定。 如上述般，分別被形成在轉印晶片和轉印對象基板（ 第2基板）中的焊墊電極，由於希望確保其尺寸（接觸面 積）大到一定程度，因此係跨過薄膜電路或電路配線的各 部分而形成，所以表面產生的凹凸之情況，變成難以避免 。如此的焊墊電極之表面的凹凸，容易成爲招致轉印時的 接觸不良的原因。 因此，在本發明中，關於被對向配置而成對的一組第 1焊墊電極和第2焊墊電極，係分別形成第1焊墊電極和 第2焊墊電極，使得各焊墊電極表面所產生的凹凸部分之 最局部的局度的合δ十’大略成爲一'定。依此，由於能夠使 對向配置的各個第1焊墊電極和第2焊墊電極確實地接觸 ，所以可以確保良好的導通狀態。 再者，在本發明中，關於各個第1焊墊電極和第2焊 墊電極，理想爲使用上述的高度調整膜來調整最高部分的 高度。進而，關於各個第1焊墊電極和第2焊墊電極，理 想爲使最局部分的膜構成作成相同。藉由此用此種構成所 產生的效果，如上所述。 又，在上述各個本發明中，轉印製程理想爲包含：在 上述轉印晶片上形成之上述第1焊墊電極與上述第2基板 上形成之上述第2焊墊電極之間形成接著層的製程。依此 -10- 1230445 (8) ’能夠作成使得第1焊墊電極和第2焊墊電極間的連接， 更爲強固且確實。再者，接著層，例如使用具有導電性的 接著劑或含有導電性粒子而構成的異方性導電膜等，來加 以形成。 又’轉印晶片形成製程，理想爲包含形成剝離層之製 程，該剝離層爲介於上述第1基板與上述轉印晶片之間， 且具有藉由被賦與能量產生狀態變化以弱化其與上述轉印 晶片間之固接狀況的性質。依此，在轉印時，容易將轉印 晶片從第2基板剝離。再者，能量的施加方法，特別理想 爲藉由使用雷射光等的光照射之方法。若藉由使用光照射 的方法，能夠對任意的區域施加能量，同時可以正確地定 位。 又，本發明的轉印晶片，係作爲至少包含：以積層膜 形成之薄膜電路，及作爲連接該薄膜電路與其他電路用之 多數個焊墊電極，的轉印單位被形成於第1基板，由該第 1基板被轉印至形成有配線之第2基板的轉印晶片； 上述多數個焊墊電極，係涵蓋上述轉印晶片之一面全 體被配置’各焊塾電極係形成爲覆盖構成其下側存在之上 述薄膜電路之薄膜元件或薄膜配線’依此而使表面產生之 凹凸部分之最高部分之高度於各焊墊電極形成爲大略相同 〇 藉由採用此種構成，由於能夠將轉印晶片被轉印至轉 印對象基板（第2基板）上的轉印對象區域時的接觸面’ 成爲大略相同的高度，所以能夠確保良好的導通狀態。 -11 - 1230445 ⑼ 又，本發明係將關於本發明的轉印晶片多數地形成在 基板上而構成的轉印來源基板。又，該轉印來源基板，理 想爲另具有剝離層，該剝離層爲介於上述基板與上述轉印 晶片之間，且具有藉由被賦與能量產生狀態變化以弱化其 與上述轉印晶片間之固接狀況的性質。Use of thin film transistors for pixel-driven display devices (photoelectric devices), such as thin film transistors driving liquid crystal display devices, thin film transistors driving organic electroluminescent display devices, and thin film transistor driving light emitting diode displays Among devices, thin-film transistor-driven electrophoretic display devices, etc., the thin-film transistor constitutes a part of the entire device, and most of the other parts are mostly composed of wiring or a support substrate. When such a display device (thin-film transistor-driven display device) is manufactured through the same manufacturing process that integrates the thin-film transistor and the wiring or the support substrate, it is highly complicated to produce a thin-film transistor due to the need for manufacturing. In general, the manufacturing cost becomes higher. However, if only the wiring or the supporting substrate is manufactured, a highly complicated manufacturing process is not required, and the manufacturing cost is also reduced. If the thin-film transistor and the wiring or the support substrate can be made individually, and the thin-film transistor is arranged only in a necessary portion, the manufacturing cost of the thin-film transistor-driven display device can be reduced. In response to such expectations, a transfer-source substrate is formed on the transfer-source substrate through a release layer to form a transferred layer composed of elements such as thin-film transistors, and then integrally bonded to the transfer-source substrate. The peeling layer is irradiated with light to cause peeling, and the transfer source substrate is detached from the peeling layer, and -4- (2) 1230445 forms the element transfer method at a predetermined position on the transfer target substrate. For example, it is disclosed in Japanese Unexamined Patent Publication No. 10-125 2 93 1 (Patent Document 1). By using the above-mentioned transfer method, since the thin film transistor can be arranged only at a necessary portion, the manufacturing cost of the thin film solar device can be reduced on average as a whole. [Patent Document 1] Japanese Patent Application Laid-Open No. 1 0- 1 25 93 1 [Summary of the Invention] (Problems to be Solved by the Invention) Using the transfer method described above, a substrate composed of a circuit including a thin film transistor or the like is used. When a transfer body (transfer wafer) is transferred to a desired transfer target substrate (for example, a substrate constituting a display device, etc.), the transfer target and the transfer target substrate are often welded to each other. Pad electrodes (connection terminals serving as electrical connections) are formed in correspondence with each other in advance to perform electrical connection between the elements contained in the transfer target and wirings or the like contained in the transfer target substrate. In this case, the conduction between the pad electrode provided in the object to be transferred and the pad electrode provided in the substrate to be transferred is reliably performed, and a display device including a substrate to be transferred is sought. These are important issues in terms of high yield of final products, cost reduction, and improvement of performance such as durability. Therefore, an object of the present invention is to provide a technique capable of ensuring a good conduction state when a pad electrode is provided between a transfer target and a transfer target substrate and the two are electrically connected. -5- 1230445 (3) (Means used to solve the problem) In order to achieve the above object, the method for manufacturing a circuit board of the present invention includes a transfer wafer forming process for forming a transfer wafer on a first substrate. The transfer wafer includes a thin film circuit formed of a laminated film and a plurality of first pad electrodes as connection terminals for connecting the thin film circuit to other circuits. The second substrate of each of the second pad electrodes, the second pad electrodes are connected to the circuit wiring and are disposed on the transfer board in correspondence with each of the plurality of first pad electrodes formed on the transfer wafer. A printing target area; and a transfer process for transferring the transfer wafer on the first substrate to the transfer target area on the second substrate so that the thin film circuit is connected to the circuit wiring to form a circuit substrate; The plurality of first pad electrodes are arranged so as to cover the entire surface of the transfer wafer, and each of the first pad electrodes is formed so as to cover the thin layer existing on the lower side thereof. The thin film element or thin film wiring of the film circuit is formed so that the height of the highest part of the uneven portion produced by the table ® is substantially the same as that of each pad electrode. Here, the "transfer wafer" referred to in the present invention uses the above-mentioned transfer technology. Specifically, a transfer target is formed on a substrate that is a transfer source in advance, and then transferred. In the case of a peel transfer technology in which a printed body is transferred to a transfer target substrate (for example, a substrate constituting a final product) different from the transfer source substrate, it becomes -6- 1230445 (4 ) State person; for example, a person composed of a circuit composed of various elements or a combination of these elements and serving as a predetermined function. In the case where a circuit is formed between a transfer wafer which is such a transfer target and a substrate (second substrate) to be transferred via a pad electrode serving as an electrical connection, according to the positioning accuracy during transfer It is desirable to ensure the size (contact area) of the pad electrode to a certain extent. Therefore, most of the pad electrodes cover the entire surface (transfer surface) of the transfer wafer 'and are arranged in a large area. In this case, since the pad electrode (the first pad electrode) on the transfer wafer side is formed across each part of the thin film circuit, it is difficult to avoid the occurrence of unevenness on the surface. Such unevenness on the surface of the pad electrode is likely to cause a contact failure during transfer. Therefore, in the present invention, the pad electrode is formed so that the height of the highest portion, that is, the highest portion, of the uneven portion generated on the surface of the pad electrode in each pad electrode is substantially the same. Accordingly, the contact surface when the transfer wafer is to be transferred to the transfer target region on the transfer target substrate can be made substantially the same in height, so that a good conduction state can be ensured. Preferably, the plurality of first pad electrodes are adjusted by adding a height adjustment film when forming the thin film element or the thin film wiring to adjust the height of the highest portion of the uneven portion. This makes it easy to adjust the height of the highest portion of the uneven portion. Such a height-adjusting film can be formed using, for example, a semiconductor film, a conductive film, or an insulating film provided between these films when forming the above-mentioned thin film element and the like. In this case, since it is possible to form a height adjustment film together when forming a thin-film element or the like, it does not cause an increase in process or complication, and the situation is good. Alternatively, 1230445 (5) may be formed separately from the thin film forming a thin film element or the like, and the height adjusting films may be formed individually. Preferably, in the above-mentioned transfer target substrate forming process, the plurality of second pad electrodes are formed so as to cover the above-mentioned circuit wiring existing on the lower side of the substrate, and the height of the highest portion of the uneven portion generated on the surface is thereby formed The second pad electrodes are formed substantially the same. As a result, even if the transfer target area on the transfer target substrate (second substrate) is not flat, the surface of the second pad electrode formed here may have unevenness. Since the contact surface with the transfer wafer in the print target area can be formed to have a substantially uniform height, a good conduction state can be ensured. Preferably, the plurality of second pad electrodes are adjusted by adding a height adjustment film to form the circuit wiring to adjust the height of the highest portion of the uneven portion. Accordingly, it is easy to adjust the height of the highest portion of the uneven portion. Such a height-adjusting film can be formed using, for example, a conductive film, an insulating film, and the like used in forming the circuit wiring described above. In this case, since the height adjustment film can be formed together when the circuit wiring is formed, it does not cause an increase in process or complication, and the situation is good. Alternatively, the height adjustment film may be formed separately from the film forming the circuit wiring. Preferably, each of the plurality of first pad electrodes has the same film configuration as the laminated film in the region corresponding to the highest portion. Further, it is preferable that each of the plurality of second pad electrodes has the same film configuration as the above-mentioned laminated film in the corresponding region of the highest portion. Herein, "the film structure is the same" in the present invention means that any or all of the film thickness, the film material, and the film-forming method, etc. are the same. In this way, by making the film structure of the highest portion the same, various characteristics (such as conductivity or mechanical strength) of the highest portion of each pad electrode can be more homogenized, so the conduction state and Improve reliability, etc. In addition, the method for manufacturing a circuit board of the present invention includes: a transfer wafer forming process for forming a transfer wafer on a first substrate, the transfer wafer including: a thin film circuit formed of a laminated film; A plurality of first pad electrodes for connection terminals of thin film circuits and other circuits; a process for forming a transfer target substrate for forming a second substrate including circuit wiring and a plurality of second pad electrodes, and the second pad electrodes Is connected to the circuit wiring, and is arranged corresponding to each of the plurality of first pad electrodes formed on the transfer wafer in the transfer target area; and a transfer process for transferring the first substrate to the first substrate The transfer wafer is transferred to the transfer target area on the second substrate, and the thin film circuit is connected to the circuit wiring to form a circuit board. The plurality of first pad electrodes cover one side of the transfer wafer. The whole is arranged, and each first pad electrode is formed so as to cover the thin film element or thin film wiring constituting the above-mentioned thin film circuit, and the plurality of second pads are formed. The electrodes are arranged corresponding to the arrangement of the plurality of first pad electrodes to cover the entire area of the transfer target area, and each of the second pad electrodes is formed to cover the above-mentioned circuit wiring existing on the lower side, -9- ( 7) 1230445 Each of the first pad electrode and the second pad electrode is formed on the surface of each of the first and second pad electrodes, which can be arranged in a pair to form a pair of uneven portions. The most complete part of the game is almost certain. As described above, since the pad electrodes formed on the transfer wafer and the transfer target substrate (second substrate) are required to ensure a large size (contact area) to a certain extent, they are across thin film circuits or circuit wiring. It is difficult to avoid the occurrence of unevenness on the surface. Such unevenness on the surface of the pad electrode is likely to cause a contact failure during transfer. Therefore, in the present invention, regarding a set of first pad electrodes and second pad electrodes arranged in pairs facing each other, the first pad electrode and the second pad electrode are respectively formed so that each pad electrode The sum of the most local localities of the unevenness produced on the surface is almost constant. Accordingly, since each of the first pad electrodes and the second pad electrodes arranged in the opposite direction can be reliably brought into contact with each other, a good conduction state can be ensured. Furthermore, in the present invention, it is desirable that the height of the highest portion is adjusted using the above-mentioned height adjustment film with respect to each of the first pad electrode and the second pad electrode. Furthermore, it is desirable that the first pad electrode and the second pad electrode have the same film configuration at the most local portion. The effects produced by this configuration are as described above. In each of the above-mentioned present inventions, the transfer process preferably includes forming an adhesive layer between the first pad electrode formed on the transfer wafer and the second pad electrode formed on the second substrate. Process. According to this -10- 1230445 (8) ′, the connection between the first pad electrode and the second pad electrode can be made stronger and more reliable. The adhesive layer is formed using, for example, a conductive adhesive or an anisotropic conductive film composed of conductive particles. The process of forming a transfer wafer preferably includes a process of forming a release layer which is interposed between the first substrate and the transfer wafer, and has a state change caused by being imparted with energy to weaken its contact with the wafer. The properties of the above-mentioned transfer wafers. Accordingly, it is easy to peel the transfer wafer from the second substrate during transfer. The method of applying energy is particularly preferably a method of irradiating with light such as laser light. By using the method of light irradiation, energy can be applied to an arbitrary area, and at the same time, it can be accurately positioned. The transfer wafer of the present invention is formed on a first substrate as a transfer unit including at least a thin film circuit formed of a laminated film and a plurality of pad electrodes for connecting the thin film circuit to other circuits. The first substrate is transferred to a transfer wafer on which the wiring is formed on the second substrate. The plurality of pad electrodes are arranged so as to cover the entire surface of the transfer wafer. Each pad electrode is formed so as to cover it. The thin-film element or thin-film wiring of the above-mentioned thin-film circuit existing thereon is formed so that the height of the highest portion of the uneven portion generated on the surface is substantially the same as that of each of the pad electrodes. The contact surface ′ when the wafer is transferred to the transfer-target region on the transfer-target substrate (second substrate) has approximately the same height, so that a good conduction state can be ensured. -11-1230445 ⑼ The present invention relates to a transfer source substrate in which a plurality of transfer wafers according to the present invention are formed on a substrate. The transfer source substrate preferably further includes a release layer, which is interposed between the substrate and the transfer wafer, and has a state change caused by being imparted with energy to weaken the transfer wafer. The nature of the ground connection.

又，本發明係使用藉由本發明的製造方法所製造的電 路基板，而被製造的光電裝置。更具體而言，本發明係關 於將上述電路基板和藉由該電路基板而被控制動作之光電 元件加以組合所構成的光電裝置。或者，本發明係使用上 述轉印晶片或上述轉印來源基板而製造的光電裝置。依此 ，可以提高光電裝置的良率、降低成本、及提高耐久性等 的性能。再者，本發明中的「光電裝置」包含由電激發光 (E L )元件、電發光元件、電漿發光元件、電泳動元件 、液晶元件等的各種光電元件所構成的顯示裝置。The present invention is a photovoltaic device that is manufactured using a circuit board manufactured by the manufacturing method of the present invention. More specifically, the present invention relates to a photovoltaic device configured by combining the above-mentioned circuit substrate and a photovoltaic element whose operation is controlled by the circuit substrate. Alternatively, the present invention is a photovoltaic device manufactured using the transfer wafer or the transfer source substrate. Accordingly, the performance of the photovoltaic device can be improved, the cost can be reduced, and the durability can be improved. Furthermore, the "photoelectric device" in the present invention includes a display device composed of various optoelectronic elements such as an electro-excitation light (EL) element, an electro-luminescent element, a plasma light-emitting element, an electrophoretic element, and a liquid crystal element.

又，本發明係將上述關於本發明的光電裝置，作爲顯 示部加以使用的電子機器。在此，電子機器包含：攝影機 、手機、個人電腦、攜帶型資訊端末裝置（亦即P D A )或 是其他各種電子機器。藉由使用關於本發明的光電裝置， 可以提高電子機器的良率、降低成本、及提高耐久性等的 性能。 【實施方式】 (本發明之實施形態） 以下，說明關於應用本發明的一實施形態的薄膜電晶 -12- (10) 1230445 體驅動型顯示裝置。在本實施形態中，作爲薄膜電晶體驅 動型顯示裝置的一例，說明關於由包含光電元件的一種類 亦即有機EL元件所構成的有機EL顯示裝置。 第1圖係槪略地表不本實施形態的有機E L顯示裝置 的構成之圖。如該圖所示的有機E L顯示裝置1 〇 〇，係將 由包含3個顏色畫素1、2、3所構成的畫素（基本畫素） 1 0 1，矩陣狀地排列多數個而構成。各顏色畫素，例如顏 色畫素1爲紅色、顏色畫素2爲綠色、顏色畫素3爲藍色 。使用內裝有由包含複數個薄膜電晶體（TFT )所構成的 驅動電路（薄膜電路）之晶片，來驅動各畫素1 〇、1。 第2圖係說明關於畫素1 01的構造之圖。第2圖（a )係表不畫素1〇1的平面圖、第2圖（b)係表示第2圖 (a)中的 A—A /剖面圖。再者，在第2圖（a)中，爲 了說明的方便，省略構成要件的一部份地加以表示。 如第2圖所示，畫素1 01，係在由玻璃等的絕緣材料 所組成的基板1 〇上’由下層側開始，依序地積層第1配 線層1 2、第2配線層1 4、及發光元件層1 6而形成。再者 ，在第2圖（a )中，爲了說明第1和第2配線層的構造 ，省略第2配線層1 4的一部份和發光元件層1 6地加以袠 ° 第1配線層1 2，係被構成：包含被形成在基板1 〇 '上 的配線20、及用來將該配線20和被包含在第2配線層1 4 中的配線（詳後述）之間加以電連接而設置的開口部22 。經由此開口部22，被包含在第2配線層1 4中的配線， •13- 1230445 (11) 各 線 元 、 34 焊 配 ) 省 層 體 各 10 基 厂 線 40 42 護 形 邰份地與配線20抵接，來謀求兩者的電連接。又，在 配線2 0之間，形成絕緣構件（例如氧化矽等）◦再者 在第2圖（a )中，省略表示該絕緣構件。 第2配線層1 4，係被構成包含：被形成在第1配 層1 2上的配線3 〇、用來將此配線3 0和被包含在發光 件層1 6中的電極（詳後述）之間加以電連接的插塞3 2 用來驅動發光元件層1 6的晶片3 4、及由用來將此晶片 和配線3 0間加以電連接的複數個焊墊電極3 6所構成的 墊群38。又，在第2圖（a)中雖然省略其圖示，在各 線3 0或插塞3 2等之間，形成絕緣構件（例如氧化矽等 。再者’在第2圖（a )中，關於晶片3 4，雖然也加以 略表示，但是該晶片3 4係被形成在上述焊墊群3 8上。 在本實施形態中，藉由第1配線層1 2和第2配線 1 4來形成電路配線。又，晶片3 4係包含複數薄膜電晶 而構成；具備分別獨立地控制包含在1個畫素1 〇〗內的 顏色畫素1、2、3之功能。此晶片3 4被形成在與基板 相異的別的基板（轉印來源基板）上，然後從轉印來源 板剝離而被轉印到基板1 0上。再者，該晶片3 4係對應 轉印晶片」。該轉印方法詳如後述。 發光元件層16，係被構成包含：被形成在第2配 層1 4上的3個畫素電極40、被配置成面對此畫素電極 之共通電極42、被配置在各畫素電極4〇和共通電極 之間的3個發光層44、及被形成在共通電極42上的保 層46。又，在各畫素電極4〇或各發光層44等之間， -14 - 1230445 (12) 成絕緣構件（例如氧化砂等）。藉由各畫素電 層在其上的各發光層44、及共通電極42，形 元件（光電元件）；藉由各發光元件，分別構 素1、2、3。根據上述晶片3 4，經由各畫素I 成爲能夠對各發光層44，分別獨立地供給電 顏色畫素1、2、3分別獨立地被開關。 接著，關於本實施形態的晶片3 4的構造 例來加以詳細地說明。 第3圖係表示晶片3 4的內部構造的平面 圖中，爲了能夠容易瞭解包含在晶片3 4內的 (TFT )或薄膜配線等的構造，省略表示設置 電晶體等的頂面上的構成要件。關於圖示中所 要件，將於以後說明。 如弟3圖所不，晶片3 4係被構成包含： 被形成在右側區域之3個開關薄膜電晶體S T 1 ;以及左右排列地被形成在左側區域之3個驅 體 DTI、DT2、DT3。 在本實施形態中，關於一個顏色畫素，係 開關薄膜電晶體和一個驅動薄膜電晶體加以組 畫素電路，來加以驅動。具體而言，第3圖所 膜電晶體S T 1，係對應輸入信號（掃描信號） 電晶體D T 1動作。驅動薄膜電晶體D T 1，控 色畫素1的發光層44中流動的電流。同樣的 關薄膜電晶體ST2和驅動薄膜電晶體DT2加 極4 0和積 成3個發光 成各顏色畫 1極 4 0，而 源，使得各 ，表示具體 圖。在第3 薄膜電晶體 在這些薄膜 省略的構成 上下排列，地 、ST2 、 ST3 動薄膜電晶 藉由將一個 合所構成的 示的開關薄 使驅動薄膜 制在構成顏 ，藉由將開 以組合而成 -15- (13) 1230445 的畫素電路，來控制在構成顏色畫素2的發光層4 4中流-動的電流。藉由將開關薄膜電晶體S T 3和驅動薄膜電晶體 DT3加以組合而成的畫素電路，來控制在構成顏色畫素3 的發光層4 4中流動的電流。 上述各開關薄膜電晶體和各驅動薄膜電晶體’包含用 來形成第1薄膜配線層、及薄膜電晶體的活性區域等的半 導體膜；構成包含：被形成在第1薄膜配線層上的半導體 層、及被形成在該半導體層上的第2薄膜配線層。在第3 圖中，爲了明確地表示出各層的區別，分別藉由將第1薄 膜配線層反白、將半導體層以往右下的粗陰影線、將第2 薄膜配線層以往右上的細陰影線，來加以表示。又，在各 層的層間，形成由S i Ο 2等所構成的絕緣層。 接著，一邊參照第3圖，一邊分別詳細地說明第1薄 膜配線層、半導體層、及第2薄膜配線層的構造。 第1薄膜配線層係被構成包含：薄膜配線50 a〜50 d 。薄膜配線50a，兼作爲各開關薄膜電晶體ST1、ST2、 ST3的閘極電極，同時與被包含在第2薄膜配線層中的薄 膜配線54a電連接。對於此薄膜配線50a，藉由經由薄膜 配線54a供給掃描信號，能夠控制各開關薄膜電晶體ST1 、ST2、ST3的動作。 又，在第3圖中雖然省略薄膜配線54a的圖示，但是 實際上係與被設置在第2薄膜配線層上側的焊墊電極（擔 任電連接的連接端子）電連接；經由此焊墊電極，掃描信 號從晶片3 4的外邰被傳達至薄膜配線5 4 a。關於焊墊電 -16- 1230445 (14) 極的詳細，容後說明。在本實施形態中’如此地對 將掃描信號供給至各開關薄膜電晶體S T 1、S T2、 配線，加以共通化，藉由作成一個共通配線’來減 薄膜配線層的形成所需要的面積’同時減少焊墊電 量，達成晶片3 4尺寸的縮小。進而’藉由焊墊電 (也就是連接處）變少’轉印時發生接觸不良的機 少。 薄膜配線5 0 b，與半導體膜5 2 a電連接；係擔 開關薄膜電晶體s τ 1供給的電流’傳達至驅動薄膜 DT1的功能，同時兼作爲驅動薄膜電晶體DT1的 極。 薄膜配線5 0 c，經由被包含在第2薄膜配線層 膜配線54d，與半導體膜52b電連接；係擔任將從 膜電晶體ST2供給的電流，傳達至驅動薄膜電晶 的功能，同時兼作爲驅動薄膜電晶體DT2的閘極電 薄膜配線50d，與半導體膜52c電連接；係擔 開關薄膜電晶體S T3供給的電流，傳達至驅動薄膜 DT3的功能，同時兼作爲驅動薄膜電晶體DT3的 極。 半導體層係被構成包含半導體膜52a〜52k。 膜5 2a，其一端側與薄膜配線54b連接，另一端則 配線50b連接，而擔任開關薄膜電晶體ST1的活性 半導體膜5 2 b ’其一端側與薄膜配線5 4 c連接，另 與薄膜配線54d連接，而擔任開關薄膜電晶體ST2 於用來 ST3 之 少第1 極的數 極數量 率也變 任將從 電晶體 閘極電 中的薄 開關薄 體 DT2 極。 任將從 電晶體 閘極電 半導體 與薄膜 區域。 一端則 的活性 -17- 1230445 (15) 區域。半導體膜52c，其一端側與薄膜配線54e連接，另 一端則與薄膜配線50d連接，而擔任開關薄膜電晶體ST3 的活性區域。 半導體膜52d，分別與薄膜配線54g、54f連接，同 時也與後述的焊墊電極（在此未圖示）連接，且擔任驅動 薄膜電晶體DT1的活性區域。半導體膜52e，分別與薄膜 配線54h、54i連接，同時也與後述的焊墊電極（在此未 圖示）連接，且擔任驅動薄膜電晶體DT2的活性區域。 半導體膜52f，分別與薄膜配線54j、54k連接，同時也與 後述的焊墊電極（在此未圖示）連接，且擔任驅動薄膜電 晶體DT3的活性區域。 半導體膜52g，被形成在薄膜配線54c的下層，係用 來調整被形成在該薄膜配線54c的上層之焊墊電極的高度 。同樣的，半導體膜52h，被形成在薄膜配線54e的下層 ，係用來調整被形成在該薄膜配線54e的上層之焊墊電極 的高度。又，關於半導體膜5 2 i、5 2 j、5 2 k也是同樣的， 係用來調整被形成在薄膜配線5 4 b、5 4 a、5 4 k的上層之焊 墊電極的高度。再者，焊墊電極的詳細（特別是焊墊電極 的「高度」之規定方法等），容後說明。 如此，在本實施形態中，在形成擔任薄膜電晶體的活 性區域之半導體膜的時候，一倂形成用來調整焊墊電極的 高度之半導體膜，亦即形成「高度調整膜」。依此，不會 導致製程的增加或複雜化等的情況發生，並能夠適當地調 整焊墊電極的高度。再者，除了使用半導體膜的情況以外 -18- 1230445 (16) ’也可以利用薄膜配線或絕緣膜等，來形成高度調整膜。 第2薄膜配線層，係被構成包含薄膜配線54a〜54k 。在此，關於被形成在第2薄膜配線層的上側，而擔任晶 片3 4的內部電路和外部之間的電連接之焊墊電極，說明 與薄膜配線54a〜54k之間的連接關係。 第4圖係說明關於焊墊電極的圖。如該圖所示，在晶 片3 4之第2薄膜配線層的上側，設置1 〇個焊墊電極5 6 a 〜5 6j。這些焊墊電極56a〜5 6j，係被構成與被包含在上 述畫素1 〇 1中的各焊墊電極3 6 (參照第2圖）一對一地 對應。將第4圖所示的晶片3 4反轉，藉由使各焊墊電極 5 6a等，相對於被包含在上述第2圖所述之畫素101中之 焊墊群3 8的各焊墊電極3 6，面對面地貼合，進行晶片3 4 的轉印。關於晶片3 4的轉印方法詳如後述。 焊墊電極5 6a，經由被形成在第2薄膜配線上的絕緣 膜中的開口部55a，與薄膜配線54a電連接。掃描信號經 由此焊墊電極56a從外部被供應至薄膜配線54a，來驅動 開關薄膜電晶體ST1〜ST3。焊墊電極56b，經由被形成 在薄膜配線54b上的絕緣膜中的開口部55b，與薄膜配線 5 4b電連接。電流經由此焊墊電極5 6b從外部被供應至薄 膜配線54b，來將電流供應至開關薄膜電晶體ST 1的活性 區域。焊墊電極5 6 c，經由被形成在薄膜配線5 4 c上的絕 緣膜中的開口部5 5 c，與薄膜配線5 4 c電連接。電流經由 此焊墊電極56c從外部被供應至薄膜配線54c，來將電流 供給至開關薄膜電晶體ST2的活性區域。焊墊電極56d， -19- 1230445 (17) 經由被形成在薄膜配線54e上的絕緣膜中的開口部55d， 與薄膜配線54e電連接。電流經由此焊墊電極56d從外部 被供應至薄膜配線54e，來將電流供應至開關薄膜電晶體 S T 3的活性區域。 焊墊電極5 6 e，經由被形成在薄膜配線5 4 f上的絕緣 膜中的開口部5 5 e，與薄膜配線5 4 f電連接。電流經由此 焊墊電極56e從外部被供應至薄膜配線54f，來將電流供 應至驅動薄膜電晶體DT1的活性區域。焊墊電極56f，經 由被形成在薄膜配線54g上的絕緣膜中的開口部55f，與 薄膜配線54g電連接。此焊墊電極56e與上述焊墊電極 3 6的其中一個電連接。而且，從驅動薄膜電晶體DT1輸 出的電流，經由薄膜配線54g、焊墊電極56f及與該焊墊 電極5 6f電連結之焊墊電極3 6，被供應至顏色畫素1。 焊墊電極56g，經由被形成在薄膜配線54h上的絕緣 膜中的開口部5 5 g，與薄膜配線5 4 h電連接。電流經由此 焊墊電極56g從外部被供應至薄膜配線54h，來將電流供 應至驅動薄膜電晶體DT2的活性區域。焊墊電極56h，經 由被形成在薄膜配線54i上的絕緣膜中的開口部55h，與 薄膜配線54i電連接。此焊墊電極56h與上述焊墊電極36 的其中一個電連接。而且，從驅動薄膜電晶體DT2輸出 的電流，經由薄膜配線54i、焊墊電極56h及與該焊墊電 極5 6h電連結之焊墊電極3 6，被供應至顏色畫素2。 焊墊電極56i，經由被形成在薄膜配線54j上的絕緣 膜中的開口部5 5 i，與薄膜配線5 4 j電連接。電流經由此 -20- 1230445 (18) 焊墊電極5 6 i從外部被供應至薄膜配線5 4 j，來將電流供 應至驅動薄膜電晶體DT3的活性區域。焊墊電極5 6j，經 由被形成在薄膜配線54k上的絕緣膜中的開口部5 5j，與 薄膜配線54k電連接。此焊墊電極56j與上述焊墊電極36 的其中一個電連接。而且，從驅動薄膜電晶體DT3輸出 的電流，經由薄膜配線5 4k '焊墊電極5 6i及與該焊墊電 極5 6 i電連結之焊墊電極3 6，被供應至顏色畫素3。 接著，說明關於被設置在晶片3 4上的各焊墊電極 56a〜5 6j的高度。 第5圖係說明關於焊墊電極的高度之圖。具體而言， 第5圖（a)係表示從第3圖和第4圖所示的B— β /方向 來看焊墊電極5 6d所得到的剖面圖；第5圖（b )係表示 從第3圖和第4圖所示的C 一 C /方向來看焊墊電極56f 所得到的剖面圖。 如第5圖（a )所示，焊墊電極5 6 d具有2處從晶片 3 4的底面算起的高度（離開距離）最高的部分亦即「最 高部分」。而且，這2處最高部分56d— 1、56d— 2，其 從晶片34的底面算起的局度，分別爲L1。又，如第5圖 (b )所示，焊墊電極5 6 f具有1處最高部分5 6 f - 1 ;該 最高部分56f— 1之從晶片34的底面算起的高度爲L1。 進而，關於未圖示的其他焊墊電極5 6 a等，分別具有至少 1處之從晶片34的底面算起的高度爲li之最高部分。 亦即，複數個焊墊電極5 6 a〜5 6 j，由於被形成在將薄 膜配線層或半導體層等加以積層所形成的薄膜電路的頂面 -21 - (19) 1230445 ，所以與外部（具體而言，對向配置的各焊墊電極36) 之間的接觸面爲非平坦。因此，在本實施形態中’各焊墊 電極分別具有至少1處的最高部分，且這些焊墊電極係形 成使得其最高部分的高度大略爲相同的L 1 °如此’爲了 使最高部分的高部調整成大約爲相同的L 1 ’將對於薄膜 電路的構成沒有直接關係的半導體膜（或絕緣膜等）’作 爲高度調整膜，加以適當地形成。又，複數個焊墊電極 5 6a〜5 6j，其各個對應最高部分之區域中的積層膜的膜構 成，係相同的。 再者，在第5圖所示的例中，係以晶片3 4的底面作 爲「基準面」來規定各最高部分的高度L1;但是基準面 也不被限定於此，只要將可以作爲共通的基準之其他的平 面（例如薄膜配線5 0 a等的形成面或半導體膜5 2 e等的形 成面等），作爲基準面便可以。 接著，詳細地說明關於被形成在上述晶片3 4內的各 焊墊電極5 6 a〜5 6 j、及以一對一地對應而被形成在各晝素 1 0 1內的複數個焊墊電極3 6。 6圖和弟7圖係|兌明關於被形成在畫素1 〇 1內的焊 墊電極36之圖。第6圖係將包含第2圖所示的畫素1〇1 內的焊墊電極3 6之區域加以擴大表示的圖。在此，考量 說明的方便’爲了使各焊墊電極3 6的區別變容易，以符 號置換焊墊電極3 6 a〜3 6 j來加以表示。各焊墊電極3 6 a〜 3 6 j，分別對應晶片3 4上的各焊墊電極5 6 a〜5 6 j。又，第 7圖（a)係表τκ從第6圖所示的D— 方向來看焊墊電 -22- 1230445 (20) 極3 6d所得到的剖面圖；第7圖（b )係表示從第 示的E — E >方向來看焊墊電極3 6 f所得到的剖面圖 如第7圖（a)所示，焊墊電極36d具有2處 有畫素101的基板10之底面算起的高度爲最高的 即「最局邰分」。而且，這2處最高部分36d— 1 2，其從基板1 0的底面算起的高度，分別爲L2。 第7圖（b)所示，焊墊電極36f具有2處最高部5 1、36f — 2，垣些取局部分36f — 1、36f — 2的局度 進而，關於未圖示的其他焊墊電極3 6 a等，分別具 1處之從基板1 〇的底面算起的高度爲L2之最高部: 亦即，複數個焊墊電極36a〜3 6j，由於被形成 線層或絕緣層等加以積層所形成的電路配線的頂面 與外部（具體而言，對向配置的各焊墊電極5 6 a等 的接觸面爲非平坦。因此，在本實施形態中，各焊 分別具有至少1處的最高部分，且這些焊墊電極係 得其最高部分的高度大略爲相同的L2。又，複數 電極3 6a〜3 6j，其各個對應最高部分之區域中的積 膜構成，係相同的。 再者，在第7圖所示的例中，雖然沒有特別地 度調整膜，但是根據焊墊電極的形成位置，也有需 況。在此種情形下，爲了調整最高部分的高度，使 與L2相同，也可以將對於電路配線的構成沒有直 的絕緣膜等，作爲高度調整膜，加以適當地形成。 方法，與上述焊墊電極56a等的情況（參照第5圖 6圖所 I ° 從形成 部份亦 、36d — 又，如 > 36f-爲L2。 有至少 分。 在將配 ，所以 )之間 墊電極 形成使 個焊墊 層膜的 設置局 要的情 一 其大略 接關係 具體的 )是同 -23- 1230445 (21) 樣的。 本實施形態的晶片3 4具有上述般的構成；接著說明 關於本實施形態的有機EL顯示裝置的製造方法。在本實 施形態中，係使用：預先將上述晶片3 4複數地形成在轉 印來源基板上，然後將該晶片3 4從第1基板剝離，而轉 印在構成有機EL顯示裝置之基板上的轉印技術。 第8圖和第9圖係說明關於本實施形態的製造方法的 圖。該轉印方法，包含以下說明的第1製程〜第5製程。 <第1製程> 第1製程，如第8圖（a )所示，在轉印來源基板60 上，形成剝離層（光吸收層）62。 轉印來源基板60，理想爲具有可以使光透過的透過 性者。依此，能夠經由轉印來源基板將光照射在剝離層上 ，而藉由光照射，能夠正確且迅速地將剝離層剝離。此情 況，光的透過率理想爲1 〇 %以上，更理想爲5 0 %以上。這 是因爲光透過率越高則光的減衰（損失）越少，只要以更 小的光量便可以將剝離層62剝離。 又，轉印來源基板60，理想爲以可靠度高的材料來 構成；特別理想是以耐熱性優異的材料來構成。其理由爲 :例如在形成作爲被轉印體的晶片3 4時，根據其種類或 形成方法，製程溫度會變高（例如3 5 0〜1 0 0 0 °C左右）， 即使在此種情況，若轉印來源基板6 0的耐熱性優異，當 將晶片3 4形成在轉印來源基板6 0上的時候，其溫度條件 -24- 1230445 (22) 等的成膜條件的設定範圍寬。依 製造多數個晶片的時候，可以進 夠可靠度高地製造出高性能的元 因此，轉印來源基板60，當 溫度爲Tm ax時，理想爲以應變 構成。具體而言，轉印來源基板 點理想爲3 5 0 °C以上，更理想爲 料，例如石英玻璃、康寧7 〇 5 9、 的耐熱玻璃。 又，轉印來源基板6 0的厚 通常理想爲〇 . 1〜5 · 0 m m，更理充 源基板60的厚度越厚則強度提 基板60的透過率低的情況，則 況。再者，當轉印來源基板60 厚度也可以超過前述上限値。再 光，轉印來源基板60的厚度，理 轉印來源基板雖然有如此的 基板與成爲最終製品的轉印對象 地利用，所以即使是使用較高價 ，故可以減少製造成本的上升。 剝離層62係具有：吸收照 界面產生剝離（以下成爲「層內 的性質；理想爲：藉由光照射， 原子間或分子間的結合力消失或 此，當在轉印來源基板上 行所希望的高溫處理，能 件或電路寺。 以形成晶片3 4時的最高 點爲T m a X以上的材料來 60的構成材料，其應變 5 0CTC以上。此種構成材 曰本電氣玻璃OA - 2等 度雖然沒有特別的限定， I爲 0 · 5〜1 · 5 m m。轉印來 昇，若越薄則當轉印來源 較不易發生光的減衰之情 的光透過率高的情況，其 者，爲了能夠均勻地照射 丨想爲均勻的。 各種條件，但是轉印來源 基板相異，由於可以重複 的材料，由於重複地使用 射光，而在其層內及/或 剝離」、「界面剝離」） 構成剝離層6 2的物質之 減少，亦即產生脫離而達 -25- 1230445 (23) 成層內剝離及/或界面剝離。 進而，也有藉由光照射，而從剝離層6 2放出氣體’ 而被發現分離效果的情況。亦即，一旦包含在剝離層6 2 內的成分成爲氣體而被放出，剝離層62吸收光而在瞬 間成爲氣體，該蒸氣被放出而對分離有貢獻。如此的剝離 層6 2的組成，例如有以下A〜F所記載的。 (A)非晶質5夕（a-Si) 在此非晶質砂中，也可以含有氫（Η ) ◦此情況’ Η 的含 量理想爲2原子％以上的程度，更理想爲2〜2 0原子 %程度。 (Β )氧化矽或矽化合物、氧化鈦或鈦酸化合物、氧 化鉻或鍩酸化合物、氧化鑭或鑭酸化合物等的各種氧化物 陶瓷、電介質（強電介質）或半導體。 (C ) PZT、PLZT、PLLT、ΡΒΖΤ等的陶瓷或電介質 (強電.介質）。 (D )氮化矽、氮化鋁、氮化鈦等的氮化物陶瓷。 (Ε )有機高分子材料 作爲有機高分子材料，只要是具有—CH-、一 CO-(酮）、—CONH—(醯胺基）、一 ΝΗ -（亞氨基）、 —C〇〇—(酯）、—Ν = Ν—(偶氮基）、—CH = N—(席 夫）等的結合（藉由光照射，這些結合被切斷）者，特別 是具有多數這些結合者，不論爲何者皆可。又，有機高分 子材料，也可以爲在其構造式中，具有芳香族碳化氫（1 -26- (24) 1230445 或2以上的苯環或其縮合環）者。 作爲如此的有機高分子材料的具體例，例如有：聚乙 嫌、聚丙烯之類的聚烯、聚醯亞胺、聚醯胺、聚酯、聚甲 基丙烯酸甲酯（PMMA )、聚伸苯基硫（PPS )、聚醚硕 、環氧樹脂等。 (F )金屬。 作爲金屬，例如有：Al、Li、Ti、Mn、In、Sll、γ、The present invention is an electronic device using the photovoltaic device of the present invention as a display unit. Here, the electronic device includes: a video camera, a mobile phone, a personal computer, a portable information terminal device (that is, P D A), or various other electronic devices. By using the photovoltaic device of the present invention, it is possible to improve the performance of the electronic device, the cost, and the durability. [Embodiment] (Embodiment of the present invention) Hereinafter, a thin film transistor -12- (10) 1230445 bulk driving type display device according to an embodiment of the present invention will be described. In this embodiment, as an example of a thin-film transistor-driven display device, an organic EL display device composed of an organic EL element, which is a type including a photovoltaic element, will be described. Fig. 1 is a diagram schematically showing the configuration of the organic EL display device of this embodiment. The organic EL display device 100 shown in the figure is formed by arranging a plurality of pixels (basic pixels) 1 1 including three color pixels 1, 2, and 3 in a matrix. For each color pixel, for example, color pixel 1 is red, color pixel 2 is green, and color pixel 3 is blue. A pixel having a driving circuit (thin film circuit) including a plurality of thin film transistors (TFTs) is used to drive each pixel 10 and 1. Fig. 2 is a diagram illustrating the structure of the pixel 101. Fig. 2 (a) is a plan view showing pixel 101, and Fig. 2 (b) is an AA / section view in Fig. 2 (a). In addition, in Fig. 2 (a), for convenience of explanation, a part of constituent elements is omitted and shown. As shown in FIG. 2, the pixel 1 01 is placed on a substrate 10 made of an insulating material such as glass, and the first wiring layer 1 2 and the second wiring layer 1 4 are sequentially laminated from the lower layer side. And a light-emitting element layer 16. In addition, in FIG. 2 (a), in order to explain the structure of the first and second wiring layers, a part of the second wiring layer 14 and the light-emitting element layer 16 are omitted and the first wiring layer 1 is added. 2. The system is configured to include wiring 20 formed on the substrate 10 ′, and to provide electrical connection between the wiring 20 and wiring (described later) included in the second wiring layer 14.的 口 部 22。 The opening portion 22. Via this opening 22, the wiring contained in the second wiring layer 14 is made. • 13-1230445 (11) Each wire element, 34 soldering) 10 each of the provincial layer body 40 42 Protective ground and wiring 20 abutment to seek electrical connection between the two. In addition, an insulating member (for example, silicon oxide) is formed between the wirings 20. Furthermore, in Fig. 2 (a), the insulating member is omitted. The second wiring layer 14 is composed of: a wiring 3 formed on the first distribution layer 12; an electrode for including this wiring 30; and an electrode included in the light emitting layer 16 (described later). A plug 3 2 electrically connected between the wafer 3 4 for driving the light emitting element layer 16 and a pad composed of a plurality of pad electrodes 36 for electrically connecting the wafer and the wiring 30. Group 38. In addition, although the illustration is omitted in FIG. 2 (a), an insulating member (for example, silicon oxide, etc.) is formed between each of the wires 30, the plug 32, and the like. Furthermore, in FIG. 2 (a), Although the wafer 34 is also shown briefly, the wafer 34 is formed on the pad group 38. In this embodiment, the wafer 34 is formed by the first wiring layer 12 and the second wiring 14. Circuit wiring. In addition, the wafer 34 is composed of a plurality of thin-film transistors; it has the function of independently controlling the color pixels 1, 2, and 3 included in one pixel 1 0. The wafer 34 is formed. On another substrate (transfer source substrate) different from the substrate, it is peeled off from the transfer source plate and transferred to the substrate 10. Furthermore, the wafer 34 corresponds to the transfer wafer. " The details of the printing method will be described later. The light-emitting element layer 16 is composed of three pixel electrodes 40 formed on the second distribution layer 14 and a common electrode 42 arranged to face the pixel electrodes. Three light-emitting layers 44 between each pixel electrode 40 and a common electrode, and a protective layer 46 formed on the common electrode 42. Also, Between each pixel electrode 40 or each light-emitting layer 44, etc., -14-1230445 (12) forms an insulating member (such as oxide sand). Each light-emitting layer 44 on which each pixel electric layer is formed, and The common electrode 42 is a shape element (photoelectric element); each light-emitting element is composed of elements 1, 2, and 3. According to the above-mentioned wafer 34, each pixel I is capable of supplying electricity to each light-emitting layer 44 independently. The color pixels 1, 2, and 3 are independently turned on and off. Next, a structure example of the wafer 34 of this embodiment will be described in detail. FIG. 3 is a plan view showing the internal structure of the wafer 34, so that It is easy to understand the structure of the (TFT) or thin film wiring included in the wafer 34, and the constituent elements on the top surface where transistors and the like are provided are omitted. The elements in the illustration will be explained later. No. The wafer 34 is composed of: three switching thin-film transistors ST1 formed in the right region; and three drivers DTI, DT2, and DT3 formed in the left region side by side. In this embodiment, About a color pixel, is the switch The film transistor and a driving thin film transistor are combined to form a pixel circuit for driving. Specifically, the film transistor ST 1 shown in FIG. 3 operates in response to the input signal (scanning signal) and the transistor DT 1. The film transistor is driven. Crystal DT 1, the current flowing in the light-emitting layer 44 of the color-controlling pixel 1. Similarly, the thin-film transistor ST2 and the driving thin-film transistor DT2 are added to the pole 40 and the product is 3 to emit light into each color and draw 1 pole 4 0. The source is shown as a specific figure. The third thin-film transistor is arranged above and below these omitted structures, and the ground, ST2, and ST3 moving thin-film transistors are made of a driving thin-film driven by a combination of the shown thin switches. In the composition, a pixel circuit of -15- (13) 1230445 is combined to control the current flowing in the light-emitting layer 4 4 constituting the color pixel 2. The pixel circuit formed by combining the switching thin-film transistor S T 3 and the driving thin-film transistor DT3 controls the current flowing in the light-emitting layer 4 4 constituting the color pixel 3. Each of the above-mentioned switching thin-film transistors and each driving thin-film transistor includes a semiconductor film for forming a first thin-film wiring layer, an active region of the thin-film transistor, and the like; the structure includes a semiconductor layer formed on the first thin-film wiring layer And a second thin film wiring layer formed on the semiconductor layer. In Figure 3, in order to clearly show the difference between the layers, the first thin-film wiring layer is reversed, the semiconductor layer has been thickly shaded from the bottom right, and the second thin-film wiring layer has been shaded from the previous right. To show it. In addition, an insulating layer made of Si O 2 or the like is formed between the layers. Next, the structures of the first thin film wiring layer, the semiconductor layer, and the second thin film wiring layer will be described in detail with reference to FIG. 3, respectively. The first thin film wiring layer system is configured to include thin film wiring 50 a to 50 d. The thin film wiring 50a also serves as a gate electrode of each switching thin film transistor ST1, ST2, and ST3, and is electrically connected to the thin film wiring 54a included in the second thin film wiring layer. This thin film wiring 50a can control the operation of each of the switching thin film transistors ST1, ST2, and ST3 by supplying a scanning signal through the thin film wiring 54a. Although the illustration of the thin film wiring 54a is omitted in FIG. 3, it is actually electrically connected to a pad electrode (a connection terminal serving as an electrical connection) provided on the upper side of the second thin film wiring layer; via this pad electrode The scanning signal is transmitted from the outer periphery of the wafer 3 4 to the thin film wiring 5 4 a. Details of pad electrode -16- 1230445 (14) pole will be described later. In this embodiment, 'the scan signal is supplied to the switching thin-film transistors ST1, ST2, and wiring in this way, and a common wild line is formed to reduce the area required for the formation of the thin-film wiring layer.' At the same time, the amount of pad power is reduced, and the size of the wafer 34 is reduced. Furthermore, 'the electric charge (i.e., the connection point) is reduced by the pad', there is less chance of poor contact during transfer. The thin film wiring 5 0 b is electrically connected to the semiconductor film 5 2 a; it is responsible for transmitting the current supplied by the switching thin film transistor s τ 1 to the function of driving the thin film transistor DT1, and also serves as the pole of the driving thin film transistor DT1. The thin film wiring 5 0 c is electrically connected to the semiconductor film 52 b via the second thin film wiring layer film wiring 54 d. The thin film wiring 5 0 c serves to transmit the current supplied from the film transistor ST2 to the driving thin film transistor, and also serves as a thin film transistor. The gate thin film wiring 50d of the driving thin film transistor DT2 is electrically connected to the semiconductor film 52c; it is responsible for the current supplied by the switching thin film transistor S T3 and transmits the function to the driving thin film DT3, and also serves as the pole of the driving thin film transistor DT3. . The semiconductor layer system is configured to include semiconductor films 52a to 52k. The film 5 2a has one end side connected to the thin film wiring 54b and the other end connected to the wiring 50b. The active semiconductor film 5 2 b 'which serves as the switching thin film transistor ST1 is connected to the thin film wiring 5 4 c at one end and to the thin film wiring. 54d connection, while serving as the switching thin film transistor ST2, the number of poles used for the first pole of ST3 is also changed from the thin-switch thin-body DT2 pole from the transistor gate. Residual transistors, gate electrodes, semiconductors, and thin film regions. At one end is the active -17-1230445 (15) region. One end of the semiconductor film 52c is connected to the thin film wiring 54e, and the other end is connected to the thin film wiring 50d, and serves as an active region of the switching thin film transistor ST3. The semiconductor film 52d is connected to the thin film wirings 54g and 54f, respectively, and also connected to a pad electrode (not shown here) described later, and serves as an active region for driving the thin film transistor DT1. The semiconductor film 52e is connected to the thin film wirings 54h and 54i, respectively, and also connected to a pad electrode (not shown here) described later, and serves as an active region for driving the thin film transistor DT2. The semiconductor film 52f is connected to the thin film wirings 54j and 54k, respectively, and also connected to a pad electrode (not shown here) described later, and serves as an active region for driving the thin film transistor DT3. The semiconductor film 52g is formed on the lower layer of the thin film wiring 54c, and is used to adjust the height of the pad electrode formed on the upper layer of the thin film wiring 54c. Similarly, the semiconductor film 52h is formed on the lower layer of the thin film wiring 54e, and is used to adjust the height of the pad electrode formed on the upper layer of the thin film wiring 54e. The same applies to the semiconductor films 5 2 i, 5 2 j, and 5 2 k, and is used to adjust the height of the pad electrodes formed on the thin film wirings 5 4 b, 5 4 a, and 5 4 k. The details of the pad electrode (especially how to specify the "height" of the pad electrode) will be described later. Thus, in this embodiment, when a semiconductor film serving as an active region of a thin film transistor is formed, a semiconductor film for adjusting the height of a pad electrode is formed at once, that is, a "height adjustment film" is formed. Accordingly, it is possible to adjust the height of the pad electrode appropriately without causing an increase in the manufacturing process or complication. Furthermore, in addition to the case of using a semiconductor film -18-1230445 (16) ', a thin film wiring or an insulating film may be used to form the height adjustment film. The second thin film wiring layer is configured to include thin film wirings 54a to 54k. Here, the connection relationship between the pad electrodes that are formed on the upper side of the second thin film wiring layer and serve as an electrical connection between the internal circuits of the wafer 34 and the outside will be described with the thin film wirings 54a to 54k. Fig. 4 is a diagram illustrating a pad electrode. As shown in the figure, on the upper side of the second thin film wiring layer of the wafer 34, 10 pad electrodes 5 6 a to 5 6j are provided. These pad electrodes 56a to 5j are configured to correspond to each of the pad electrodes 36 (see Fig. 2) included in the above-mentioned pixel 101. The wafer 34 shown in FIG. 4 is reversed, and each pad electrode 56a, etc. is compared with each pad of the pad group 38 included in the pixel 101 described in FIG. 2 described above. The electrodes 36 are bonded face to face, and the wafer 3 4 is transferred. The method of transferring the wafer 34 will be described in detail later. The pad electrode 56a is electrically connected to the thin film wiring 54a through an opening 55a in an insulating film formed on the second thin film wiring. The scan signal is supplied from the outside to the thin film wiring 54a via the pad electrode 56a, thereby driving the switching thin film transistors ST1 to ST3. The pad electrode 56b is electrically connected to the thin film wiring 54b via an opening 55b in an insulating film formed on the thin film wiring 54b. Current is supplied from the outside to the thin film wiring 54b via this pad electrode 56b to supply the current to the active area of the switching thin film transistor ST1. The pad electrode 5 6 c is electrically connected to the thin film wiring 5 4 c via an opening 5 5 c in the insulating film formed on the thin film wiring 5 4 c. A current is supplied from the outside to the thin film wiring 54c via this pad electrode 56c to supply a current to the active region of the switching thin film transistor ST2. The pad electrode 56d, -19-1230445 (17) is electrically connected to the thin film wiring 54e via an opening 55d in an insulating film formed on the thin film wiring 54e. A current is supplied from the outside to the thin film wiring 54e via this pad electrode 56d to supply the current to the active region of the switching thin film transistor S T 3. The pad electrode 5 6 e is electrically connected to the thin film wiring 5 4 f via an opening 5 5 e in the insulating film formed on the thin film wiring 5 4 f. A current is supplied from the outside to the thin film wiring 54f via this pad electrode 56e to supply the current to the active region of the thin film transistor DT1. The pad electrode 56f is electrically connected to the thin film wiring 54g through an opening 55f in an insulating film formed on the thin film wiring 54g. This pad electrode 56e is electrically connected to one of the pad electrodes 36 described above. The current output from the driving thin film transistor DT1 is supplied to the color pixel 1 via the thin film wiring 54g, the pad electrode 56f, and the pad electrode 36 which is electrically connected to the pad electrode 56f. 56 g of pad electrodes are electrically connected to the thin film wiring 54 h via the opening 5 5 g in the insulating film formed on the thin film wiring 54 h. A current is supplied from the outside to the thin film wiring 54h via this pad electrode 56g to supply the current to the active region of the thin film transistor DT2. The pad electrode 56h is electrically connected to the thin film wiring 54i via an opening 55h in an insulating film formed on the thin film wiring 54i. This pad electrode 56h is electrically connected to one of the pad electrodes 36 described above. The current output from the driving thin film transistor DT2 is supplied to the color pixel 2 via the thin film wiring 54i, the pad electrode 56h, and the pad electrode 36 which is electrically connected to the pad electrode 56h. The pad electrode 56i is electrically connected to the thin film wiring 5 4 j via an opening 5 5 i in the insulating film formed on the thin film wiring 54j. The current is supplied to the thin film wiring 5 4 j from the outside via this -20-1230445 (18) pad electrode 5 6 i to supply the current to the active area of the thin film transistor DT3. The pad electrode 5 6j is electrically connected to the thin film wiring 54k through an opening 5 5j in the insulating film formed on the thin film wiring 54k. This pad electrode 56j is electrically connected to one of the pad electrodes 36 described above. The current output from the driving thin-film transistor DT3 is supplied to the color pixel 3 via the thin-film wiring 54k 'pad electrode 56i and the pad electrode 36 which is electrically connected to the pad electrode 56i. Next, the height of each of the pad electrodes 56a to 56j provided on the wafer 34 will be described. FIG. 5 is a diagram illustrating the height of the pad electrode. Specifically, Fig. 5 (a) is a cross-sectional view of the pad electrode 56d when viewed from the B-β / direction shown in Figs. 3 and 4; Fig. 5 (b) is a view from Cross-sectional views of the pad electrode 56f viewed in the C-C / direction shown in FIGS. 3 and 4. As shown in FIG. 5 (a), the pad electrode 5 6 d has two portions having the highest height (distance from the bottom surface) of the wafer 34, that is, the "highest portion". Further, the localities of the two highest portions 56d-1 and 56d-2 from the bottom surface of the wafer 34 are L1. Further, as shown in FIG. 5 (b), the pad electrode 5 6 f has one highest portion 5 6 f-1; the height of the highest portion 56 f-1 from the bottom surface of the wafer 34 is L1. Further, the other pad electrodes 5 6 a and the like (not shown) each have at least one portion having the highest height from the bottom surface of the wafer 34 as li. That is, the plurality of pad electrodes 5 6 a to 5 6 j are formed on the top surface of a thin film circuit formed by laminating a thin film wiring layer or a semiconductor layer, etc.-21-(19) 1230445. Specifically, the contact surfaces between the pad electrodes 36) arranged oppositely are not flat. Therefore, in this embodiment, 'each pad electrode has at least one highest portion, and these pad electrode systems are formed so that the height of the highest portion is approximately the same L 1 ° so' In order to make the highest portion of the highest portion It is adjusted to be approximately the same as L1 ', and a semiconductor film (or an insulating film or the like) which is not directly related to the configuration of the thin film circuit is appropriately formed as a height adjustment film. In addition, the plurality of pad electrodes 56a to 56j each have the same film structure of the laminated film in the region corresponding to the highest portion. Furthermore, in the example shown in FIG. 5, the bottom surface of the wafer 34 is used as the "reference surface" to define the height L1 of each highest portion; however, the reference surface is not limited to this, as long as it can be used as a common Other reference planes (for example, a formation surface of a thin film wiring 50 a and the like or a formation surface of a semiconductor film 5 2 e and the like) may be used as the reference surface. Next, the pad electrodes 5 6 a to 5 6 j formed in the wafer 34 and the plurality of pads formed in each of the day elements 101 in a one-to-one correspondence will be described in detail. Electrode 3 6. Fig. 6 and Fig. 7 are diagrams showing the pad electrodes 36 formed in the pixel 101. FIG. 6 is an enlarged view of a region including the pad electrode 36 in the pixel 101 shown in FIG. 2. Here, considering the convenience of description ', in order to make the difference between the pad electrodes 36 easier, the pad electrodes 3 6 a to 3 6 j are replaced by symbols. Each pad electrode 3 6 a to 3 6 j corresponds to each pad electrode 5 6 a to 5 6 j on the wafer 34. Fig. 7 (a) is a cross-sectional view of the table τκ viewed from the D-direction shown in Fig. 6 on the pad electric-22-1230445 (20) pole 3 6d; Fig. 7 (b) shows A cross-sectional view of the pad electrode 3 6 f viewed from the E-E > direction shown in FIG. 7 is shown in FIG. 7 (a), and the pad electrode 36 d has the bottom surface of the substrate 10 with the pixel 101 at two places. The highest height is the "most round of points". In addition, the heights of the two highest portions 36d-12 from the bottom surface of the substrate 10 are L2, respectively. As shown in FIG. 7 (b), the pad electrode 36f has two highest portions 51, 36f-2, and the positions of the partial portions 36f-1, 36f-2. Further, regarding other pads (not shown) The electrodes 3 6 a and so on each have the highest portion of the height L2 from the bottom surface of the substrate 10 at one point: that is, the plurality of pad electrodes 36 a to 36 j are formed by forming a wire layer or an insulating layer, etc. The contact surface between the top surface of the circuit wiring formed by the lamination and the outside (specifically, the pad electrodes 5 6 a and the like disposed opposite to each other are non-flat. Therefore, in this embodiment, each solder has at least one place. The height of these pad electrodes is almost the same as the height of the highest portion of L2. Also, the plurality of electrodes 3 6a to 3 6j, each of which corresponds to the structure of the accumulated film in the region of the highest portion, is the same. In the example shown in FIG. 7, although the film is not specifically adjusted, there is a need depending on the formation position of the pad electrode. In this case, in order to adjust the height of the highest part, the same as L2 It is also possible to have no straight insulation for the structure of circuit wiring As a height adjustment film, it is appropriately formed. The method is the same as in the case of the pad electrode 56a (refer to FIG. 5 and FIG. 6) from the forming part, 36d — again, as > 36f- is L2 There are at least points. In the future, so) the formation of pad electrodes between the pads and the arrangement of the pad film is important (the general relationship is specific) is the same as -23-1230445 (21). The wafer 34 of this embodiment has the above-mentioned structure. Next, a method for manufacturing the organic EL display device of this embodiment will be described. In this embodiment, a plurality of wafers 34 are formed on a transfer source substrate in advance, and then the wafer 34 is peeled off from the first substrate and transferred to a substrate constituting an organic EL display device. Transfer technology. 8 and 9 are diagrams illustrating a manufacturing method according to this embodiment. This transfer method includes the first to fifth processes described below. < First process > In the first process, as shown in FIG. 8 (a), a release layer (light absorbing layer) 62 is formed on the transfer source substrate 60. The transfer source substrate 60 is preferably one having a light-transmitting property. According to this, light can be irradiated to the peeling layer through the transfer source substrate, and the light can be used to accurately and quickly peel the peeling layer. In this case, the light transmittance is preferably 10% or more, and more preferably 50% or more. This is because the higher the light transmittance, the less the attenuation (loss) of light, and the peeling layer 62 can be peeled with a smaller amount of light. The transfer source substrate 60 is preferably formed of a highly reliable material, and is particularly preferably formed of a material having excellent heat resistance. The reason is that, for example, when forming a wafer 34 as a transfer target, the process temperature may increase depending on the type or the formation method (for example, about 3500 to 100 ° C), even in this case. If the transfer source substrate 60 is excellent in heat resistance, when the wafer 34 is formed on the transfer source substrate 60, the temperature setting range of -24-1230445 (22) and other film forming conditions are set in a wide range. When manufacturing a large number of wafers, it is possible to manufacture high-performance elements with high reliability. Therefore, when the temperature of the transfer source substrate 60 is Tm ax, it is desirable to be configured with strain. Specifically, the transfer source substrate point is preferably 350 ° C or more, and more preferably, such as quartz glass, Corning 709, and heat-resistant glass. The thickness of the transfer source substrate 60 is usually preferably 0.1 to 5.0 mm, and the thicker the thickness of the source substrate 60, the higher the strength and the lower the transmittance of the substrate 60. Furthermore, the thickness of the transfer source substrate 60 may exceed the aforementioned upper limit 値. In addition, the thickness of the transfer source substrate 60 is not limited. Although the transfer source substrate has such a substrate and is used as a transfer target for the final product, even if it is used at a higher price, the increase in manufacturing cost can be reduced. The peeling layer 62 has the following characteristics: peeling occurs at the interface of absorption (hereinafter referred to as "in-layer properties; ideally: by light irradiation, the bonding force between atoms or molecules disappears; High temperature processing, energy devices or circuit temples. The material with the highest point at the time of forming the wafer 34 is T ma X or more. The material is 60, and the strain is 50 CTC or more. This kind of material is equivalent to the electrical glass OA-2. Although there is no particular limitation, I is 0 · 5 ~ 1 · 5 mm. When the transfer is increased, the thinner the light transmittance is, the lower the light source is, which is less likely to cause light attenuation. Can be uniformly irradiated 丨 I want to be uniform. Various conditions, but the transfer source substrate is different, because of the repetitive material, due to repeated use of light, and within the layer and / or peeling "," Interface peeling " Reduction of the material of the release layer 62, that is, detachment occurs to reach -25-1230445 (23) In-layer peeling and / or interface peeling. Furthermore, there is a case where a separation effect is found by emitting gas' from the release layer 62 by irradiation with light. That is, once the components contained in the release layer 6 2 are released as a gas, the release layer 62 absorbs light and becomes a gas instantly, and the vapor is released to contribute to separation. The composition of such a release layer 62 is as described in A to F below. (A) Amorphous (a-Si) Amorphous sand may contain hydrogen (Η) ◦ In this case, the content of Η is preferably about 2 atomic% or more, and more preferably 2 to 2 0 atomic% degree. (B) Various oxides such as silicon oxide or silicon compound, titanium oxide or titanate compound, chromium oxide or gallate compound, lanthanum oxide or lanthanate compound, ceramics, dielectric (ferroelectric) or semiconductor. (C) Ceramics or dielectrics (ferroelectric. Dielectrics) such as PZT, PLZT, PLLT, PBZT, etc. (D) Nitride ceramics such as silicon nitride, aluminum nitride, and titanium nitride. (E) Organic polymer materials As organic polymer materials, as long as they have —CH—, —CO— (ketone), —CONH— (amido), —N— (imino), —C〇〇— ( Esters), —N = Ν— (azo), —CH = N— (Schiff), etc. (these bonds are cut off by light irradiation), especially those who have the majority of these bonds, whatever Anyone can. In addition, the organic polymer material may be an aromatic hydrocarbon (1 -26- (24) 1230445 or more benzene ring or a condensed ring thereof) in its structural formula. Specific examples of such an organic polymer material include polyethylene, polyethylene, polypropylene, polyimide, polyimide, polyester, polymethyl methacrylate (PMMA), and polystyrene. Phenyl sulfur (PPS), polyether master, epoxy resin, etc. (F) Metal. Examples of metals include: Al, Li, Ti, Mn, In, Sll, γ,

La、La,

Ce、Nd、Pr、Gd、Sm或至少含有這些金屬的至少一 種以上的合金。其他，也能夠利用含有氫的合金來構成剝 離層。剝離層使用含有氫的合金之情況，伴隨著光的照射 ，氫被釋放出來，依此可以促進剝離層中的剝離。 又，也可以利用含有氮的合金來構成。離層使用含有 氮的合金之情況，伴隨著光的照射，氮被釋放出來，依此 可以促進剝離層中的剝離。進而，也可以將剝離層作成多 層膜。多層膜例如可以做成由非晶質矽膜和被形成在其上 的金屬膜所構成。作爲多層膜的材料，也能夠由上述陶瓷 、金屬、有機局分子材料的至少一種來構成。 剝離層6 2的形成方法，並沒有特別地限制，可以根 據膜的組成或膜厚等的條件，加以適當地形成。例如有： CVD、濺鍍等的各種氣相成膜法、各種電鍍法、旋轉塗佈 等的塗佈法、各種印刷法、轉印法、噴墨塗覆法、粉末噴 射法等，也可以組合2種以上這些方法來形成。 再者’雖然在第8圖（a )沒有圖示出來，根據轉印 -27- (25) 1230445 來源基板60和剝離層62的性質’也可以在轉印來源基板 6 〇和剝離層6 2之間’設置以提局兩者的密者性爲目的之 中間層。此中間層’例如在製造時或使用時’係用來發揮 :對被轉印層加以物理的或化學的保護之保護層' 絕緣層 、阻止往被轉印層或從被轉印層開始之成分的移動（遷移 )之障壁層、及反射層之至少一種機能。 <第2製程> 接著，說明第2製程。第2製程如第8圖（b )所示 ，在剝離層6 2上，形成複數個晶片3 4。將由複數個晶片 3 4所構成的層，稱爲被轉印層6 4。 在薄膜電晶體等的製造中，要求一定程度的高溫製程 ，因而形成薄膜電晶體等的基材，需要如轉印來源基板般 地滿足各種條件。在本實施形態的製造方法中，由於利用 滿足各種製造條件的轉印來源基板來製造薄膜電晶體等， 所以可以將薄膜電晶體等，轉印至沒有滿足此製造條件之 最終基板上。亦即，在本實施形態的製造方法中，作爲最 終基板’具有：能夠使用由較廉價的材料所構成的基板， 而擁有可以降低製造成本之優點；或是可以使用具可撓性 之撓性基板等’而具有使得最終基板的選擇範圍變廣等的 優點。 在此，說明關於被轉印層6 4中的各晶片3 4之分離。 作爲各晶片3 4的分離方法，可以考慮：藉由蝕刻等將各 個晶片3 4分離的方法；僅使剝離層分離的方法；以及藉 -28- 1230445 (26) ώ將特定的構造形成在轉印來源基板上，使各個被轉印體 容易分離等的方法◦在此，說明將各個晶片3 4完全地分 離之方法。 如第8圖（c )所示，爲了將各晶片3 4各自地分離， 在相當於晶片3 4區域的外周，藉由濕式蝕刻或乾式鈾刻 等’形成成爲凹部構造的溝62c，使各晶片34殘留成島 狀。此溝62c，在基板的厚度方向，係將被轉印層64的 全部及剝離層62的全部（參照第8圖（c ))或一部份（ 參照第8圖（d ))加以切除。此切除也可以比被轉印層 64爲淺。此溝62c，除了如第8圖（d )所示地鈾刻至剝 離層62的一部份而形成以外；也可以如第8圖（c )所示 地將剝離層62完全地蝕刻而將各晶片3 4和位於其正下方 的剝離層62，以相同的形狀之狀態，殘留成島狀。藉由 形成相同的晶片3 4，然後以相等的節距進行蝕刻來將被 轉印體並排地配置在轉印來源基板6 0上，在剝離製程（ 後述的第4和第5製程）中，可以容易地僅轉印所希望的 晶片3 4。 藉由預先切除被轉印層64，可以將剝離體的一部份 ，延著其區域的形狀，完全地剝離；在該區域剝離時，可 以防止被破壞。又，伴隨著剝離之被轉印層6 4的破壞， 可以做成不會及於鄰接區域。又，藉由往膜厚方向預先地 切除，即便用來將特定的晶片3 4接合在轉印對象基材上 的接著層的接合力弱的情況，也可以做成將晶片3 4剝離 。又，由於成爲轉印對象的區域之外觀明確，基板間的轉 -29- 1230445 (27) 印時的定位變容易。 再者，如第8圖（e )所示，也可以進行過蝕，使得 剝離層62與晶片3 4之接著面積’比被轉印體的剝離層接 合面的全部面積小。藉由如此地將剝離層6 2過触刻，由 於剝離層的面積變小，所以將光照射在剝離層6 2上來進 行剝離時，除了以較少的力便能夠確實地剝離以外，藉由 縮小剝離層62，能夠減少剝離塒所需要的光能量。 進而，如第8圖（d )所示，也可以僅蝕刻被轉印層 > 6 4而預先形成溝6 2 c，而使剝離層，6 2以連續的狀態殘留 。由於若能夠對形成有晶片3 4之區域沒有遺漏地賦予能 量，則能夠在此區域的剝離層62確實地產生剝離，所以 即使剝離層62本身沒有設置裂縫，也可以僅使所希望的 被轉印體剝離。 <第3製程> 接著，如第9圖（a )所示，藉由將轉印來源基板6 0 之晶片3 4的形成側的面、及轉印對象基板6 6之轉印晶片 3 4側的面，一邊對準一邊重合，並根據需要施加按壓力 ，僅使應該轉印的晶片3 4，經由具有導電性的接著層6 8 ，選擇地接合在轉印對象基板66側。 在此，在本實施形態中，將第i配線層！ 2形成在上 述基板1 0上，在該第1配線層丨2上形成有配線3 0和焊 墊電極3 6的狀態者（參照第2圖），相當於第9圖（a ) 所不的轉印對象基板66。而且，使被包含在此轉印對象 -30- 1230445 (28) 基板6 6中的各焊墊電極3 6、及被設置在成爲轉印對象的 晶片34中之各焊墊電極56a等，互相抵接來進行晶片34 的貼合。 作爲構成上述接著層6 8的接著劑之適當例，例如有 :反應硬化型接著劑、熱硬化型接著劑、紫外線硬化型接 著劑等的光硬化型接著劑、嫌氣硬化型接著劑等的各種硬 化型接著劑。接著劑的組成’例如可以爲··環氧系、丙烯 酸酯系、聚矽氧烷系等。又’使用一般市面所販賣的接著 劑時，也可以藉由將適當的溶劑添加在要使用的接著劑中 ，調出適宜塗佈的黏度。 在本實施形態中，接著層6 8僅形成在應該轉印的晶 片3 4上、或是僅形成在對應應該轉印的晶片3 4之轉印對 象基板66上。如此的接著層6 8的局部形成，能夠應用各 種印刷法或液體吐出法來實施。液體吐出法中，有利用壓 電體的變形來吐出液體之壓電噴射法、或是利用熱來產生 氣泡來使液體吐出的方法。在本實施形態中，例示使用噴 墨塗覆（液體吐出）法之接著層6 8的形成。 再者，如第1 〇圖所示，也可以使用由包含導電性粒 子所構成的異方性導電膜，來形成接著層6 9。此情況， 由於不需要對各個焊墊電極設置個別的接著層，所以定位 精度沒有如此地要求，具有接著層的形成變容易的優點。 <第4製程> 接著，如第9圖（b )所示，從轉印來源基板6 0和轉 -31 - 1230445 (29) 印對象基板66兩者的接合體之轉印來源基板60側 僅對應該轉印的晶片3 4的剝離層6 2，選擇地照射 僅在支持著晶片34之剝離層62，產生剝離（層內 /或界面剝離）。 剝離層6 2的層內剝離及/或界面剝離之產生 有在剝離層62的構成材料中產生脫離；或是被包 離層62中的氣體的放出；進而有藉由在照射之後 的熔融、蒸散等的相變化等的原理。 在此，所謂的脫離，係指：吸收照射光的固定 剝離層6 2的構成材料），激發出光化學或熱反應 其表面或內部的原子或分子的結合被切斷而放出者 係出現剝離層6 2的構成材料的全部或一部份發生 蒸故（氣化）等的相變化之現象。又，也有根據前 化，變成微小的氣泡，使結合力變小者。 剝離層6 2發生層內剝離、界面剝離或是發生 種剝離’係受到剝離層62的組成或其他各種原因 ;作爲其原因之一，舉例而言，有照射光的種類、 強度、到達深度等的條件。 作爲照射光L，只要能夠在剝離層62中產生 離及/或界面剝離便可以；例如X光、紫外線、 、紅外線、雷射光等。 其中，根據使剝離層62的剝離（脫離）容易 可以高精度地局部照射方面來考量，雷射光係理想 種雷射光，理想爲具有波長100nm〜35〇nm的雷射 ，藉由 光L， 剝離及 原理， 含在剝 所產生 材料（ ，而在 ;主要 熔融、 述相變 前述兩 所影響 波長、 層內剝 可見光 產生且 的。此 光。藉 -32- 1230445 (30) 由使用如此的短波長雷射光，可以提高光照射精度，同時 能夠有效地進行剝離層62的剝離。 作爲產生如此的雷射光的雷射裝置，使用準分子雷射 是適當的◦準分子雷射，由於在短波長區域，輸出高能量 ，所以能夠在極短的時間內，於剝離層62中產生脫離； 因此，相鄰的轉印對象基板66或第1基板60等，溫度幾 乎不會上升，晶片3 4等不會發生劣化、損傷，便能夠使 剝離層62剝離。 或者，例如使剝離層62發生氣體放出、氣化、昇華 等的相變化，而賦予分離特性時，所照射的雷射光的波長 ，理想爲3 5 0nm〜1 200nm程度。如此波長的雷射光，能 夠使用在YAG、氣體雷射等的一般加工領域中被廣泛使 用的雷射光源或照射裝置等；能夠價廉且簡單地進行光照 射。又，藉由使用如此的可見光區域的波長之雷射光，轉 印來源基板6 0只要具有可見光透光性即可，能夠使轉印 來源基板60的選擇之自由度變廣。 又，所照射的雷射光之能量密度、特別是準分子雷射 的情況之能量密度，理想爲10〜5 000mJ/cm2程度，更理 想爲 1 00〜5 00 mJ/ cm2程度。又，照射時間理想爲1〜 lOOOnsec程度，更理想爲10〜lOOnsec。能量密度越高或 照射時間越長，容易產生脫離％;另一*方面’能量密度越 低或照射時間越短，則可以降低由於透過剝離層62的照 射光，對晶片3 4等所造成的不良影響之可能性。 -33- 60 1230445 (31) <第5製程> 接著，如第9圖（c )所示’藉由對轉印來源基板 和轉印對象基板6 6，施加使兩者分開的力’將轉印來 基板6 0從轉印對象基板6 6卸下。藉由前述第4製程而 該轉印至轉印對象基板6 6上的晶片3 4之剝離層6 2 ’ 於從晶片3 4剝離，所以這些應該轉印的晶片3 4 ’與第 基板6 0側切斷。又，應該轉印的晶片3 4，藉由接著層 而與轉印對象基板66接合。 再者，在前述第4製程中，雖然希望剝離層62發 完全地剝離，但是應該轉印之晶片3 4的接著層6 8的接 強度，比將要殘留的剝離層6 2所產生的接合力強’結 在使轉印來源基板6 0和轉印對象基板6 6分離時’若應 轉印的晶片3 4確實地轉印至轉印對象基板6 6側的話， 即使僅剝離層6 2的一部份剝離也可以。 如此的被轉印體的轉印，係根據利用剝離層的剝離 弱化的剝離層的結合力、及應用於被轉印體之接著層的 合力之相對的力關係來決定。若剝離層所產生的剝離充 ，則接著層的結合力即使弱，被轉印體的轉印也是可能 ;相反的，剝離層所產生的剝離即使不充分，若接著層 結合力高，則可以將被轉印體加以轉印。 如第9圖（c )所示，藉由將轉印來源基板6 0從轉 對象基板66分開，晶片34被轉印至轉印對象基板66 的規定位置。然後’藉由形成覆蓋晶片3 4等的絕緣膜 ，形成第2圖所示的第2配線層1 4而完成電路基板； 源 應 由 1 68 生 著 果 該 則 而 結 分 的 的 印 上 等 進 -34- 1230445 (32) 而，藉由在第2配線層1 4上形成發光元件層1 6，形成有 機EL顯示裝置1〇〇。 再者，被轉印至轉印對象基板6 6上的晶片3 4，會有 附著剝離層62的殘留部份之情況，希望將其完全地除去 。用來除去殘留的剝離層6 2的方法，例如洗淨、蝕刻、 灰化、硏磨等的方法；或是從將這些加以組合的方法中， 適當地加以選擇來採用。 同樣的，在完成晶片3 4的轉印之轉印來源基板6 〇的 表面，附著有剝離層62的剝離殘留時，能夠以與前述轉 印對象基板6 6相同的方法，加以除去。依此，能夠將轉 印來源基板60再利用（再循環）。藉由如此地再利用轉 印來源基板60，能夠節省製造成本。這對於使用由石英 玻璃般的高價材料、稀少材料所構成的轉印來源基板60 之情況，特別有用。 如此，在本實施形態中，關於分別設置在晶片3 4側 的焊墊電極、及設置在轉印對象基板6 6 (形成有畫素1 〇 ! 之基板1 〇 )的焊墊電極，形成各焊墊電極，使得其表面 的凹凸部份的最高部分亦即最高部分的高度，大略相同。 依此，由於晶片3 4能夠使被轉印至基板1 0上的轉印對象 區域時的接觸面，成爲大致相等，所以可以確保良好的導 通狀態。 接著，說明關於包含本實施形態的有機EL顯示裝置 1 0 0而構成的各種電子機器。第1 1圖係表示可以應用關 於本實施形態的有機E L顯示裝置之電子機器的具體例之 -35- (33) 1230445 圖。 第1 1圖（a )係應用於手機的例子；該手機2 3 0，具 備·天線2 3 1、聲苜輸出部2 3 2、聲音輸入部2 3 3、操作 部2 3 4 '及本實施形態的有機E L顯示裝置1 〇 〇。如此， 可以將本發明的顯示裝置作爲顯示部來使用。 第1 1圖（b )係應用於攝影機的例子；該攝影機2 4 0 ，具備：顯像部241、操作部242、聲音輸入部243、及 本實施形態的有機EL顯示裝置1 00。如此，關於本發明 的顯示裝置，可以作爲檢景器或顯示部來加以利用。 第1 1圖（c )係應用於攜帶型個人電腦的例子；該電 腦2 5 0 ’具備：照相部2 5 1、操作部2 5 2、及本實施形態 的有機E L顯示裝置1 〇 〇。如此，關於本發明的顯示裝置 ’可以作爲顯示部來加以利用。 第1 1圖（d )係應用於頭罩式顯示器的例子；該頭罩 式顯示器260，具備：束帶261、光學系統收容部262、 及本實施形態的有機EL顯示裝置1 00。如此，關於本發 明的顯示裝置，可以作爲影像顯示來源來加以利用。 又，關於本發明的顯示裝置1 〇 〇，並不限定於上述例 子，例如也可以應用於：附有顯示功能的傳真裝置、數位 照相機的檢景器、攜帶型TV、個人數位助理等的各種機 器。 再者，本發明並不被限定於上述實施形態的內容，在 本發明要旨的範圍內，可以進行各種變化實施。例如，在 上述實施形態中，係將分別被包含於各焊墊電極56a〜5 6j -36- 1230445 (34) 的「最高部分」的高度，全部形成爲L1 ;同 包含於各焊墊電極36a〜3 6j的「最高部分」& 部形成爲L2 ;但是關於各個被對向配置而成費 _電極，即使形成各焊墊電極，使得其表面所I 部分的最高部分的高度之合計，大略爲一定，貝 與上述實施形態同樣的效果。 第1 2圖係說明關於被對向配置而成對的名 的最高部分的高度之合計，作成大略成爲一定& 。於第12圖中’焊塾電極136a和焊塾電極1 電極1 3 6 b和焊墊電極1 5 6 b，係分別被對向配S 形成。又，在第12圖中，省略表示被形成在名 下側的積層膜。 被形成在轉印晶片1 3 4側的各焊墊電極，舅 15 6a的最高部分的高度爲LI 1、焊墊電極156b 分的高度爲L12，兩者的高度相異。又，被形成 側的各焊墊電極，其焊墊電極1 3 6 a的最高部分 L21、焊墊電極136b的最高部分的高度爲L22， 度相異。但是，若著眼於成對的焊墊電極的最请 度，則各焊墊電極係被形成使得焊墊電極1 3 6a 極1 5 6 a的最高部分的高度的合計，與焊墊電極 墊電極1 5 6 b的最高部分的高度的合計，大略相p 如此，在第12圖所示的實施形態中，關於 的一組焊墊電極，各焊墊電極係被形成使得其；i 高度的合計大略成爲一定。即使如此地形成各烤 F使分別被 ]高度，全 f的一組焊 【生的凹凸 J仍可得到 r焊墊電極 J情況之圖 5 6 a、焊墊 [而成對地 〃焊墊電極 ;焊墊電極 的最高部 在基板1 〇 、的高度爲 兩者的高 ί部分的高 和焊墊電 1 3 6 b和焊 司。 卜各個成對 ^高部分的 1墊電極， -37- 1230445 (36) 第10圖係說明關於使用骞方性導電膜來形成接著層 之情況的圖。 第1 1 ( a )至（d )圖係表示可以應用有機el顯示裝 置之電子機器的具體例之圖。 第1 2圖係說明關於被對向配置而成對的各焊墊電極 的最高部分的高度之合計，作成大略成爲一定的情況之圖Ce, Nd, Pr, Gd, Sm or an alloy containing at least one or more of these metals. Alternatively, the peeling layer can be formed using an alloy containing hydrogen. In the case where an alloy containing hydrogen is used as the release layer, hydrogen is released with the irradiation of light, thereby promoting the peeling in the release layer. It may also be configured using an alloy containing nitrogen. When an alloy containing nitrogen is used for the delamination, nitrogen is released along with the irradiation of light, which can promote peeling in the peeling layer. Furthermore, a multilayer film may be used as the release layer. The multilayer film can be made of, for example, an amorphous silicon film and a metal film formed thereon. As a material of the multilayer film, at least one of the above-mentioned ceramics, metals, and organic local molecular materials may be used. The method for forming the release layer 62 is not particularly limited, and it can be appropriately formed according to conditions such as the film composition and film thickness. For example, various vapor deposition methods such as CVD and sputtering, various plating methods, coating methods such as spin coating, various printing methods, transfer methods, inkjet coating methods, and powder spraying methods may be used. It is formed by combining two or more of these methods. Furthermore, although not shown in FIG. 8 (a), the transfer source substrate 60 and the release layer 62 may be transferred to the transfer source substrate 60 and the release layer 62 according to the properties of the transfer-27- (25) 1230445 source substrate 60 and the release layer 62. Between 'sets the middle layer for the purpose of raising the confidentiality of the two. This intermediate layer is used, for example, at the time of manufacture or use to perform: a protective layer that protects the transferred layer physically or chemically. At least one function of a barrier layer and a reflective layer for movement (migration) of components. < Second process > Next, the second process will be described. In the second process, as shown in FIG. 8 (b), a plurality of wafers 34 are formed on the release layer 62. A layer composed of a plurality of wafers 3 4 is referred to as a transferred layer 6 4. In the manufacture of thin-film transistors and the like, a certain high-temperature process is required. Therefore, to form a substrate such as a thin-film transistor, it is necessary to satisfy various conditions like a transfer source substrate. In the manufacturing method of this embodiment, since a thin film transistor or the like is manufactured using a transfer source substrate that satisfies various manufacturing conditions, the thin film transistor or the like can be transferred to a final substrate that does not satisfy the manufacturing conditions. That is, in the manufacturing method of this embodiment, as a final substrate, it is possible to use a substrate made of a relatively inexpensive material, which has the advantage of reducing the manufacturing cost, or it can use flexible flexibility The substrate and the like have advantages such as a wide selection range of the final substrate. Here, the separation of each wafer 34 in the transferred layer 64 will be described. As a method of separating each of the wafers 34, a method of separating each of the wafers 34 by etching or the like; a method of separating only the peeling layer; and a specific structure formed on the basis of -28-1230445 (26) A method of easily separating each of the objects to be transferred onto the print source substrate. Here, a method of completely separating each of the wafers 34 will be described. As shown in FIG. 8 (c), in order to separate the respective wafers 34, grooves 62c having a recessed structure are formed on the periphery of the region corresponding to the wafer 34 by wet etching or dry uranium etching, etc., so that Each wafer 34 remains in an island shape. This groove 62c is formed by cutting out all of the transferred layer 64 and all of the peeling layer 62 (refer to FIG. 8 (c)) or a part (refer to FIG. 8 (d)) in the thickness direction of the substrate. This cut may be shallower than the transferred layer 64. This groove 62c is formed by engraving uranium to a part of the release layer 62 as shown in FIG. 8 (d); the release layer 62 may also be completely etched as shown in FIG. 8 (c) to Each of the wafers 34 and the peeling layer 62 located immediately below them remain in an island shape in the same shape. By forming the same wafer 34 and then performing etching at an equal pitch, the transferees are arranged side by side on the transfer source substrate 60, and in the peeling process (the fourth and fifth processes described later), It is possible to easily transfer only the desired wafer 34. By cutting off the transferred layer 64 in advance, a part of the peeling body can be completely peeled along the shape of the area; when the area is peeled off, it can be prevented from being damaged. In addition, it is possible to prevent the transfer layer 64 from being damaged by the peeling, so that it cannot reach the adjacent area. In addition, by cutting in advance in the film thickness direction, the wafer 34 can be peeled off even if the bonding force for bonding the specific wafer 34 to the adhesive layer of the transfer target substrate is weak. In addition, since the appearance of the area to be transferred is clear, the transfer between substrates -29-1230445 (27) positioning during printing becomes easy. Further, as shown in FIG. 8 (e), over-etching may be performed so that the area of the bonding area 'between the peeling layer 62 and the wafer 34 is smaller than the entire area of the bonding surface of the peeling layer of the transfer target. When the release layer 62 is over-etched in this way, the area of the release layer becomes small. Therefore, when light is irradiated on the release layer 62 to perform peeling, in addition to being able to reliably peel with less force, By reducing the peeling layer 62, the light energy required for peeling can be reduced. Furthermore, as shown in FIG. 8 (d), the grooves 6 2c may be formed in advance by etching only the transferred layer > 64, so that the peeling layer 6 2 remains in a continuous state. If energy can be applied to the area where the wafer 34 is formed without omission, the peeling layer 62 in this area can be reliably peeled. Therefore, even if the peeling layer 62 itself is not provided with cracks, only the desired substrate can be transferred. The print is peeled. < Third process > Next, as shown in FIG. 9 (a), the surface on the formation side of the transfer source substrate 60 0 wafer 3 4 and the transfer target substrate 6 6 are transferred to the transfer wafer 3 The surfaces on the 4 sides are superposed while being aligned, and a pressing force is applied as needed, and only the wafer 3 4 to be transferred is selectively bonded to the transfer target substrate 66 side through the conductive adhesive layer 6 8. Here, in this embodiment, the i-th wiring layer is formed! 2 is formed on the substrate 10, and the state where the wiring 30 and the pad electrode 36 are formed on the first wiring layer 丨 2 (refer to FIG. 2) is equivalent to that shown in FIG. 9 (a). Transfer target substrate 66. Then, each pad electrode 36 included in the transfer target -30-1230445 (28) substrate 66 and each pad electrode 56a provided in the transfer target wafer 34 and the like are mutually made. The abutting is performed to attach the wafer 34. Suitable examples of the adhesive constituting the adhesive layer 68 include a light-curable adhesive such as a reaction-curable adhesive, a heat-curable adhesive, an ultraviolet-curable adhesive, and a gas-curable adhesive. Various hardening type adhesives. The composition of the adhesive agent may be, for example, epoxy-based, acrylic-based, polysiloxane-based, or the like. When a commercially available adhesive is used, an appropriate solvent can be added to the adhesive to be used to adjust the viscosity for proper coating. In this embodiment, the adhesive layer 68 is formed only on the wafer 34 to be transferred or only on the transfer target substrate 66 corresponding to the wafer 34 to be transferred. Such partial formation of the adhesive layer 68 can be performed by applying various printing methods or liquid ejection methods. The liquid ejection method includes a piezoelectric ejection method that ejects a liquid by deforming a piezoelectric body, or a method that generates bubbles by using heat to eject a liquid. In this embodiment, the formation of the adhesive layer 68 using the ink jet coating (liquid ejection) method is exemplified. Furthermore, as shown in FIG. 10, an anisotropic conductive film composed of conductive particles may be used to form the adhesive layer 69. In this case, since it is not necessary to provide an individual bonding layer for each pad electrode, the positioning accuracy is not so required, and there is an advantage that the formation of the bonding layer is easy. < 4th process > Next, as shown in FIG. 9 (b), the transfer source substrate 60 is a combination of both the transfer source substrate 60 and the transfer-31-1230445 (29) the printed target substrate 66. On the side, only the peeling layer 62 of the wafer 34 corresponding to the transfer is selectively irradiated only on the peeling layer 62 supporting the wafer 34 to cause peeling (peeling within the layer and / or interface). In-layer peeling and / or interfacial peeling of the release layer 62 may cause detachment in the constituent material of the release layer 62; or release of gas in the encapsulation layer 62; further, by melting after irradiation, Principles of phase changes such as evapotranspiration. Here, the so-called detachment means: the constituent material of the fixed peeling layer 62 that absorbs the irradiated light), and the photochemical or thermal reaction is excited, and the bonding of atoms or molecules on the surface or inside is cut off, and the peeling layer appears in the emitter. 6 All or part of the 2 constituent materials undergo a phase change such as vaporization (gasification). In addition, there are also those that become micro-bubbles and make the bonding force smaller according to the advance. The peeling layer 62 has internal layer peeling, interfacial peeling, or seed peeling, depending on the composition of the peeling layer 62 or various other reasons; as one of the reasons, for example, the type, intensity, and depth of irradiation light, etc. conditions of. As the irradiation light L, any separation and / or interface peeling in the release layer 62 may be used; for example, X-rays, ultraviolet rays, infrared rays, laser light, and the like. Among them, in order to make the peeling (detachment) of the peeling layer 62 easy and can be considered in terms of local irradiation with high accuracy, the laser light is an ideal kind of laser light, preferably a laser having a wavelength of 100 nm to 35 nm, and is separated by light L And the principle of containing the material produced in the peeling, and the main melting, the phase transition mentioned above, the two wavelengths affected by the above-mentioned layers, and the visible light generated by the peeling. This light. Borrow -32-1230445 (30) by using such a short Wavelength laser light can improve the accuracy of light irradiation and effectively peel the peeling layer 62. As a laser device that generates such laser light, the use of excimer laser is appropriate. Area, high energy output, so separation can occur in the peeling layer 62 in a very short time; therefore, the temperature of the adjacent transfer target substrate 66 or the first substrate 60, etc., hardly rises, and the wafers 3, 4, etc. The peeling layer 62 can be peeled without deterioration or damage. Alternatively, for example, when the peeling layer 62 undergoes a phase change such as gas evolution, vaporization, sublimation, and the like, and provides separation characteristics The wavelength of the laser light to be irradiated is preferably about 350 nm to 1 200 nm. The laser light with such a wavelength can be a laser light source or an irradiation device widely used in general processing fields such as YAG and gas lasers; Light irradiation can be performed inexpensively and simply. Moreover, by using laser light having a wavelength in the visible light region, the transfer source substrate 60 only needs to be transparent to visible light, and selection of the transfer source substrate 60 can be made. The degree of freedom is widened. Also, the energy density of the irradiated laser light, particularly the energy density in the case of excimer laser light, is preferably about 10 to 5,000 mJ / cm2, and more preferably about 1 to 500 mJ / cm2. In addition, the irradiation time is preferably about 1 to 100 Onsec, and more preferably 10 to 100 nsec. The higher the energy density or the longer the irradiation time, the detachment is likely to occur; on the other hand, the lower the energy density or the shorter the irradiation time, the It is possible to reduce the possibility of adverse effects on the wafer 34 due to the light irradiated through the release layer 62. -33- 60 1230445 (31) < Fifth process > Next, as shown in FIG. 9 (c) Show The transfer source substrate and the transfer target substrate 66 are applied with a force to separate them from each other, and the transfer substrate 60 is detached from the transfer target substrate 6 6. The transfer to the transfer target substrate 60 is performed by the fourth process described above. The release layer 6 2 ′ of the wafer 3 4 on the transfer target substrate 6 6 is peeled from the wafer 34, so these wafers 3 4 ′ to be transferred are cut off from the first substrate 60 side. Also, the wafers to be transferred are cut off. 3 4 is bonded to the transfer target substrate 66 by an adhesive layer. Furthermore, in the aforementioned fourth process, although the release layer 62 is desirably completely peeled off, the adhesive layer 6 of the wafer 3 4 to be transferred should be The bonding strength is stronger than the bonding force generated by the peeling layer 6 2 to be left. 'When the transfer source substrate 60 and the transfer target substrate 6 6 are separated,' the wafer 3 4 to be transferred is surely transferred to In the case of the transfer target substrate 66, only a part of the release layer 62 can be peeled. The transfer of such a transfer body is determined based on the relative force relationship between the bonding force of the release layer weakened by the peeling of the release layer and the combined force applied to the adhesive layer of the transfer body. If the release charge produced by the release layer is weak, the transfer force of the transfer layer is possible even if the bonding force of the adhesive layer is weak. On the contrary, if the release force produced by the release layer is not sufficient, if the adhesive force of the adhesive layer is high, the The object to be transferred is transferred. As shown in FIG. 9 (c), by separating the transfer source substrate 60 from the transfer target substrate 66, the wafer 34 is transferred to a predetermined position on the transfer target substrate 66. Then, 'the circuit board is completed by forming an insulating film covering the wafer 34, etc., and forming the second wiring layer 14 shown in FIG. 2; the source should be printed from 1 68, and the result should be printed, etc. -34-1230445 (32) Further, by forming a light-emitting element layer 16 on the second wiring layer 14, an organic EL display device 100 is formed. In addition, the wafer 3 4 transferred to the transfer target substrate 6 6 may adhere to the residual portion of the peeling layer 62, and it is desirable to completely remove it. A method for removing the remaining release layer 62 is, for example, a method of cleaning, etching, ashing, honing, or the like, or a method of appropriately selecting and combining these methods. Similarly, on the surface of the transfer source substrate 60 where the transfer of the wafer 34 has been completed, when the peeling residue of the release layer 62 is adhered, it can be removed in the same manner as the transfer target substrate 66 described above. In this way, the transfer source substrate 60 can be reused (recycled). By reusing the transfer source substrate 60 in this way, manufacturing costs can be saved. This is particularly useful when a transfer source substrate 60 made of a high-priced material such as quartz glass and a rare material is used. As described above, in this embodiment, each of the pad electrodes provided on the wafer 34 side and the pad electrodes provided on the transfer target substrate 6 6 (the substrate 1 〇 where the pixel 1 〇! Is formed) is formed. The height of the highest portion of the pad electrode on the surface of the pad electrode, that is, the highest portion, is substantially the same. Accordingly, since the wafer 34 can make the contact surfaces at the time of being transferred to the transfer target region on the substrate 10 approximately equal, a good conduction state can be ensured. Next, various electronic devices configured including the organic EL display device 100 of this embodiment will be described. FIG. 11 is a -35- (33) 1230445 showing a specific example of an electronic device to which the organic EL display device according to this embodiment can be applied. Figure 11 (a) is an example applied to a mobile phone; the mobile phone 2 3 0 includes an antenna 2 3 1, a sound output unit 2 3 2, a sound input unit 2 3 3, an operation unit 2 3 4 ′, and The organic EL display device 100 of the embodiment. In this way, the display device of the present invention can be used as a display unit. FIG. 11 (b) is an example applied to a video camera. The video camera 240 includes a display unit 241, an operation unit 242, a voice input unit 243, and an organic EL display device 100 according to this embodiment. As described above, the display device of the present invention can be used as a viewfinder or a display unit. Fig. 11 (c) shows an example applied to a portable personal computer. The computer 250 'includes a camera section 25, an operation section 25, and an organic EL display device 100 according to this embodiment. As described above, the display device ′ of the present invention can be used as a display unit. FIG. 11 (d) is an example applied to a head-mounted display. The head-mounted display 260 includes a strap 261, an optical system housing portion 262, and the organic EL display device 100 of this embodiment. As described above, the display device of the present invention can be used as a video display source. The display device 100 of the present invention is not limited to the above examples, and may be applied to, for example, a facsimile device with a display function, a viewfinder of a digital camera, a portable TV, and a personal digital assistant. machine. It should be noted that the present invention is not limited to the contents of the embodiments described above, and various modifications can be made within the scope of the gist of the present invention. For example, in the above embodiment, the height of the "highest part" included in each pad electrode 56a to 5 6j -36-1230445 (34) is all formed as L1; the same is included in each pad electrode 36a The "highest part" of ~ 3 6j is formed as L2; however, each electrode is arranged oppositely to form an electrode. Even if each pad electrode is formed, the total height of the highest part of the part I on the surface is roughly the same. To be sure, the same effects as in the above-mentioned embodiment can be obtained. Figure 12 illustrates the total height of the highest part of the paired names arranged opposite to each other. In Fig. 12, the 'soldering electrode 136a, the welding electrode 1 electrode 1 3 6 b, and the pad electrode 1 5 6 b are formed by the opposite alignment S, respectively. In Fig. 12, the laminated film formed on the underside is omitted. Each pad electrode formed on the transfer wafer 1 3 4 side has a height of LI 1 at the highest portion of 舅 15 6a and a height of 156 b of the pad electrode L12. The heights of the two are different. Moreover, the height of the highest portion L21 of the pad electrode 136a and the highest portion of the pad electrode 136b of each pad electrode on the formed side is L22, and the degrees are different. However, if attention is paid to the pair of pad electrodes, each pad electrode system is formed such that the total height of the highest portion of the pad electrode 1 3 6a and the electrode 15 6 a is equal to that of the pad electrode pad electrode. The total height of the highest part of 1 5 6 b is roughly the same as p. In the embodiment shown in FIG. 12, each pad electrode system is formed so that it is a group of pad electrodes; i Roughly became certain. Even in this way, each baking F is formed so that it is respectively] high, and a set of welding f of the whole f can still get r pad electrode J. Figure 5 6a, pad [composed of ground pad electrode The highest part of the pad electrode is on the substrate 10, and the height of the two parts is the height of the two parts, and the pads are 1 3 6 b and the welding division. Each pad electrode in a pair of high portions, -37-1230445 (36) Fig. 10 is a diagram illustrating a case where a rectangular conductive film is used to form an adhesive layer. Figures 11 (a) to (d) are diagrams showing specific examples of electronic equipment to which an organic el display device can be applied. FIG. 12 is a diagram for explaining a case where the total height of the highest portions of the pad electrodes arranged in pairs facing each other is roughly constant.

〔符號說明〕 2 0、30:配線 34 :晶片（轉印晶片） 36、36&〜36』、56&〜56〗、：焊墊電極（連接端子） 36d-l、36d_2、36f-l、36f-2、56d-l、56d-2、56f-l :最高部分[Description of Symbols] 2 0, 30: Wiring 34: Wafer (Transfer Wafer) 36, 36 & ~ 36 』, 56 & ~ 56〗 ,: Pad electrode (connection terminal) 36d-1, 36d_2, 36f-1, 36f-2, 56d-l, 56d-2, 56f-l: highest part

40 :畫素電極 42 :共通電極 44 :發光層 100 :有機EL (電激發光）顯示裝置 1 0 1 :畫素 39-40: pixel electrode 42: common electrode 44: light emitting layer 100: organic EL (electrically excited light) display device 1 0 1: pixel 39-

Claims (1)

1230445 (1) 拾、申請專利範圍 1 · 一種電路基板之製造方法，係包含： 轉印晶片形成製程，用於在第1基板上形成轉印晶片 ’該轉印晶片包含：以積層膜形成之薄膜電路，及作爲連 接該薄膜電路與其他電路用之連接端子的多數個第1焊墊 電極； 轉印對象基板形成製程，用於形成包含電路配線及多 數個第2焊墊電極的第2基板，該第2焊墊電極，係連接 於該電路配線之同時，與形成於上述轉印晶片上之上述多 數個第1焊墊電極之各個對應配置於轉印對象區域；及 轉印製程，用於將上述第1基板上之上述轉印晶片轉 印於上述第2基板上之上述轉印對象區域使上述薄膜電路 連接於上述電路配線而形成電路基板； 上述多數個第1焊墊電極，係涵蓋上述轉印晶片之一 面全體被配置，各第1焊墊電極係形成爲覆蓋構成其下側 存在之上述薄膜電路之薄膜元件或薄膜配線，依此而使表 面產生之凹凸部分之最高部分之高度於各焊墊電極形成爲 大略相同。 2. 如申請專利範圍第1項之電路基板之製造方法， 其中 上述多數個第1焊墊電極，係於形成上述薄膜元件或 上述薄膜配線時被附加高度調整膜據以調整上述凹凸部分 之最高部分之高度。 3. 如申請專利範圍第1或2項之電路基板之製造方 -40- (2) 1230445 法，其中 於上述轉印對象基板形成製程中，上述多數個第2焊 墊電極’係形成爲覆蓋構成其下側存在之上述電路配線， 依此而使表面產生之凹凸部分之最高部分之高度於各第2 焊墊電極形成爲大略相同。 4 ·如申請專利範圍第3項之電路基板之製造方法， 其中 上述多數個第2焊墊電極，係於形成上述電路配線時 被附加高度調整膜據以調整上述凹凸部分之最高部分之高 度。 5 .如申請專利範圍第1或2項之電路基板之製造方 法，其中 上述多數個第1焊墊電極之各個，其於上述最高部分 對應區域中之上述積層膜之膜構成爲相同。 6.如申請專利範圍第1或2項之電路基板之製造方 法，其中 上述多數個第2焊墊電極之各個，其於上述最高部分 對應區域中之下側之上述積層膜之膜構成爲相同。 7 · —種電路基板之製造方法，係包含： 轉印晶片形成製程，用於在第1基板上形成轉印晶片 ’該轉印晶片包含··以積層膜形成之薄膜電路’及作爲連 接該薄膜電路與其他電路用之連接端子的多數個第1焊墊 電極； 轉印對象基板形成製程，用於形成包含電路配線及多 -41 - 1230445 (3) 數個第2焊墊電極的第2基板，該第2焊墊電極，係連接 於該電路配線之同時，與形成於上述轉印晶片上之上述多 數個第1焊墊電極之各個對應配置於轉印對象區域·，及 轉印製程，用於將上述第1基板上之上述轉印晶片轉 印於上述第2基板上之上述轉印對象區域使上述薄膜電路 連接於上述電路配線而形成電路基板； 上述多數個第1焊墊電極，係涵蓋上述轉印晶片之一 面全體被配置，各第1焊墊電極係形成爲覆蓋構成其下側 存在之上述薄0吴電路之薄0吴兀件或薄膜配線， 上述多數個第2焊墊電極，係和上述多數個第1焊墊 電極之配置對應地涵蓋上述轉印對象區域全體被配置，各 第2焊墊電極係形成爲覆蓋構成其下側存在之上述電路配 線’ 上述第1焊墊電極與第2焊墊電極之各個係形成於， 可使呈對向配置而構成對之一組第1及第2焊墊電極之各 個之表面產生之凹凸部分之最高部分之高度合計成爲大略 一定。 8.如申請專利範圍第1、2或7項之電路基板之製造 方法，其中 上述轉印製程包含：在上述轉印晶片上形成之上述第 1焊墊電極與上述第2基板上形成之上述第2焊墊電極之 間形成接著層的製程。 9 ·如申請專利範圍第1、2或7項之電路基板之製造 方法，其中 -42- (4) 1230445 上述轉印晶片形成製程包含形成剝離層之製程，該剝 離層爲介於上述第1基板與上述轉印晶片之間，且具有藉 由被賦與能量產生狀態變化以弱化其與上述轉印晶片間之 固接狀況的性質。 10. 一種轉印晶片，係作爲至少包含：以積層膜形成 之薄膜電路，及作爲連接該薄膜電路與其他電路用之多數 個焊墊電極，的轉印單位被形成於第1基板，由該第1基 板被轉印至形成有配線之第2基板的轉印晶片； 上述多數個焊墊電極，係涵蓋上述轉印晶片之一面全 體被配置，各焊墊電極係形成爲覆蓋構成其下側存在之上 述薄膜電路之薄膜元件或薄膜配線，依此而使表面產生之 凹凸部分之最高部分之高度於各焊墊電極形成爲大略相同 〇 1 1 · 一種轉印來源基板，係將多數個個申請專利範圍 第1 0項之轉印晶片形成於基板上而構成者。 1 2 ·如申請專利範圍第1 1項之轉印來源基板，其中 上述轉印來源基板另具有剝離層，該剝離層爲介於上 述基板與上述轉印晶片之間，且具有藉由被賦與能量產生 狀態變化以弱化其與上述轉印晶片間之固接狀況的性質。 1 3 . —種光電裝置，係使用申請專利範圍第〗至9項 中任一項之製造方法製造之電路基板而製造者。 1 4 · 一種電子機器，係使用申請專利範圍第1 3項之光 電裝置作爲顯示部者。 -43-1230445 (1) Pick up and apply for patent scope 1 · A method for manufacturing a circuit board includes: a transfer wafer forming process for forming a transfer wafer on a first substrate; the transfer wafer includes: a laminated film Thin film circuit and a plurality of first pad electrodes as connection terminals for connecting the thin film circuit to other circuits; a transfer target substrate forming process for forming a second substrate including circuit wiring and a plurality of second pad electrodes The second pad electrode is connected to the circuit wiring and is disposed in the transfer target area in correspondence with each of the plurality of first pad electrodes formed on the transfer wafer; and the transfer process is used for A circuit board is formed by transferring the thin film circuit to the circuit wiring by transferring the transfer wafer on the first substrate to the transfer target region on the second substrate; the plurality of first pad electrodes are The entire surface of one of the transfer wafers is arranged, and each of the first pad electrodes is formed so as to cover a thin film element or a thin film that constitutes the above-mentioned thin film circuit. Wiring, so the height of the highest portion of the convex portion of the surface of the pad is generated in each of the welding electrodes are formed as roughly identical. 2. For the method of manufacturing a circuit board according to item 1 of the scope of patent application, in which the plurality of first pad electrodes are added with a height adjustment film to adjust the height of the uneven portion when forming the thin film element or the thin film wiring. The height of the part. 3. For example, the method for manufacturing circuit boards of the scope of patent application No. 1 or 2 is -40- (2) 1230445 method, in the above-mentioned transfer target substrate forming process, the above-mentioned plurality of second pad electrodes are formed to cover The above-mentioned circuit wiring that is formed below it is formed so that the height of the highest portion of the uneven portion generated on the surface is substantially the same as that of each of the second pad electrodes. 4. The method for manufacturing a circuit board according to item 3 of the scope of patent application, wherein the plurality of second pad electrodes are adjusted in height by adding a height adjustment film when forming the circuit wiring. 5. The method for manufacturing a circuit board according to item 1 or 2 of the scope of patent application, wherein each of the plurality of first pad electrodes described above has the same film structure of the laminated film in the corresponding region of the highest part. 6. The method for manufacturing a circuit board according to item 1 or 2 of the scope of patent application, wherein each of the above-mentioned plurality of second pad electrodes has the same film structure of the above-mentioned laminated film in the corresponding region of the highest part above . 7 · A method for manufacturing a circuit substrate, comprising: a transfer wafer forming process for forming a transfer wafer on a first substrate; "the transfer wafer includes a thin film circuit formed of a laminated film" and as a connection to the Many first pad electrodes for connection terminals of thin film circuits and other circuits; transfer target substrate forming process for forming circuit pads and multiple -41-1230445 (3) second second pad electrodes The substrate, the second pad electrode are connected to the circuit wiring, and are arranged in the transfer target area in correspondence with each of the plurality of first pad electrodes formed on the transfer wafer, and the transfer process Configured to transfer the transfer wafer on the first substrate to the transfer target region on the second substrate so that the thin film circuit is connected to the circuit wiring to form a circuit substrate; the plurality of first pad electrodes The first pad electrode is formed to cover the entire surface of the transfer wafer, and each of the first pad electrodes is formed to cover the thin-walled components or thin-film wiring that constitute the thin-walled circuit described above, The plurality of second pad electrodes are arranged so as to cover the entire area of the transfer target area corresponding to the arrangement of the plurality of first pad electrodes, and each of the second pad electrodes is formed so as to cover the above-mentioned existing on the lower side. Circuit wiring 'Each of the above-mentioned first pad electrode and second pad electrode is formed so that it is possible to arrange them in an opposite direction to form uneven portions on the surfaces of each of the pair of first and second pad electrodes. The total height of the highest part becomes roughly constant. 8. The method for manufacturing a circuit board according to item 1, 2, or 7 of the scope of patent application, wherein the transfer process includes: the first pad electrode formed on the transfer wafer and the above formed on the second substrate. A process of forming a bonding layer between the second pad electrodes. 9 · If the method of manufacturing a circuit board according to item 1, 2 or 7 of the scope of patent application, wherein -42- (4) 1230445 The above-mentioned transfer wafer formation process includes a process of forming a release layer, the release layer is between the above-mentioned first Between the substrate and the above-mentioned transfer wafer, there is a property that a state change is caused by being imparted with energy to weaken the state of the connection between the substrate and the above-mentioned transfer wafer. 10. A transfer wafer comprising at least: a thin film circuit formed of a laminated film and a plurality of pad electrodes for connecting the thin film circuit and other circuits, a transfer unit is formed on a first substrate, and The first substrate is transferred to a transfer wafer on which the wiring is formed on the second substrate. The plurality of pad electrodes are arranged so as to cover the entire surface of the transfer wafer, and each pad electrode is formed so as to cover the lower side. The thin film elements or thin film wirings of the above-mentioned thin film circuits are formed so that the height of the highest part of the uneven portion generated on the surface is substantially the same as that of each pad electrode. 1 1 · A transfer source substrate is a plurality of A transfer wafer having a scope of application for item 10 is formed on a substrate. 1 2 · The transfer source substrate according to item 11 of the scope of patent application, wherein the transfer source substrate further has a release layer, which is interposed between the substrate and the transfer wafer, and is provided by The state changes with energy generation to weaken the nature of the state of the connection with the transfer wafer. 1 3. — An optoelectronic device is a circuit board manufactured using the manufacturing method of any one of the scope of patent applications Nos. 9 to 9. 1 4 · An electronic device that uses a photovoltaic device as claimed in item 13 of the patent application as the display unit. -43-
TW092127693A 2002-10-08 2003-10-06 Circuit board and its manufacturing method, transfer chip, transfer source substrate, optoelectronic apparatus, and electronic machine TWI230445B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002295134A JP3918708B2 (en) 2002-10-08 2002-10-08 Circuit board and manufacturing method thereof, transfer chip, transfer source substrate, electro-optical device, electronic apparatus

Publications (2)

Publication Number Publication Date
TW200416966A TW200416966A (en) 2004-09-01
TWI230445B true TWI230445B (en) 2005-04-01

Family

ID=32025513

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092127693A TWI230445B (en) 2002-10-08 2003-10-06 Circuit board and its manufacturing method, transfer chip, transfer source substrate, optoelectronic apparatus, and electronic machine

Country Status (6)

Country Link
US (1) US7726013B2 (en)
EP (1) EP1408365B1 (en)
JP (1) JP3918708B2 (en)
KR (1) KR100553491B1 (en)
DE (1) DE60326200D1 (en)
TW (1) TWI230445B (en)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4411598B2 (en) * 2004-09-30 2010-02-10 セイコーエプソン株式会社 Transfer source substrate and semiconductor device manufacturing method
JP2006196712A (en) * 2005-01-13 2006-07-27 Toshiba Corp Manufacturing method of thin-film element
JP4692268B2 (en) * 2005-12-22 2011-06-01 パナソニック株式会社 Electronic component mounting system and electronic component mounting method
JP2008003577A (en) * 2006-05-25 2008-01-10 Canon Inc Method of manufacturing image display device and method of dividing device
US20080122119A1 (en) * 2006-08-31 2008-05-29 Avery Dennison Corporation Method and apparatus for creating rfid devices using masking techniques
KR100867924B1 (en) * 2007-03-07 2008-11-10 삼성에스디아이 주식회사 Donor substrate, method of fabricating thereof and organic light emitting display device
US7807520B2 (en) * 2007-06-29 2010-10-05 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8034663B2 (en) 2008-09-24 2011-10-11 Eastman Kodak Company Low cost die release wafer
US20100072490A1 (en) * 2008-09-24 2010-03-25 Kerr Roger S Low cost flexible display sheet
JP5390832B2 (en) * 2008-11-04 2014-01-15 キヤノン株式会社 Functional area transfer method, LED array, LED printer head, and LED printer
US8279145B2 (en) * 2009-02-17 2012-10-02 Global Oled Technology Llc Chiplet driver pairs for two-dimensional display
JP5258666B2 (en) * 2009-04-22 2013-08-07 株式会社半導体エネルギー研究所 Method for manufacturing light emitting device and substrate for film formation
US9209059B2 (en) * 2009-12-17 2015-12-08 Cooledge Lighting, Inc. Method and eletrostatic transfer stamp for transferring semiconductor dice using electrostatic transfer printing techniques
US20110151114A1 (en) * 2009-12-18 2011-06-23 Cooledge Lighting, Inc. Composite patterning device and method for removing elements from host substrate by establishing conformal contact between device and a contact surface
US11325828B2 (en) * 2013-02-22 2022-05-10 Vibrant Composites Inc. High-volume millimeter scale manufacturing
KR20180021926A (en) 2013-12-02 2018-03-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device and method for manufacturing the same
CN111128707B (en) * 2014-08-26 2023-06-16 株式会社尼康 Method for manufacturing element and transfer substrate
CN106158848B (en) * 2015-04-07 2019-03-22 群创光电股份有限公司 Display panel
WO2016183844A1 (en) * 2015-05-21 2016-11-24 Goertek.Inc Transferring method, manufacturing method, device and electronic apparatus of micro-led
EP3221882A4 (en) * 2015-07-14 2018-05-02 Goertek Inc. Assembling method, manufacturing method, device and electronic apparatus of flip-die
US10586817B2 (en) 2016-03-24 2020-03-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and separation apparatus
JP2017207744A (en) 2016-05-11 2017-11-24 株式会社半導体エネルギー研究所 Display device, module, and electronic device
KR102554183B1 (en) 2016-07-29 2023-07-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Separation method, display device, display module, and electronic device
KR102638304B1 (en) * 2016-08-02 2024-02-20 삼성디스플레이 주식회사 Display apparatus
TW201808628A (en) 2016-08-09 2018-03-16 Semiconductor Energy Lab Manufacturing method of semiconductor device
DE102016124646A1 (en) * 2016-12-16 2018-06-21 Osram Opto Semiconductors Gmbh Method for producing a semiconductor component
KR102448482B1 (en) * 2017-12-29 2022-09-27 엘지디스플레이 주식회사 Display device comprising microchip
CN108807265B (en) * 2018-07-09 2020-01-31 厦门乾照光电股份有限公司 Micro-LED bulk transfer method, display device and manufacturing method
CN113540156A (en) * 2020-04-15 2021-10-22 深圳市柔宇科技有限公司 Display panel, preparation method thereof and electronic device
CN112967987B (en) * 2020-10-30 2022-03-01 重庆康佳光电技术研究院有限公司 Chip transfer substrate and chip transfer method
CN113257978A (en) * 2021-05-12 2021-08-13 华南理工大学 Chip transfer apparatus and chip transfer method
CN113257979A (en) * 2021-05-12 2021-08-13 华南理工大学 Chip transfer substrate, chip transfer apparatus and chip transfer method

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8402654D0 (en) * 1984-02-01 1984-03-07 Secr Defence Flatpanel display
JP2833111B2 (en) * 1989-03-09 1998-12-09 日立化成工業株式会社 Circuit connection method and adhesive film used therefor
DE4032397A1 (en) * 1990-10-12 1992-04-16 Bosch Gmbh Robert METHOD FOR PRODUCING A HYBRID SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE PRODUCED BY THE METHOD
AU648417B2 (en) * 1991-03-27 1994-04-21 Integrated System Assemblies Corporation Multichip integrated circuit module and method of fabrication
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5384691A (en) * 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
KR0162531B1 (en) * 1994-09-30 1998-12-15 가네꼬 히사시 Manufacture of anisotropic conductive film and manufacture of lcd panel using this film
US20020004320A1 (en) * 1995-05-26 2002-01-10 David V. Pedersen Attaratus for socketably receiving interconnection elements of an electronic component
US5566448A (en) * 1995-06-06 1996-10-22 International Business Machines Corporation Method of construction for multi-tiered cavities used in laminate carriers
JPH1041349A (en) * 1996-07-24 1998-02-13 Hitachi Chem Co Ltd Circuit board
JP4619462B2 (en) * 1996-08-27 2011-01-26 セイコーエプソン株式会社 Thin film element transfer method
JP2000323534A (en) * 1999-05-13 2000-11-24 Sony Corp Mounting structure of semiconductor element and mounting method thereof
JP3447619B2 (en) * 1999-06-25 2003-09-16 株式会社東芝 Active matrix substrate manufacturing method, intermediate transfer substrate
JP4058607B2 (en) * 1999-08-19 2008-03-12 セイコーエプソン株式会社 WIRING BOARD AND ITS MANUFACTURING METHOD, ELECTRONIC COMPONENT, CIRCUIT BOARD AND ELECTRONIC DEVICE
JP2001168339A (en) * 1999-12-08 2001-06-22 Sharp Corp Method for forming transistor array panel for display
JP3906653B2 (en) 2000-07-18 2007-04-18 ソニー株式会社 Image display device and manufacturing method thereof
JP4655368B2 (en) 2000-12-12 2011-03-23 日本電気株式会社 Mobile terminal
JP2002244576A (en) * 2001-02-21 2002-08-30 Sony Corp Method for manufacturing display device, display device and liquid crystal display device
JP3994681B2 (en) 2001-04-11 2007-10-24 ソニー株式会社 Element arrangement method and image display device manufacturing method
JP3890921B2 (en) 2001-06-05 2007-03-07 ソニー株式会社 Element arrangement method and image display device manufacturing method
JP2002314123A (en) 2001-04-18 2002-10-25 Sony Corp Method of transferring element, method of arranging element using it, and method of manufacturing image display device
JP3608615B2 (en) 2001-04-19 2005-01-12 ソニー株式会社 Device transfer method, device array method using the same, and image display device manufacturing method
JP2002343944A (en) 2001-05-14 2002-11-29 Sony Corp Transferring method of electronic part, arraying method of element, and manufacturing method of image display device

Also Published As

Publication number Publication date
DE60326200D1 (en) 2009-04-02
KR20040032047A (en) 2004-04-14
EP1408365A3 (en) 2005-02-02
US20040128829A1 (en) 2004-07-08
EP1408365A2 (en) 2004-04-14
KR100553491B1 (en) 2006-02-20
US7726013B2 (en) 2010-06-01
EP1408365B1 (en) 2009-02-18
TW200416966A (en) 2004-09-01
JP2004133047A (en) 2004-04-30
JP3918708B2 (en) 2007-05-23

Similar Documents

Publication Publication Date Title
TWI230445B (en) Circuit board and its manufacturing method, transfer chip, transfer source substrate, optoelectronic apparatus, and electronic machine
TWI236135B (en) Method of manufacturing optoelectronic apparatus, optoelectronic apparatus, transferring chip, transferring source substrate, and electronic machine
KR100711745B1 (en) Active matrix substrate and method of manufacturing the same, electro-optical device, and electronic device
CN100489569C (en) Method of manufacturing optical film
US6814832B2 (en) Method for transferring element, method for producing element, integrated circuit, circuit board, electro-optical device, IC card, and electronic appliance
KR100494479B1 (en) Method for manufacturing an active matrix substrate
US7282385B2 (en) Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus
TW200415422A (en) Liquid crystal display device and manufacturing method of liquid crystal display device
JPH10177187A (en) Method for attaining electric conduction between transferred thin film structure blocks, production of active matrix substrate, the active matrix substrate, and liquid crystal device
JP2004349539A (en) Method of peeling and manufacturing laminate, electrooptic device, and electronic equipment
JP4939742B2 (en) Method for producing optical film
JP4244003B2 (en) Device chip mounting method

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees