JP4206321B2 - 半導体素子収納用パッケージおよび半導体装置 - Google Patents
半導体素子収納用パッケージおよび半導体装置 Download PDFInfo
- Publication number
- JP4206321B2 JP4206321B2 JP2003332019A JP2003332019A JP4206321B2 JP 4206321 B2 JP4206321 B2 JP 4206321B2 JP 2003332019 A JP2003332019 A JP 2003332019A JP 2003332019 A JP2003332019 A JP 2003332019A JP 4206321 B2 JP4206321 B2 JP 4206321B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- circuit board
- line conductor
- semiconductor element
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Semiconductor Lasers (AREA)
Description
1a:載置部
2:枠体
2a:棚部
2b:貫通孔
3:同軸コネクタ
3a:外周導体
3b:中心導体
3c:絶縁体
4:蓋体
5:半導体素子
6:回路基板
6a:線路導体
6b:同一面接地導体
Claims (2)
- 半導体素子の載置部を含む上側主面を有している基体と、
貫通孔が形成された側部を有しており、前記載置部を囲繞するように前記上側主面に接合された金属製の枠体と、
前記貫通孔に嵌着されているとともに、外周導体と中心導体と絶縁体とを含んでおり、前記中心導体が前記外周導体の中心軸に設けられており、前記絶縁体が前記外周導体および前記中心導体の間に介在されている同軸コネクタと、
前記枠体の内面のうち前記貫通孔の下方の部位に設けられた棚部の上面、または、前記基体の前記載置部と前記枠体の前記側部との間に設けられているとともに、線路導体および同一面接地導体を含む上面を有しており、前記線路導体が前記中心導体に電気的に接続された一端部と前記半導体素子に電気的に接続される他端部とを有しており、前記同一面接地導体が前記線路導体の両側に設けられている回路基板と、を備えており、
前記線路導体および前記同一面接地導体の各々の前記中心導体側の端が、前記回路基板の前記中心導体側の端面に達しておらず、
前記線路導体と前記端面との距離が、前記同一面接地導体と前記端面との距離より大きいことを特徴とする半導体素子収納用パッケージ。 - 請求項1記載の半導体素子収納用パッケージと、
前記基体の前記載置部に固定されており、前記線路導体に電気的に接続された半導体素子と、
を備えた半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003332019A JP4206321B2 (ja) | 2003-09-24 | 2003-09-24 | 半導体素子収納用パッケージおよび半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003332019A JP4206321B2 (ja) | 2003-09-24 | 2003-09-24 | 半導体素子収納用パッケージおよび半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005101206A JP2005101206A (ja) | 2005-04-14 |
JP4206321B2 true JP4206321B2 (ja) | 2009-01-07 |
Family
ID=34460493
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003332019A Expired - Fee Related JP4206321B2 (ja) | 2003-09-24 | 2003-09-24 | 半導体素子収納用パッケージおよび半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4206321B2 (ja) |
-
2003
- 2003-09-24 JP JP2003332019A patent/JP4206321B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005101206A (ja) | 2005-04-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6258724B2 (ja) | 電子部品搭載用パッケージおよびそれを用いた電子装置 | |
JP2016189431A (ja) | 電子部品搭載用パッケージおよびそれを用いた電子装置 | |
JP6193595B2 (ja) | 電子部品搭載用パッケージおよびそれを用いた電子装置 | |
JP5241609B2 (ja) | 構造体,接続端子,パッケージ、並びに電子装置 | |
JP5725876B2 (ja) | 電子部品収納用パッケージおよび電子装置 | |
KR20170137153A (ko) | 전자 부품 탑재용 패키지 및 그것을 사용한 전자 장치 | |
JP6122309B2 (ja) | 電子部品搭載用パッケージおよびそれを用いた電子装置 | |
JP4903738B2 (ja) | 電子部品収納用パッケージおよび電子装置 | |
JP2009054982A (ja) | 電子部品搭載用パッケージおよびそれを用いた電子装置 | |
JP4789636B2 (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP5743712B2 (ja) | 電子部品収納用パッケージおよび電子装置 | |
JP4969490B2 (ja) | 基板保持部材及びパッケージ、並びに電子装置 | |
JP4377768B2 (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP2009283898A (ja) | 電子部品容器体およびそれを用いた電子部品収納用パッケージならびに電子装置 | |
JP4206321B2 (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP4522010B2 (ja) | 入出力端子および半導体素子収納用パッケージおよび半導体装置 | |
JP3690656B2 (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP3720726B2 (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP4210207B2 (ja) | 高周波用配線基板 | |
JP3702241B2 (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP5734072B2 (ja) | 電子部品収納用パッケージおよび電子装置 | |
JP2004134413A (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP4164011B2 (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP3652278B2 (ja) | 半導体素子収納用パッケージおよび半導体装置 | |
JP2006128323A (ja) | 半導体素子収納用パッケージおよび半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060912 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080620 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080624 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080821 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080924 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20081020 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111024 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121024 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131024 Year of fee payment: 5 |
|
LAPS | Cancellation because of no payment of annual fees |