JP4154391B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4154391B2 JP4154391B2 JP2004567536A JP2004567536A JP4154391B2 JP 4154391 B2 JP4154391 B2 JP 4154391B2 JP 2004567536 A JP2004567536 A JP 2004567536A JP 2004567536 A JP2004567536 A JP 2004567536A JP 4154391 B2 JP4154391 B2 JP 4154391B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- gas discharge
- discharge hole
- semiconductor device
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
Claims (6)
- 半導体素子と、
該半導体素子を搭載する樹脂基板と、
該樹脂基板を支持する支持板とを設けてなる半導体装置において、
前記支持板を貫通するガス放出孔を形成し、
前記樹脂基板内に、該樹脂基板内部で発生したガスを樹脂基板外部に放出する基板内ガス放出孔を形成し、
かつ、該基板内ガス放出孔と、前記ガス放出孔とが対向するよう構成し、
該基板内ガス放出孔と前記ガス放出孔とを介して前記樹脂基板で発生するガスを放出する構成とした半導体装置。 - 請求項1記載の半導体装置において、
更に、前記半導体素子と熱的に接続され、該半導体素子で発生する熱を放熱する放熱部材を設け、
かつ、該放熱部材を前記ガス放出孔の開口部に対し離間させた構成の半導体装置。 - 請求項1記載の半導体装置において、
更に、前記樹脂基板及び前記支持板を覆うキャップを設け、
かつ、該キャップに、前記ガス放出孔から放出されたガスを前記キャップの外部に放出するキャップ用ガス放出孔を形成した構成の半導体装置。 - 半導体素子と、
該半導体素子を搭載する基板と、
該基板に樹脂製接着材を用いて固定され、該基板を支持する支持板とを設けてなる半導体装置において、
前記支持板を貫通するガス放出孔を形成し、
前記基板内に、該基板内部で発生したガスを基板外部に放出する基板内ガス放出孔を形成し、
かつ、該基板内ガス放出孔と、前記ガス放出孔とが対向するよう構成し、
該基板内ガス放出孔と前記ガス放出孔とを介して前記基板及び前記樹脂製接着材で発生するガスを放出する構成とした半導体装置。 - 請求項4記載の半導体装置において、
更に、前記半導体素子と熱的に接続され、該半導体素子で発生する熱を放熱する放熱部材を設け、
かつ、該放熱部材を前記ガス放出孔の開口部に対し離間させた構成の半導体装置。 - 請求項4記載の半導体装置において、
更に、前記基板及び前記支持板を覆うキャップを設け、
かつ、該キャップに、前記ガス放出孔から放出されたガスを前記キャップの外部に放出するキャップ用ガス放出孔を形成した構成の半導体装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/000917 WO2004068581A1 (ja) | 2003-01-30 | 2003-01-30 | 半導体装置及び支持板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2004068581A1 JPWO2004068581A1 (ja) | 2006-05-25 |
JP4154391B2 true JP4154391B2 (ja) | 2008-09-24 |
Family
ID=32800824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004567536A Expired - Fee Related JP4154391B2 (ja) | 2003-01-30 | 2003-01-30 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7304389B2 (ja) |
JP (1) | JP4154391B2 (ja) |
WO (1) | WO2004068581A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009099620A (ja) * | 2007-10-12 | 2009-05-07 | Fujitsu Ltd | コア基板およびその製造方法 |
US20090166890A1 (en) * | 2007-12-31 | 2009-07-02 | Chrysler Gregory M | Flip-chip package |
JP6036083B2 (ja) * | 2012-09-21 | 2016-11-30 | 株式会社ソシオネクスト | 半導体装置及びその製造方法並びに電子装置及びその製造方法 |
EP3063832B1 (en) | 2013-10-29 | 2022-07-06 | Zoll Medical Israel Ltd. | Antenna systems and devices and methods of manufacture thereof |
EP3664694A4 (en) | 2017-08-10 | 2021-07-28 | Zoll Medical Israel Ltd. | SYSTEMS, DEVICES AND METHODS FOR THE PHYSIOLOGICAL MONITORING OF PATIENTS |
CN109243987B (zh) * | 2018-09-14 | 2020-06-16 | 苏州通富超威半导体有限公司 | 倒装结构及倒装方法 |
US10991680B2 (en) * | 2019-09-18 | 2021-04-27 | Alpha And Omega Semiconductor (Cayman), Ltd. | Common source land grid array package |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1050770A (ja) | 1996-08-05 | 1998-02-20 | Hitachi Ltd | 半導体装置及びその製造方法 |
JPH11186438A (ja) * | 1997-12-19 | 1999-07-09 | Toshiba Corp | 半導体装置 |
JP3275874B2 (ja) * | 1999-03-31 | 2002-04-22 | 日本電気株式会社 | 半導体装置及びスティフナー |
JP2000349178A (ja) * | 1999-06-08 | 2000-12-15 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6303871B1 (en) | 1999-06-11 | 2001-10-16 | Intel Corporation | Degassing hole design for olga trace impedance |
JP3899755B2 (ja) * | 1999-11-04 | 2007-03-28 | 富士通株式会社 | 半導体装置 |
US6383846B1 (en) * | 2000-03-20 | 2002-05-07 | Chi-Chih Shen | Method and apparatus for molding a flip chip semiconductor device |
-
2003
- 2003-01-30 JP JP2004567536A patent/JP4154391B2/ja not_active Expired - Fee Related
- 2003-01-30 WO PCT/JP2003/000917 patent/WO2004068581A1/ja active Application Filing
-
2005
- 2005-02-25 US US11/064,948 patent/US7304389B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050151234A1 (en) | 2005-07-14 |
JPWO2004068581A1 (ja) | 2006-05-25 |
WO2004068581A1 (ja) | 2004-08-12 |
US7304389B2 (en) | 2007-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7591067B2 (en) | Thermally enhanced coreless thin substrate with embedded chip and method for manufacturing the same | |
US7656015B2 (en) | Packaging substrate having heat-dissipating structure | |
US6985362B2 (en) | Printed circuit board and electronic package using same | |
JP3973340B2 (ja) | 半導体装置、配線基板、及び、それらの製造方法 | |
KR101058621B1 (ko) | 반도체 패키지 및 이의 제조 방법 | |
KR101077410B1 (ko) | 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법 | |
US10043726B2 (en) | Embedded component substrate with a metal core layer having an open cavity and pad electrodes at the bottom of the cavity | |
KR100630690B1 (ko) | 열 소산 경로를 구비한 멀티 칩 패키지 | |
JP4454181B2 (ja) | 半導体装置 | |
KR20070045929A (ko) | 전자 부품 내장 기판 및 그 제조 방법 | |
US7071569B2 (en) | Electrical package capable of increasing the density of bonding pads and fine circuit lines inside a interconnection | |
JPH07169872A (ja) | 半導体装置及びその製造方法 | |
KR20110085481A (ko) | 적층 반도체 패키지 | |
US8188379B2 (en) | Package substrate structure | |
US7489517B2 (en) | Die down semiconductor package | |
KR20070010915A (ko) | 방열층을 갖는 배선기판 및 그를 이용한 반도체 패키지 | |
US7714451B2 (en) | Semiconductor package system with thermal die bonding | |
US8957516B2 (en) | Low cost and high performance flip chip package | |
JP2006165320A (ja) | 半導体積層モジュールとその製造方法 | |
JP2008160019A (ja) | 電子部品 | |
US7304389B2 (en) | Semiconductor device and supporting plate | |
US20140118951A1 (en) | Interposer and package on package structure | |
KR100768998B1 (ko) | 다층인쇄회로기판을 사용한 범프접속형 칩실장모듈 | |
JP2004023103A (ja) | 高電圧bgaパッケージ、高電圧bgaパッケージ用ヒートスプレッダーの製造方法及び高電圧bgaパッケージ用ヒートスプレッダー | |
TW201603665A (zh) | 印刷電路板、用以製造其之方法及具有其之層疊封裝 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071120 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080118 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080318 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080514 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080624 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080707 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110711 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110711 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120711 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120711 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130711 Year of fee payment: 5 |
|
LAPS | Cancellation because of no payment of annual fees |