JP4149268B2 - リセット回路及びリセット方法 - Google Patents

リセット回路及びリセット方法 Download PDF

Info

Publication number
JP4149268B2
JP4149268B2 JP2002580146A JP2002580146A JP4149268B2 JP 4149268 B2 JP4149268 B2 JP 4149268B2 JP 2002580146 A JP2002580146 A JP 2002580146A JP 2002580146 A JP2002580146 A JP 2002580146A JP 4149268 B2 JP4149268 B2 JP 4149268B2
Authority
JP
Japan
Prior art keywords
reset
signal
clock
circuit
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002580146A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004524631A (ja
Inventor
ルネ、イエンセン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips NV, Koninklijke Philips Electronics NV filed Critical Koninklijke Philips NV
Publication of JP2004524631A publication Critical patent/JP2004524631A/ja
Application granted granted Critical
Publication of JP4149268B2 publication Critical patent/JP4149268B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Debugging And Monitoring (AREA)
JP2002580146A 2001-04-05 2002-04-05 リセット回路及びリセット方法 Expired - Fee Related JP4149268B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/826,570 US6529053B2 (en) 2001-04-05 2001-04-05 Reset circuit and method therefor
PCT/IB2002/001096 WO2002082246A2 (en) 2001-04-05 2002-04-05 Reset circuit and method therefor

Publications (2)

Publication Number Publication Date
JP2004524631A JP2004524631A (ja) 2004-08-12
JP4149268B2 true JP4149268B2 (ja) 2008-09-10

Family

ID=25246920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002580146A Expired - Fee Related JP4149268B2 (ja) 2001-04-05 2002-04-05 リセット回路及びリセット方法

Country Status (6)

Country Link
US (1) US6529053B2 (enExample)
EP (1) EP1379937B1 (enExample)
JP (1) JP4149268B2 (enExample)
AT (1) ATE493696T1 (enExample)
DE (1) DE60238750D1 (enExample)
WO (1) WO2002082246A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611158B2 (en) * 2001-07-24 2003-08-26 Koninklijke Philips Electronics N.V. Method and system using a common reset and a slower reset clock
US6762632B1 (en) 2003-05-15 2004-07-13 Stmicroelectronics, Inc. Reset driver circuits and methods
US7098557B2 (en) * 2003-05-15 2006-08-29 Stmicroelectronics, Inc. Constant voltage discharge device
US7081780B2 (en) * 2004-06-01 2006-07-25 Randall Don Briggs Reset circuitry for an integrated circuit
US8258844B2 (en) * 2006-08-03 2012-09-04 Seagate Technology Llc System-wide reset of multiple electronic devices
CN100498649C (zh) * 2007-03-28 2009-06-10 威盛电子股份有限公司 复位系统及复位方法
JP5159470B2 (ja) * 2008-06-27 2013-03-06 富士通テン株式会社 信号処理装置および信号処理方法
EP2596412B1 (en) 2010-07-20 2018-01-03 NXP USA, Inc. Electronic circuit, safety critical system, and method for providing a reset signal
US9712153B1 (en) 2016-03-03 2017-07-18 Nxp Usa, Inc. Method and device for reset modification based on system state

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967377A (en) 1981-12-10 1990-10-30 Canon Kabushiki Kaisha Control system using computers and having an initialization function
US5510740A (en) * 1993-04-21 1996-04-23 Intel Corporation Method for synchronizing clocks upon reset
US5371417A (en) * 1993-07-02 1994-12-06 Tandem Computers Incorporated Multiple frequency output clock generator system
JP3684590B2 (ja) * 1994-04-25 2005-08-17 カシオ計算機株式会社 リセット制御装置及びリセット制御方法
US5887146A (en) * 1995-08-14 1999-03-23 Data General Corporation Symmetric multiprocessing computer with non-uniform memory access architecture
DE19631066A1 (de) 1996-08-01 1998-02-05 Bosch Gmbh Robert Brennstoffeinspritzventil
US6480967B1 (en) * 1999-05-21 2002-11-12 Koninklijke Philips Electronics N.V. Multiple module processing system with reset system independent of reset characteristics of the modules

Also Published As

Publication number Publication date
ATE493696T1 (de) 2011-01-15
WO2002082246A2 (en) 2002-10-17
US20020145454A1 (en) 2002-10-10
JP2004524631A (ja) 2004-08-12
EP1379937A2 (en) 2004-01-14
WO2002082246A3 (en) 2002-12-12
EP1379937B1 (en) 2010-12-29
DE60238750D1 (enExample) 2011-02-10
US6529053B2 (en) 2003-03-04

Similar Documents

Publication Publication Date Title
CN100373288C (zh) 无假信号的时钟选择电路
US6784699B2 (en) Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time
JP5317356B2 (ja) クロック制御信号生成回路、クロックセレクタ、及び情報処理装置
KR960015134A (ko) 전력 관리상태에 응답하여 다중 클럭된 회로를 클럭하는 클럭 제어기
KR100607535B1 (ko) 프로세싱 시스템 및 다수의 프로세싱 모듈 리셋 방법
US8627132B2 (en) Autonomous multi-device event synchronization and sequencing technique eliminating master and slave assignments
US5862373A (en) Pad cells for a 2/N mode clocking scheme
JP4149268B2 (ja) リセット回路及びリセット方法
EP1415217B1 (en) Method and system using a common reset and a slower reset clock
EP1335268A2 (en) Glitchless clock selection circuit
KR20160143159A (ko) 데이터 복원을 안정적으로 제어하는 파워 게이팅 제어 회로
US6023770A (en) Semiconductor device
US6586969B1 (en) Method and system for synchronously initializing digital logic circuits
US5583893A (en) Method and apparatus for safely suspending and resuming operation of an electronic device
US8090929B2 (en) Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes
CN1954492B (zh) 在存在抖动时钟源时使时钟发生器同步的方法和装置
JP4750505B2 (ja) クロック切り換え回路
JP2836245B2 (ja) チップ内クロックの同期化方式
JP2018180963A (ja) 情報処理装置
JPH04365110A (ja) クロック停止回路
JP2000163155A (ja) データ処理回路
JP2722920B2 (ja) クロック発振停止制御回路
JPH0512461A (ja) クロツク供給回路
JPH06324757A (ja) 電子機器
JPH11202967A (ja) 半導体集積回路及びクロックカウンタの同期方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050404

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070511

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070518

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070814

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071005

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20071228

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080110

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080527

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080625

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110704

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110704

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110704

Year of fee payment: 3

R360 Written notification for declining of transfer of rights

Free format text: JAPANESE INTERMEDIATE CODE: R360

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110704

Year of fee payment: 3

R370 Written measure of declining of transfer procedure

Free format text: JAPANESE INTERMEDIATE CODE: R370

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110704

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110704

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110704

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120704

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130704

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees