Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/24—Resetting means

Definitions

• modules To contain and potentially shorten the design and development cycle time for large-scale systems, previously designed components, or modules, are commonly used. Such modules, having been designed for systems having differing reset requirements, often have differing clock and timing constraints. Some modules, for example, employ an asynchronous reset scheme, a synchronous reset scheme or a mix of both. Others employ a positive-edge- triggered clocking scheme, a negative-edge-triggered clocking scheme, a level sensitive scheme, a multi-phased scheme, and so on. In like manner, the convention used for resetting each module may differ. For each module, the reset strategy employed introduces timing constraints relative to the particular clocking scheme employed.
• a reset circuit is adapted to reset a plurality of circuit modules in a manner that addresses problems including those discussed in the Background hereinabove.
• the reset circuit includes a reset module adapted to generate a reset signal, a clock module and a plurality of synchronization modules.
• the clock module has an external clock reference and at least one clock module output for each of the plurality of circuit modules.
• a plurality of circuit modules adapted to enable internal resets in response to a reset signal are reset using a method that addresses problems including those discussed in the Background hereinabove.
• a reset signal is generated, and a reset clock signal having a frequency of an external clock reference is sent to each circuit module in response to the generated reset signal.
• the reset signal is synchronized to the reset clock signal for each circuit module, and the synchronized reset signal is to reset each circuit module. When the reset is disabled, each circuit module releases its internal reset almost simultaneously.
• FIG. 1 is a flow diagram for a circuit reset, according to an example embodiment of the present invention
• FIG. 2 is a timing diagram for a circuit reset, according to another example embodiment of the present invention
• FIG. 3 is a reset circuit, according to another example embodiment of the present invention
• Each of the circuit modules includes a synchronization module adapted to synchronize the reset signal among all circuit modules using the clock signal received from the clock module.
• the clock module holds the reset clock signal for a selected amount of time, and then releases the signal from the external clock. The reset signals are then simultaneously released at each of the circuit modules.
• FIG. 2 shows a timing diagram for an electronic system, according to another example embodiment of the present invention.
• Module clock cycles are shown as curve 210, and at clock cycle 212, power Vdd (curve 220) is applied to the system.
• An external reset input, reset_in_n is asserted, shown at curve 230, and held for 1ms.
• the reset input causes assertion of a peripheral reset, peri_rst_n, to the clock module and the circuit modules, shown as curve 240.
• peri_rst_n When peri_rst_n is asserted, the clock module enables an external clock on module clock outputs to the circuit modules, or peripheral devices.
• the external clock is used to apply a synchronized internal reset, mod int_rst_n, at each circuit module, shown by curve 250, using the peri_rst_n signal and the external clock signal.
• the reset_in_n signal is de-asserted at node 232
• the peri_rst_n signal is subsequently de- asserted after one clock cycle at node 242. All circuit modules release their internal resets synchronously, or nearly simultaneously, at node 252, which improves the ability to effect a safe transfer to system boot.
• the external clock remains asserted for a selected period, and the clock module then switches to a functional clock for each module after the reset has been released.
• the functional clock may, for example, include a clock signal having a particular frequency and phase related to requirements at each circuit module and overall system timing constraints.
• the selected period for which the external clock is asserted is effected via a register in the clock module that is programmed to hold the external clock for a number of clock cycles.
• the reset_in_n signal is de-asserted, software in the register operates to switch the clocks from the reference clock to the functional clocks for each circuit module.
• the switch is effected after a number of clock cycles that allows the internal resets to be released before the switch is made.
• the internal reset at each circuit module is released two clock cycles after peri_rst_n is de- asserted.
• the clock module 320 includes clock outputs clkl (item 322), clk2 (item 324), clk3 (item 326) and clkn (item 327) adapted to send a clock signal to each of the peripheral devices.
• FIG. 3 shows three peripheral devices and four clock outputs, the system 300 is adaptable to accommodate additional peripheral devices up to an "N" number of devices, as well as clock outputs for each of the peripheral devices, as indicated by dashed lines.
• Each of the peripheral devices 330, 332 and 334 include synchronization modules 340, 342 and 344, respectively, each having at least one input port adapted to receive the clock outputs, and an input port adapted to receive the reset signal 314.
• Synchronization module 340 receives clock output clkl and clk2;
• module 342 receives clock output clk3 and
• module 344 receives clock output clkn.
• the synchronization modules use the clock outputs and the reset signal to generate internal reset signals 350, 351, 352 and 353.
• Each internal reset signal is synchronized such that each peripheral device is reset using the same clock input, and thus, each device is released from reset nearly simultaneously when the reset is disabled.
• FIG. 4A and FIG. 4B show example synchronizers adapted to be used in connection with a reset circuit, such as that described in connection with FIG. 3, according to another example embodiment of the present invention.
• the synchronizer 410 in FIG. 4A is adapted to generate a reset signal asynchronously
• the synchronizer 460 in FIG. 4B is adapted to generate a reset signal synchronously. Both devices are adapted to effect synchronous de-assertion of a reset at a peripheral device.
• reset input signal 414 is received at flip-flop 420 and at AND gate 440.
• a clock signal 416 cycles the flip-flop 420 and the reset input signal is provided to flip-flop 430.
• the clock signal 416 cycles flip-flop 430, and the reset input signal from the flip-flop is provided to AND gate 440, which in turn provides an internal reset signal 418 to the peripheral device for which the synchronizer is used.
• synchronizer 460 receives a reset input signal 464 at flip-flop 470, which cycles according to a clock signal 466.
• the reset signal is provided to flip-flop 480, which is also responsive to the clock signal 466.
• Flip-flop 480 is cycled and provides an internal reset signal 468 to the peripheral device for which the synchronizer is used.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Electronic Switches (AREA)
• Debugging And Monitoring (AREA)

Priority Applications (4)

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Publications (2)

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• 2001
  • 2001-04-05 US US09/826,570 patent/US6529053B2/en not_active Expired - Lifetime
• 2002
  • 2002-04-05 WO PCT/IB2002/001096 patent/WO2002082246A2/en not_active Ceased
  • 2002-04-05 DE DE60238750T patent/DE60238750D1/de not_active Expired - Lifetime
  • 2002-04-05 AT AT02724495T patent/ATE493696T1/de not_active IP Right Cessation
  • 2002-04-05 EP EP02724495A patent/EP1379937B1/en not_active Expired - Lifetime
  • 2002-04-05 JP JP2002580146A patent/JP4149268B2/ja not_active Expired - Fee Related

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