JP4134893B2 - Electronic device package - Google Patents

Electronic device package Download PDF

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Publication number
JP4134893B2
JP4134893B2 JP2003407232A JP2003407232A JP4134893B2 JP 4134893 B2 JP4134893 B2 JP 4134893B2 JP 2003407232 A JP2003407232 A JP 2003407232A JP 2003407232 A JP2003407232 A JP 2003407232A JP 4134893 B2 JP4134893 B2 JP 4134893B2
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Prior art keywords
electronic device
substrate
device package
container member
adhesive
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JP2005167129A (en
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和司 東
伸治 石谷
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2003407232A priority Critical patent/JP4134893B2/en
Priority to CNB2004800360904A priority patent/CN100440490C/en
Priority to PCT/JP2004/017931 priority patent/WO2005055317A1/en
Priority to US10/581,792 priority patent/US7692292B2/en
Priority to CN200810169256XA priority patent/CN101369560B/en
Publication of JP2005167129A publication Critical patent/JP2005167129A/en
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Publication of JP4134893B2 publication Critical patent/JP4134893B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Description

本発明は、密閉された内部空間に電子素子を備える電子素子パッケージに関する。   The present invention relates to an electronic device package including an electronic device in a sealed internal space.

従来より、半導体素子、弾性表面波素子、その他様々な電子素子を、大気中に存在する水分や酸素等の影響から守る一手法として、容器の内部に電子素子を収納し、容器内部を密閉して電子素子を封止する技術が知られている。   Conventionally, as a method of protecting semiconductor elements, surface acoustic wave elements, and other various electronic elements from the effects of moisture, oxygen, etc. existing in the atmosphere, the electronic elements are stored inside the container and the container is sealed. A technique for sealing an electronic element is known.

このような電子素子を内部空間に配置して封止した電子素子デバイスとして、特許文献１に例示されるように、容器の密閉に樹脂の接着剤が用いられることがある。特許文献１では、半導体加速度センサにおいて、端子板をハウジングの外部に導出するための切り欠き溝を接着剤で封止した後にハウジングの内部を脱気し、脱気用の封止孔を熱圧着してセンサチップを封止する技術が開示されている。なお、容器が金属製の場合には、容器を構成する部材同士の接合および封止にはんだが用いられることもある。   As an electronic element device in which such an electronic element is disposed and sealed in an internal space, a resin adhesive may be used to seal the container, as exemplified in Patent Document 1. In Patent Document 1, in a semiconductor acceleration sensor, a notch groove for leading a terminal plate to the outside of the housing is sealed with an adhesive, and then the inside of the housing is deaerated, and a deaeration sealing hole is thermocompression bonded. Thus, a technique for sealing the sensor chip is disclosed. In addition, when a container is metal, a solder may be used for joining and sealing of the members which comprise a container.

一方、フリップチップボンディングにより搭載された電子素子と基板との空隙を密閉して電子素子を封止する技術も利用されている。例えば、特許文献２では、弾性表面波装置の製造において、基板上の複数の弾性表面波素子に対して樹脂を２段階に分けて塗布することにより、気泡の噛み込みを抑制しつつ粘性の高い樹脂により弾性表面波素子を封止する技術が開示されている。特許文献３では、表面弾性波デバイスの製造において、パッケージ基板上にフリップチップ接続された表面弾性波チップを低融点ガラスにより封止する技術が開示されている。
特開平１１−２３７４０１号公報 特開２００３−１４２９７２号公報 特開２００３−１１０４０２号公報 On the other hand, a technique for sealing an electronic element by sealing a gap between the electronic element mounted by flip chip bonding and the substrate is also used. For example, in Patent Document 2, in the production of a surface acoustic wave device, a resin is applied in a two-stage manner to a plurality of surface acoustic wave elements on a substrate, thereby suppressing the biting of bubbles and having a high viscosity. A technique for sealing a surface acoustic wave element with a resin is disclosed. Patent Document 3 discloses a technique for sealing a surface acoustic wave chip flip-chip connected to a package substrate with a low-melting glass in manufacturing a surface acoustic wave device.
JP-A-11-237401 JP 2003-142972 A JP 2003-110402 A

ところで、樹脂は水分や酸素に対する気密性の程度が余り高くないため、封止材として樹脂を用いると電子素子の種類によっては適正な封止（または、パッケージ化）が実現されない場合がある。一方、特許文献３に開示されているように低融点ガラスにより封止したり、あるいは、容器を構成する部材をはんだにて接合する場合は、高い気密性（密閉性）を得ることができる反面、高温で低融点ガラスやはんだを溶融するための加熱処理が必要となり、耐熱性の低い電子素子の封止には適していない。特に、化合物半導体等の電子素子は耐熱性が低いため、高温加熱により損傷する可能性が高い。   By the way, since the degree of airtightness with respect to moisture and oxygen is not so high, proper sealing (or packaging) may not be realized depending on the type of electronic element when the resin is used as a sealing material. On the other hand, when it is sealed with low melting point glass as disclosed in Patent Document 3 or when the members constituting the container are joined with solder, high airtightness (sealing property) can be obtained. Heat treatment for melting low melting glass or solder at a high temperature is required, and it is not suitable for sealing an electronic element having low heat resistance. In particular, electronic devices such as compound semiconductors have low heat resistance, and thus are highly likely to be damaged by high-temperature heating.

本発明は、上記課題に鑑みなされたものであり、電子素子パッケージにおいて電子素子を低温（好ましくは１５０℃以下）にて密閉空間に収納するとともに密閉空間の気密性を向上することを目的としている。   The present invention has been made in view of the above-described problems, and an object of the present invention is to accommodate an electronic element in an electronic element package in a sealed space at a low temperature (preferably 150 ° C. or lower) and improve the airtightness of the sealed space. .

請求項１に記載の発明は、電子素子パッケージであって、電子素子と、前記電子素子が収納される空間を形成する第１の容器部材および第２の容器部材と、樹脂を主成分とし、前記第１の容器部材と前記第２の容器部材とを接着して前記空間を密閉する接着剤と、前記接着剤の外側の表面を覆う金属膜とを備え、 前記電子素子が前記第１の容器部材に実装され、前記第２の容器部材が樹脂により形成され、前記第１の容器部材が平坦な部材であり、前記第２の容器部材は前記第１の容器部材を覆う凹部を有し、前記凹部の縁に前記空間側へ向いて形成された鍔部は前記接着剤を介して前記第１の容器部材に接着され、前記第２の容器部材の外側の表面も金属膜により覆われていることを特徴とする電子素子パッケージを備える。 Invention of Claim 1 is an electronic element package, Comprising: The electronic element, The 1st container member and 2nd container member which form the space in which the said electronic element is accommodated, Resin as a main component, An adhesive that adheres the first container member and the second container member to seal the space; and a metal film that covers an outer surface of the adhesive; and the electronic device includes the first element. Mounted on a container member, the second container member is formed of resin, the first container member is a flat member, and the second container member has a recess that covers the first container member. The flange formed on the edge of the recess toward the space is bonded to the first container member via the adhesive, and the outer surface of the second container member is also covered with a metal film. an electronic device package, characterized in that is.

請求項２に記載の発明は、請求項１に記載の電子素子パッケージであって、前記金属膜がメッキ層である。   A second aspect of the present invention is the electronic device package according to the first aspect, wherein the metal film is a plating layer.

請求項３に記載の発明は、請求項２に記載の電子素子パッケージであって、前記接着剤が、金属粒子を含む。   A third aspect of the present invention is the electronic device package according to the second aspect, wherein the adhesive includes metal particles.

請求項４に記載の発明は、請求項１ないし３のいずれかに記載の電子素子パッケージであって、前記電子素子が半導体素子である。   A fourth aspect of the present invention is the electronic element package according to any one of the first to third aspects, wherein the electronic element is a semiconductor element.

請求項５に記載の発明は、請求項１ないし４のいずれかに記載の電子素子パッケージであって、前記空間内に吸湿剤をさらに備える。 The invention according to claim 5 is the electronic device package according to any one of claims 1 to 4 , further comprising a hygroscopic agent in the space.

本発明では、低温にて第１の容器部材と第２の容器部材とを接着して電子素子を密閉空間に収納することができるとともに密閉空間の気密性を向上することができる。   In the present invention, the first container member and the second container member can be bonded at a low temperature so that the electronic element can be stored in the sealed space, and the airtightness of the sealed space can be improved.

請求項２および１１の発明では、金属膜を容易に形成することができる。   In the inventions of claims 2 and 11, the metal film can be easily formed.

請求項３の発明では、金属膜をより容易に形成することができる。   In the invention of claim 3, the metal film can be formed more easily.

請求項５ないし８の発明では、電子素子パッケージの製造コストを削減することができ、請求項６および８の発明では、密閉空間の信頼性を向上することができる。   In the inventions of claims 5 to 8, the manufacturing cost of the electronic device package can be reduced, and in the inventions of claims 6 and 8, the reliability of the sealed space can be improved.

請求項９および１２の発明では、電子素子パッケージの内部の空間を確実に除湿することができる。   In the ninth and twelfth aspects of the present invention, it is possible to reliably dehumidify the space inside the electronic element package.

図１は、本発明の一の実施の形態に係る電子素子パッケージ１の構成を示す断面図である。電子素子パッケージ１は、内部に電子素子である半導体素子７１が封止されたパッケージ（すなわち、電子素子を密閉空間内に設けてパッケージ化したもの）であり、平坦な基板９、基板９上に実装される半導体素子７１、並びに、半導体素子７１の側方および上方（基板９とは反対側）を囲むように基板９に取り付けられることにより半導体素子７１が収納される空間（以下、「内部空間」という。）９０を基板９と共に形成するカバー部材２を備える。   FIG. 1 is a cross-sectional view showing a configuration of an electronic element package 1 according to an embodiment of the present invention. The electronic element package 1 is a package in which a semiconductor element 71 as an electronic element is sealed (that is, a package in which an electronic element is provided in a sealed space). The semiconductor element 71 to be mounted, and a space in which the semiconductor element 71 is accommodated by being attached to the substrate 9 so as to surround the side and upper side (the side opposite to the substrate 9) of the semiconductor element 71 (hereinafter referred to as “internal space”). The cover member 2 which forms 90 with the board | substrate 9 is provided.

基板９は、半導体素子７１が実装される側の主面、および、その裏面（内部空間９０とは反対側の面）に電極等が形成された多層基板であり、低温焼成セラミック（以下、「ＬＴＣＣ（Low Temperature Cofired Ceramics）」という。）により形成され、通常のセラミック（ＬＴＣＣと区別するために、以下、「ＨＴＣＣ（High Temperature Cofired Ceramics）」という。）製の基板とは形成プロセスを異にする。   The substrate 9 is a multilayer substrate in which electrodes and the like are formed on the main surface on which the semiconductor element 71 is mounted and the back surface (the surface opposite to the internal space 90). LTCC (Low Temperature Cofired Ceramics) ”), and the formation process is different from a substrate made of normal ceramics (hereinafter referred to as“ HTCC (High Temperature Cofired Ceramics) ”). To do.

半導体素子７１は、いわゆるベアＩＣチップであり、半導体素子７１の下面のランド上に形成された金属のバンプ７２が基板９上の電極に電気的に接合されることにより基板９に実装される。基板９の表裏両面の電極は適宜互いに電気的に接続されており、電子素子パッケージ１が基板９側から他の外部基板に実装されることにより、外部基板と半導体素子７１とが電気的に接続される。   The semiconductor element 71 is a so-called bare IC chip, and is mounted on the substrate 9 by electrically bonding metal bumps 72 formed on lands on the lower surface of the semiconductor element 71 to electrodes on the substrate 9. The electrodes on both the front and back surfaces of the substrate 9 are appropriately electrically connected to each other, and the electronic device package 1 is mounted on the other external substrate from the substrate 9 side, so that the external substrate and the semiconductor element 71 are electrically connected. Is done.

カバー部材２はプラスチック等の樹脂により器状に形成され、カバー部材２の凹部２３が基板９を覆うようにして基板９に取り付けられることにより、内部空間９０が形成される。カバー部材２の凹部２３の縁には基板９に沿って内側に向かう鍔部２１が形成されている。   The cover member 2 is formed into a container shape with a resin such as plastic, and the concave portion 23 of the cover member 2 is attached to the substrate 9 so as to cover the substrate 9, thereby forming an internal space 90. On the edge of the recess 23 of the cover member 2, a flange 21 is formed inward along the substrate 9.

電子素子パッケージ１では、基板９とカバー部材２の鍔部２１とが、熱硬化性樹脂を主成分とするとともに銀（Ａｇ）の粒子（銅（Ｃｕ）等の他の金属粒子であってもよい。）を含む接着剤３（いわゆる、銀ペースト）を介して接着されて内部空間９０が密閉される。また、接着剤３およびカバー部材２の外側の表面は、ニッケル（Ｎｉ）および金（Ａｕ）（他の金属であってもよい。）の被膜４により覆われる。さらに、内部空間９０にはカバー部材２に取り付けられた吸湿剤２２（例えば、酸化マグネシウム）が設けられる。   In the electronic device package 1, the substrate 9 and the flange portion 21 of the cover member 2 may be composed of thermosetting resin as a main component and other metal particles such as silver (Ag) particles (copper (Cu)). The internal space 90 is hermetically sealed with an adhesive 3 (so-called silver paste) containing the adhesive. The outer surfaces of the adhesive 3 and the cover member 2 are covered with a coating 4 of nickel (Ni) and gold (Au) (may be other metals). Furthermore, a moisture absorbent 22 (for example, magnesium oxide) attached to the cover member 2 is provided in the internal space 90.

図２は、電子素子パッケージ１の製造工程を示す図である。電子素子パッケージ１が製造される際には、まず、半導体素子７１が基板９上の所定の実装位置に載置され、バンプ７２と基板９の電極とが当接した状態で、半導体素子７１が基板９に向かって押圧されつつ超音波振動が付与されることにより、バンプ７２と電極とが接合されて基板９に実装される（ステップＳ１１）。半導体素子７１の実装は他の手法により行われてもよく、例えば、異方導電性樹脂フィルム（またはペースト）や非導電性樹脂フィルム（またはペースト）を介して行われてもよい。さらには、バンプ７２および基板９の電極にエネルギー波を照射して真空中で接合する、いわゆる、常温接合が採用されてもよい。なお、バンプ７２は基板９の電極上に形成されていてもよい。実装される半導体素子７１（後述のようにその他の電子素子であってもよい。）の個数は複数であってもよい。   FIG. 2 is a diagram illustrating a manufacturing process of the electronic element package 1. When the electronic element package 1 is manufactured, first, the semiconductor element 71 is placed at a predetermined mounting position on the substrate 9, and the semiconductor element 71 is in a state where the bump 72 and the electrode of the substrate 9 are in contact with each other. By applying ultrasonic vibration while being pressed toward the substrate 9, the bumps 72 and the electrodes are joined and mounted on the substrate 9 (step S11). The mounting of the semiconductor element 71 may be performed by other methods, for example, via an anisotropic conductive resin film (or paste) or a non-conductive resin film (or paste). Further, so-called room temperature bonding may be employed in which the bumps 72 and the electrodes of the substrate 9 are irradiated with energy waves and bonded in vacuum. The bump 72 may be formed on the electrode of the substrate 9. There may be a plurality of semiconductor elements 71 (other electronic elements may be used as described later) to be mounted.

続いて、カバー部材２の内側であって基板９に取り付けられた際に基板９と対向する面（すなわち、凹部２３の底面）に吸湿剤２２が取り付けられる（ステップＳ１２）。その後、基板９上のカバー部材２が接着される接着位置（および／または、カバー部材２の鍔部２１の基板９に対向する面）に接着剤３が塗布され、カバー部材２が接着剤３を介して基板９に取り付けられる。カバー部材２が取り付けられた基板９は比較的低温な１５０℃以下（好ましくは、約１２０℃〜１３０℃）にて加熱処理され、接着剤３が硬化し、基板９とカバー部材２とが接着されて内部空間９０が密閉される（ステップＳ１３）。これにより、内部空間９０が吸湿剤２２により確実に除湿され、耐湿信頼性が向上する。   Subsequently, the hygroscopic agent 22 is attached to the inner surface of the cover member 2 and the surface facing the substrate 9 when attached to the substrate 9 (that is, the bottom surface of the recess 23) (step S12). Thereafter, the adhesive 3 is applied to the bonding position (and / or the surface of the collar portion 21 of the cover member 2 facing the substrate 9) where the cover member 2 is bonded on the substrate 9, and the cover member 2 is bonded to the adhesive 3 It is attached to the substrate 9 via The substrate 9 to which the cover member 2 is attached is heated at a relatively low temperature of 150 ° C. or less (preferably about 120 ° C. to 130 ° C.), the adhesive 3 is cured, and the substrate 9 and the cover member 2 are bonded. Thus, the internal space 90 is sealed (step S13). As a result, the internal space 90 is reliably dehumidified by the moisture absorbent 22, and the moisture resistance reliability is improved.

また、カバー部材２の鍔部２１と基板９とが接着されるため、鍔部２１がない場合に比べて接着される面積が大きく、基板９とカバー部材２との接合がより安定する。その結果、内部空間９０の密閉の信頼性が向上される。なお、鍔部２１は凹部２３の外側を向くように形成されてもよい。   Moreover, since the collar part 21 and the board | substrate 9 of the cover member 2 are adhere | attached, the area to adhere | attach is large compared with the case where there is no collar part 21, and joining of the board | substrate 9 and the cover member 2 becomes more stable. As a result, the reliability of sealing the internal space 90 is improved. The flange 21 may be formed so as to face the outside of the recess 23.

次に、基板９の裏面（内部空間９０とは反対側の主面）の少なくとも電極部分がマスク材により被覆された後、電子素子パッケージ１に無電解メッキが施され、ニッケルメッキ層および金メッキ層（以下、「メッキ層」と総称する。）が順次形成されて電子素子パッケージ１（およびマスク材）の表面が覆われる。 電子素子パッケージ１では、無電解メッキを利用することメッキ層である金属膜を容易に形成することができる。さらに、接着剤３に銀粒子が含まれているため、接着剤３の外側の表面においてニッケルメッキ層が安定して成長しやすく（メッキが乗りやすく）、金属膜をより容易に形成することができる。   Next, after at least an electrode portion of the back surface (main surface opposite to the internal space 90) of the substrate 9 is covered with a mask material, the electronic element package 1 is subjected to electroless plating, and a nickel plating layer and a gold plating layer (Hereinafter collectively referred to as “plated layer”) are formed in sequence to cover the surface of the electronic element package 1 (and the mask material). In the electronic element package 1, a metal film as a plating layer can be easily formed by using electroless plating. Furthermore, since silver particles are contained in the adhesive 3, the nickel plating layer is likely to grow stably on the outer surface of the adhesive 3 (easy to be plated), and a metal film can be more easily formed. it can.

電子素子パッケージ１のメッキが終了すると、電子素子パッケージ１からマスク材が除去され、マスク材により被覆された部位以外の表面にのみメッキ層が残されることによりニッケルおよび金により形成される被膜４を有する電子素子パッケージ１の製造が完了する（ステップＳ１４）。   When the plating of the electronic element package 1 is completed, the mask material is removed from the electronic element package 1, and the coating 4 formed of nickel and gold is formed by leaving the plating layer only on the surface other than the portion covered with the mask material. The manufacture of the electronic device package 1 is completed (step S14).

以上に説明したように、電子素子パッケージ１では、低温（通常のはんだやガラスパウダー接合に比べて低温であり、好ましくは、１５０℃以下）にて硬化する接着剤３により基板９とカバー部材２とが接着され、半導体素子７１が収納された内部空間９０が密閉される。その結果、耐熱性の低い半導体素子７１であっても熱による損傷を与えることなく低温にて密閉空間内に収納することができる。また、セラミックや金属等に比べて耐熱性の低い安価な樹脂製のカバー部材２を使用することができ、電子素子パッケージ１の製造コストを削減することができる。   As described above, in the electronic device package 1, the substrate 9 and the cover member 2 are bonded by the adhesive 3 that is cured at a low temperature (lower temperature than normal solder or glass powder bonding, preferably 150 ° C. or less). And the internal space 90 containing the semiconductor element 71 is sealed. As a result, even the semiconductor element 71 having low heat resistance can be stored in the sealed space at a low temperature without being damaged by heat. In addition, an inexpensive resin cover member 2 having lower heat resistance than ceramic or metal can be used, and the manufacturing cost of the electronic element package 1 can be reduced.

電子素子パッケージ１では、接着剤３の外側の表面が金属の被膜４に覆われるため、水分等が接着剤３を通過して内部空間９０に浸入することが防止され、樹脂を主成分とする接着剤３の表面が外気中に露出している場合に比べて内部空間９０の気密性を向上することができる。また、樹脂製のカバー部材２の外側の表面も金属の被膜４にて覆われるため、ピンホールのない高い信頼性にて密閉された内部空間９０が実現される。   In the electronic device package 1, the outer surface of the adhesive 3 is covered with the metal coating 4, so that moisture or the like is prevented from passing through the adhesive 3 and entering the internal space 90, and the resin is a main component. The airtightness of the internal space 90 can be improved compared to the case where the surface of the adhesive 3 is exposed to the outside air. In addition, since the outer surface of the resin cover member 2 is also covered with the metal film 4, a highly reliable sealed internal space 90 without a pinhole is realized.

また、電子素子パッケージ１では、平坦な基板９上に実装された半導体素子７１が凹部２３を備える（凹状であることを含む。）カバー部材２により密封されるため、基板９にキャビティ（凹部）を形成する工程を省略することができ、電子素子パッケージ１の製造コストを削減することができる。特に、ＨＴＣＣに比べてキャビティの形成にコストを要するＬＴＣＣ製の基板９を用いる場合に、電子素子パッケージ１の製造コストを大きく削減することができる。   Further, in the electronic element package 1, the semiconductor element 71 mounted on the flat substrate 9 is sealed by the cover member 2 including the recess 23 (including the recess), and therefore, the substrate 9 has a cavity (recess). The process of forming can be omitted, and the manufacturing cost of the electronic element package 1 can be reduced. In particular, when an LTCC substrate 9 that requires a cost for forming a cavity as compared with HTCC is used, the manufacturing cost of the electronic device package 1 can be greatly reduced.

以上、本発明の実施の形態について説明してきたが、本発明は上記実施の形態に限定されるものではなく、様々な変更が可能である。例えば、電子素子パッケージ１の製造終了時点において内部空間９０に存在するガスの水分含有量が十分に少ない場合には、吸湿剤２２は省略されてもよい。   Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the hygroscopic agent 22 may be omitted when the moisture content of the gas present in the internal space 90 is sufficiently small at the end of manufacturing the electronic element package 1.

カバー部材２は、製造コスト削減の観点からは樹脂により形成されることが好ましいが、金属やセラミック等の他の材料により形成されてもよい。基板９およびカバー部材２はそれぞれ、キャビティを有する基板（いわゆる、「キャビティ基板」）、および、キャビティの開口部を覆う平坦な蓋であってもよい。この場合であっても、基板９とカバー部材２とを接着剤３により接着し、接着剤３の外側の表面を金属の被膜４により覆うことにより、気密性の高い電子素子パッケージ１を低温にて製造することができる。   The cover member 2 is preferably formed of a resin from the viewpoint of manufacturing cost reduction, but may be formed of other materials such as metal or ceramic. Each of the substrate 9 and the cover member 2 may be a substrate having a cavity (so-called “cavity substrate”) and a flat lid that covers the opening of the cavity. Even in this case, the substrate 9 and the cover member 2 are bonded with the adhesive 3, and the outer surface of the adhesive 3 is covered with the metal coating 4, so that the highly airtight electronic element package 1 can be cooled to a low temperature. Can be manufactured.

電子素子パッケージ１の製造工程において加熱処理を極力避けたい場合には、光硬化性樹脂等の加熱処理なしに硬化する接着剤３が、基板９とカバー部材２との接着に用いられる。この場合であっても、被膜４が無電解メッキにより接着剤３の外側の表面に形成されて、内部空間９０の気密性が向上される。   When it is desired to avoid heat treatment as much as possible in the manufacturing process of the electronic element package 1, the adhesive 3 that cures without heat treatment such as a photocurable resin is used for bonding the substrate 9 and the cover member 2. Even in this case, the coating 4 is formed on the outer surface of the adhesive 3 by electroless plating, and the airtightness of the internal space 90 is improved.

被膜４の形成は、作業の容易性および製造コストの削減という観点から無電解メッキにより行われることが好ましいが、接着剤３として導電性接着剤を使用している場合には電解メッキにより行うことも可能である。また、スパッタにより金属の被膜４が形成されてもよい。   The formation of the coating 4 is preferably performed by electroless plating from the viewpoint of ease of work and reduction of manufacturing cost. However, when a conductive adhesive is used as the adhesive 3, it is performed by electrolytic plating. Is also possible. Moreover, the metal film 4 may be formed by sputtering.

本発明は、半導体素子以外の様々な種類の電子素子のパッケージに利用可能であり、耐熱性が低く、かつ、耐湿性も低い電子素子に対しても利用可能である。   The present invention can be used for packages of various types of electronic elements other than semiconductor elements, and can also be used for electronic elements having low heat resistance and low moisture resistance.

一の実施の形態に係る電子素子パッケージの構成を示す断面図Sectional drawing which shows the structure of the electronic element package which concerns on one embodiment 電子素子パッケージの製造工程を示す図Diagram showing manufacturing process of electronic device package

符号の説明Explanation of symbols

１ 電子素子パッケージ
２ カバー部材
３ 接着剤
４ 被膜
９ 基板
２１ 鍔部
２２ 吸湿剤
２３ 凹部
７１ 半導体素子
９０ 内部空間
Ｓ１１〜Ｓ１４ ステップ DESCRIPTION OF SYMBOLS 1 Electronic element package 2 Cover member 3 Adhesive 4 Coating 9 Substrate 21 Gutter part 22 Hygroscopic agent 23 Recessed part 71 Semiconductor element 90 Internal space S11-S14 Step

Claims (5)

電子素子パッケージであって、
電子素子と、
前記電子素子が収納される空間を形成する第１の容器部材および第２の容器部材と、
樹脂を主成分とし、前記第１の容器部材と前記第２の容器部材とを接着して前記空間を密閉する接着剤と、
前記接着剤の外側の表面を覆う金属膜と、
を備え、
前記電子素子が前記第１の容器部材に実装され、
前記第２の容器部材が樹脂により形成され、
前記第１の容器部材が平坦な部材であり、
前記第２の容器部材は前記第１の容器部材を覆う凹部を有し、前記凹部の縁に前記空間側へ向いて形成された鍔部は前記接着剤を介して前記第１の容器部材に接着され、
前記第２の容器部材の外側の表面も金属膜により覆われていることを特徴とする電子素子パッケージ。 An electronic device package,
An electronic element;
A first container member and a second container member forming a space in which the electronic element is stored;
An adhesive mainly composed of a resin, and seals the space by bonding the first container member and the second container member;
A metal film covering the outer surface of the adhesive;
With
The electronic element is mounted on the first container member;
The second container member is formed of resin;
The first container member is a flat member;
The second container member has a recess that covers the first container member, and a flange formed on the edge of the recess toward the space side is formed on the first container member via the adhesive. Glued ,
An electronic device package, wherein an outer surface of the second container member is also covered with a metal film . 請求項１に記載の電子素子パッケージであって、
前記金属膜がメッキ層であることを特徴とする電子素子パッケージ。 The electronic device package according to claim 1,
An electronic device package, wherein the metal film is a plating layer. 請求項２に記載の電子素子パッケージであって、
前記接着剤が、金属粒子を含むことを特徴とする電子素子パッケージ。 The electronic device package according to claim 2,
The electronic device package, wherein the adhesive contains metal particles. 請求項１ないし３のいずれかに記載の電子素子パッケージであって、
前記電子素子が半導体素子であることを特徴とする電子素子パッケージ。 The electronic device package according to any one of claims 1 to 3,
An electronic device package, wherein the electronic device is a semiconductor device. 請求項１ないし４のいずれかに記載の電子素子パッケージであって、
前記空間内に吸湿剤をさらに備えることを特徴とする電子素子パッケージ。 The electronic device package according to any one of claims 1 to 4 ,
An electronic device package, further comprising a hygroscopic agent in the space.
JP2003407232A 2003-12-05 2003-12-05 Electronic device package Expired - Fee Related JP4134893B2 (en)

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PCT/JP2004/017931 WO2005055317A1 (en) 2003-12-05 2004-12-02 Packaged electronic element and method of producing electronic element package
US10/581,792 US7692292B2 (en) 2003-12-05 2004-12-02 Packaged electronic element and method of producing electronic element package
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