JP2001110845A - Flip-chip packaging structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a flip-chip packaging structure, wherein a flip chip can be packaged in the packaging structure in almost the same occupation area as that of a semiconductor bare chip itself and at the same time, the flip chip can obtain a high reliability equal with that of the flip chip in the case where the flip chip is hermetically sealed in a package. SOLUTION: In a semiconductor bare chip of a flip chip main body, wall- shaped hermetic rings, which encircle an interface electrode being method on the surface of an active circuit on the bare chip and bump electrodes, are formed using a metal film capable of making a solid phase junction with the hermetic rings, ring lands of the same form as that of the hermetic rings are provided on the surface, which is mounted with this flip chip, of a substrate using a metal film capable of making a solid phase junction with the ring lands and the hermetic rings of the flip chip is made a solid phase junction with the ring lands on the substrate to hermetically seal a semiconductor bare chip single member.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding structure between a semiconductor bare chip and a substrate constituting an electronic circuit or an electronic component.

[0002]

2. Description of the Related Art A semiconductor bare chip is an active element formed by dividing a semiconductor wafer on which a desired circuit is formed. However, since the semiconductor wafer is a thin semiconductor plate, the shape of the semiconductor bare chip may be a thin rectangular parallelepiped. In many cases, an active circuit and an electrode as an external interface of the active circuit are also formed on one surface of the rectangular parallelepiped. In order for this semiconductor bare chip to function as one electronic component, electrodes formed two-dimensionally on the surface of the semiconductor bare chip and electrodes such as an external wiring board must be connected by some method. The method of making the connection is a wire bonding method in which one end of a fine metal wire is joined to a planar electrode formed on a semiconductor bare chip, and the opposite end is joined to an electrode such as an external wiring board. It is roughly classified into a flip chip method in which a bump is attached to a planar electrode and the bump is joined to an electrode such as an external wiring board. The bump is a word meaning a protruding shape, and refers to a connection terminal that protrudes slightly, unlike a connection terminal that is extended long like a lead.

[0003] The wire bonding method is also called face-up mounting because the semiconductor bare chip is attached to the wiring board in a direction in which the active circuits and electrodes formed on the semiconductor bare chip can be viewed. The flip chip method uses the active circuit and electrodes. It is called face-down mounting because the formed surface faces the wiring board side, and is also called bump mounting because bumps are used. The wire bond method requires a large occupation area larger than the occupation area of the semiconductor bare chip itself because a wire is stretched around the semiconductor bare chip, and the wires are stretched one by one, whereas in the case of the flip chip method, No special area is required for connection between the electrodes of the semiconductor bare chip and the electrodes of the wiring board, so the area required for mounting the semiconductor bare chip is almost equal to the occupied area of the semiconductor bare chip itself, and it is possible to use one surface. Since all the bumps are provided, the connection with the wiring board can be performed collectively. Therefore, the flip-chip method is the most suitable method for minimizing the occupation area required for mounting the semiconductor bare chip and achieving high-density mounting, miniaturizing the electronic device and shortening the construction period.

Conventionally, semiconductor bare chips are individually housed in a package and internally connected by wire bonding to connect leads and terminals derived from the package to electrodes of a wiring board. In general, high-density packaging has been promoted by arranging packaged semiconductor parts at high density and miniaturizing the package. As the number of pins and the pitch of package leads have reached a limit as the number of packages has increased, the presence of packages has become an obstacle to high-density packaging. Therefore, in order to achieve high-density mounting, it is inevitable to adopt a method of directly mounting a semiconductor bare chip having no external package on a wiring board, and as a mounting method of the semiconductor bare chip itself, a minimum occupied area is required. At the same time, attention has been focused on flip-chip mounting, which allows connection of a semiconductor bare chip and a substrate at once, and various flip-chip mounting methods have been proposed.

A bump-shaped electrode is generally referred to as a bump regardless of its shape or material, and various materials are available, such as gold, solders, and metal balls. There are also many types of bonding methods between the bumps and the external wiring board circuit. The flip-chip mounting methods can be broadly classified into three types: solid-phase bonding, soldering, and bonding. Therefore, it is selected according to factors such as application, device structure, processing man-hour, and price.

[0006] Solid-phase bonding is a method of directly bonding the same type of metal or different types of metal without using a bonding material such as solder or an adhesive, and is thermo-compression bonding or thermo-ultrasonic to which ultrasonic waves are applied. A method of mechanically joining various metals by crimping, where the surface of the metals to be joined is elastically and plastically deformed due to pressure or vibration, and the distance between the atoms of the metals to be joined is extremely large. This is a method of forming a metal bond by an interatomic force. This is a metal joining method in which no joining material is interposed and metals to be joined are not melted as in welding, so that a fragile intermetallic compound is not formed. Fine Au
A wire bonding method of bonding a wire or an Al wire to an electrode of a semiconductor bare chip is also one of the methods for performing the solid-phase bonding, and has a long history as a semiconductor connection technique and is a highly reliable connection technique. In Au wire bonding, generally, the tip of the wire is melted by a gas torch or electric discharge to form an Au ball, and the ball is solid-phase bonded to the electrode of the semiconductor bare chip, and the opposite end is the electrode of the substrate on which the semiconductor bare chip is attached. In the case where an Au bump is formed as a bump, an Au ball is solid-phase bonded to an electrode of a semiconductor bare chip by applying this ball bonding method, and then the wire is cut off. It can also be formed. Electrode material of semiconductor bare chip is generally Al or Au
Both Al and Au can be used for solid-state bonding of Au balls, and because of the application technology of the wire bonding method, they are used as a method for forming Au bumps relatively easily. I have.

In the case of the solder bump method and the copper ball method bump, any solder material is used in the process of forming a bump on a semiconductor bare chip. In the case of the adhesive method, a bump is formed on a semiconductor bare chip and then the bump is formed. There is a method of connecting the electrodes of the semiconductor bare chip and the electrodes of the substrate directly using a conductive adhesive, and a method of directly connecting the electrodes of the semiconductor bare chip and the electrodes of the substrate without bumps using an anisotropic conductive film. The connection material is obtained by adding conductive particles to the connection material, and has a relatively high connection resistance. In either method, since a bare semiconductor chip is used barely, at least its active circuit forming surface must be protected by some method so as not to be corroded by an active atmosphere or moisture. In addition, in some cases, other than corrosion prevention, it is necessary to take measures to prevent the bump junction from being broken due to a temperature change or a mechanical shock, which may be different from the wire bonding method.

Means for protecting the active circuit formation surface of the semiconductor bare chip include a method of housing the entire flip chip in a package and hermetically sealing it, and a method of protecting a bump height between the flip chip and a substrate on which the flip chip is mounted. There is a method of filling the gap with a protective resin. A method of housing the entire flip chip in a package and hermetically sealing it is a method of protecting the active circuit forming surface of the semiconductor bare chip, which can completely block the outside air and directly touches the bump junction and the active circuit surface of the semiconductor bare chip Is the most reliable method because the inert gas and the vacuum are hermetically sealed and there is no substance causing corrosion, and the factor that generates stress is minimized. Even if the internal connection method does not require the same area as that of the wire bonding method, the area occupied by the semiconductor bare chip itself is not enough, and the flip chip original semiconductor bare chip can be mounted with the minimum occupied area. You will be alienated. There is also a means for hermetically sealing the entire circuit board in a package after forming a circuit board by arranging a plurality of flip chips, but the unit price of the package alone is expensive,
If a package is developed for a circuit, the development cost would be very high. Therefore, when performing flip-chip mounting, a package is hardly used to adopt a hermetically sealed structure.

[0009] The method of filling the gap between the semiconductor bare chip and the substrate with a protective resin and encapsulating the resin requires almost the same occupied area as the semiconductor bare chip itself, so that the original semiconductor bare chip for flip chip mounting is mounted with the minimum occupied area. On the other hand, it is a means where the advantage of being able to be achieved and the advantage that the material is inexpensive because of sealing by resin filling is exhibited,
It is difficult to fill the resin into narrow gaps, and it is impossible to completely prevent the resin from flowing out.Also, since the resin itself breathes, it is impossible to completely prevent the influence of the outside air In particular, infiltration of a very small amount of water is unavoidable.Moreover, the structure is such that the filling resin directly touches the bump connection part. This method also has many problems inherent in that circuit characteristics are distorted due to the influence of the dielectric constant of the protective resin as the frequency becomes higher.

A conventional flip chip mounting structure will be described with reference to the drawings. FIG. 10 is a cross-sectional view showing a mounting structure of a flip chip having a resin sealing structure, wherein 1 is a semiconductor bare chip, 2 is an interface electrode formed on an active circuit surface of the semiconductor bare chip 1, and 3 is attached to the interface electrode 2. A flip chip 4 is formed of the semiconductor bare chip 1 and the bump electrode 3. Reference numeral 5 denotes a bump land, and 7 denotes a sealing resin. Here, as a method of forming the bump electrode 3, as described above, an Au ball bump method to which Au wire bonding is applied, an Au plating stacking method in which Au plating is formed by thickening, or a method in which common solder is melted and formed. Any method such as a solder ball method, a method of plating a metal ball, and the like may be used.

By bonding the bump land 6 formed on the substrate 5 and the bump electrode 3, the flip chip 4 is electrically connected to the substrate 5 and also mechanically bonded and fixed. Although there are a plurality of combinations of the bump lands 6 and the bump electrodes 3, since both are on the same plane, the connection process can be performed by only one connection process for one flip chip 4. Can be connected collectively, and at the same time, the step of fixing the flip chip 4 itself is completed in this collective step. When the bump electrode 3 is an Au ball bump, the bump land 6 and the bump electrode 3 are bonded with a metal capable of solid-phase bonding the bump land 6 or a metal film capable of solid-phase bonding at least only on the surface. Method of solid-state bonding by thermocompression bonding or thermosonic bonding, or Au
The bump electrode 3 and the bump land 6 are joined by using a solder such as Au-Sn, Au-Ge or the like which can be joined without any problem. In the case of the solder ball method in which the bump electrode 3 is formed by melting paste solder, the solder ball itself is melted again and joined to the bump land 6, and in the case where the bump electrode 3 is a plated metal ball, Pb- A method of joining the bump electrode 3 and the bump land 6 using a very common solder such as an Sn-based solder is used. Both methods are the same in that the bumps 3 formed on the semiconductor bare chip 1 are bonded together to the bump lands of the substrate 5.

In flip chip mounting, flip chip 4
When the semiconductor bare chip 1 is simply attached to the substrate 5, the active circuit forming surface of the semiconductor bare chip 1 faces the substrate 5, and at the same time, a gap corresponding to the thickness of the bump 3 is always formed between the semiconductor bare chip 1 and the substrate 5. In this case, since the active circuit surface of the semiconductor bare chip 1 is corroded from the electrode 2 by the active gas or moisture in the atmosphere, at least the active circuit surface of the semiconductor bare chip 1 must be protected from direct contact with the outside air. The sealing resin 7 is used for this protection.
In general, a method of injecting and filling a gap corresponding to the thickness of the bump electrode 3 is used. FIG. 11 is a cross-sectional view showing a step of injecting and filling the sealing resin 7. The gap between the semiconductor bare chip 1 and the substrate 5 resulting from the height of the bump 3 of about 30 to 100 μm is formed by an injection needle from the side of the flip chip 4. The sealing resin is injected using the needle 8 described above. The sealing resin 7 has a different curing method such as a thermosetting type or an ultraviolet curing type. However, the resin is cured by a method suitable for the resin to complete the resin sealing step. It is sealed.

[0013]

The location where the sealing resin is injected and filled to protect the active circuit surface of the semiconductor bare chip 1 is the same as the height of the bump electrode 3, and the height is 30. Since it is only about 100 μm and the flowability of the resin itself is not so high in order to suppress the outflow, it is difficult to uniformly inject the sealing resin into these narrow gaps. The larger the size is, the more likely voids 9 are partially filled with resin. Resin sealing is performed for the purpose of shutting off the outside air, but on the contrary, the outside air is included in the void 9 and the existence of the void 9 is caused by the semiconductor bare chip 1 and the substrate 5.
There is a problem that it is impossible to find out by visual inspection or other inspections because it is hidden by the.

Although the sealing resin 7 is made with its fluidity adapted for injection / filling, the outflow to the surroundings is completely prevented as long as the sealing resin 7 is injected and filled using the fluidity of the resin. If a plurality of flip chips 4 are mounted on the substrate 5 adjacent to each other as shown in FIG. 11, the sealing resin 7 between the adjacent flip chips 4 flows out and is integrated. This may cause a problem in appearance and a problem of unnecessary stress generation at the same time.

When a plurality of flip chips 4 are to be mounted on a single substrate 5 at a high density as shown in FIG. 11, there is a space around each flip chip 4 to allow a needle 8 to be inserted. In addition, since a space must be ensured in consideration of the minimum outflow of the sealing resin 7, there is a problem that a dead space is generated from the viewpoint of flip chip original high-density and compact mounting.

Further, since the sealing resin 7 is a polymer material and breathes itself, it is impossible to completely shut off the outside air.
When used in a poor environment for a long period of time When corrosion occurs in the interface circuit 2 of the semiconductor bare chip 1 or the active circuit of the semiconductor bare chip 1 via the interface electrode 2 or when the sealing resin that has absorbed moisture is rapidly heated. The absorbed water is vaporized, and the vapor pressure stress causes the sealing resin 7 such as the bump joint, the sealing resin 7 and the semiconductor bare chip 1.
There is a problem in terms of reliability that a crack may be generated in a portion touched by the device.

The bump electrode 3 and the semiconductor bare chip 1
Junction with interface electrode 2 and bump electrode 3
There is a problem that the sealing resin 7 is in direct contact with the bonding portion between the substrate and the bump land 6 of the substrate 5 and the connection reliability of the bump connecting portion is reduced due to the expansion and contraction stress of the resin.

In addition, since the sealing resin 7 comes into direct contact with the active circuit surface and the bump connection portion of the semiconductor bare chip 1, the circuit characteristics become distorted as the circuit configuration becomes higher in frequency due to the dielectric constant of the sealing resin. There is a problem with circuit function.

According to the present invention, it is possible to obtain a flip chip mounting structure which can be mounted in an occupied area substantially equal to the occupied area of the semiconductor bare chip itself, and at the same time, obtains high reliability equivalent to that when the package is hermetically sealed. It is the purpose.

[0020]

According to a first aspect of the present invention, there is provided a flip-chip mounting structure in which a flip-chip having at least a surface covered with a metal capable of solid-phase bonding is plated with a metal material capable of solid-phase bonding. Stacked to form a wall-shaped hermetic ring surrounding the entire active circuit surface of the semiconductor bare chip, and solid-state bonding of the bumps to the bump lands provided on the substrate, at least the surface of which is coated with a metal capable of solid-state bonding, and An airtight ring is solid-phase bonded to a ring-shaped land provided at least on the surface of which is coated with a metal capable of solid-phase bonding, so that the entire active circuit surface of the semiconductor bare chip and the bump bonding portion have an airtight structure in units of one flip chip. It was done.

In the flip chip mounting structure according to the second invention, at least the active circuit surface of the semiconductor bare chip according to the first invention is formed of a Si semiconductor, and a solid metal is formed into the same shape as the hermetic ring in the first invention. Au on the surface
A coated metal ring was manufactured, and this metal ring was directly Au-Si eutectic bonded to an active circuit surface formed of a Si semiconductor of a semiconductor bare chip, and an airtight ring was attached to a flip chip.

In a flip chip mounting structure according to a third aspect of the present invention, a ring pattern is formed on the active circuit surface of the semiconductor bare chip in a ring shape surrounding the entire active circuit forming portion and at least the surface is coated with a metal coating capable of solid-phase bonding. A metal ring is formed by processing a solid metal in the same shape as the hermetic ring of the first invention and applying a metal coating capable of solid-phase bonding on at least the surface thereof, and solid-phase bonding the metal ring to a ring pattern to form a flip chip. An air-tight ring is attached to this.

In the flip chip mounting structure according to the fourth invention, the airtight ring is attached to the flip chip by using a high-temperature solder which melts the metal ring at a temperature higher than the temperature applied in the solid-state joining process in the third invention. It is a thing.

According to a fifth aspect of the present invention, there is provided a flip chip mounting structure in which a protective glass used for protecting an active circuit surface of a semiconductor bare chip is formed thickly so as to collectively surround the plurality of electrode pads and bump electrodes. One glass hermetic ring is formed, and the end face of this hermetic ring is provided with a metal coating capable of solid-phase bonding.

According to a sixth aspect of the present invention, there is provided a flip chip mounting structure according to the first to fifth aspects, wherein an airtight ring attached to the flip chip and a ring type provided at least on a surface of the substrate, which can be solid-phase bonded. The land and the land are hermetically bonded using solder that is melted at a temperature lower than the temperature applied in the solid phase bonding process.

The mounting structure of the flip chip according to the seventh invention is that the powder glass is formed into the same shape as the hermetic ring of the first invention to produce a powder glass ring, and this powder glass ring is connected to the flip chip and the substrate. Sandwiched between
A portion surrounded by a semiconductor bare chip, a glass hermetic ring, and a substrate by simultaneously bonding the bump electrodes of the flip chip and the bump lands of the substrate using a solid-state bonding method at the same time and solidifying the powder glass ring. Is hermetically sealed.

According to an eighth aspect of the present invention, in the flip chip mounting structure according to the first to seventh aspects, the temperature is higher than the temperature applied in the solid-state bonding process between the bump land provided on the substrate and the flip-chip bump electrode. It is joined using solder that melts at a low temperature.

A flip chip mounting structure according to a ninth aspect of the present invention is the flip chip mounting structure according to the first to eighth aspects, wherein a plurality of airtight rings individually surrounding a plurality of electrodes of the semiconductor bare chip,
Or a structure in which a plurality of electrodes are divided into a plurality of blocks and a plurality of hermetic rings are provided so as to enclose the periphery of each block at a time, and the electrodes of the semiconductor bare chip are divided individually or block by block and hermetically sealed. is there.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a cross-sectional view showing Embodiment 1 of the present invention.
Reference numeral 5 is the same as or equivalent to that shown in the conventional example. Reference numeral 10 denotes a bump electrode whose surface is coated with a metal capable of solid-phase bonding. The bump electrode 10 is formed by solid-state bonding of an Au ball bump formed by solid-state bonding by applying the Au wire bonding method, a metal ball whose surface is coated with a metal capable of solid-state bonding, or solid-state bonding. The bump 1 is formed of a material that can be formed by plating using a possible metal and is made of a material commonly used for the interface electrode 2 of the semiconductor bare chip.
Any material can be used as long as it can attach 0.

Reference numeral 12 denotes an airtight ring which surrounds all of the plurality of bump electrodes 10 and the entire active circuit forming surface of the semiconductor bare chip 1, and is a plating stacking ring which is thickened by a plating process. The plating stacking ring 12 is formed by using a metal capable of solid-phase bonding by a plating process, and is formed to a height slightly lower than the height of the bump electrode 10. Therefore, the plating stacking ring 12 is apparently similar to a ring-shaped metal workpiece that can be solid-phase bonded and attached by some method. However, since the plating stacking ring 12 is formed by directly plating the surface of the semiconductor bare chip 1, the plating stacking ring 12 is stacked. There is no gap between the contact between the ring 12 and the semiconductor bare chip 1, and an airtight structure is formed.

Since the plating stacking ring 12 is formed by stacking by a plating process, the plating stacking ring 12 may be collectively formed for a large number of semiconductor bare chips in a wafer state before the semiconductor bare chips 1 are divided into individual chips. It is possible to use the bump electrode 10
Is formed by a plating stacking method, it is also possible to form both the bump electrode 10 and the plating stacking ring 12 at the same time. 13 is formed on the substrate 5,
Bump lands are provided at positions corresponding to the bump electrodes 10, and at least the surface thereof is the bump electrode 1.
Cover with a metal film capable of solid-phase bonding with a metal capable of solid-phase bonding forming the zero surface. 14 is formed on the substrate 5,
A ring-shaped land formed in substantially the same shape at a position corresponding to the plating stacking ring 12, and at least the surface thereof can be solid-phase bonded to a metal capable of solid-phase bonding forming the surface of the plating stacking ring 12. Cover with a possible metal film.

The flip chip 11 is placed on the substrate 5 with the positions of the bump electrode 10 and the bump land 13 and the positions of the plating stacking ring 12 and the ring-shaped land 14, and then the flip chip 11 is placed in an inert gas or vacuum. 5, the portion on which the flip chip 11 is placed and the flip chip 11 are heated until reaching a temperature of 300 to 350 ° C.
At that temperature, the flip chip 11 is subjected to a solid phase bonding step of pressing the flip chip 11 against the substrate 5. In this solid-phase bonding step, the plurality of sets of the bump electrodes 10 and the bump lands 13 are all solid-phase bonded at the same time, and the plating stacking ring 12 and the ring-shaped lands 14 are simultaneously solid-phase bonded.
At this time, since the bump electrode 10 is formed to be slightly higher than the plating stacking ring 12, the bump electrode 10 is first solid-phase bonded in the solid phase bonding step. The plating stacking ring 1 formed slightly lower than the bump electrode 10 after the solid phase bonding of the bump electrode 10 because the bump ring 10 is slightly crushed in the bonding.
2 is also solid-phase bonded.

In the solid phase bonding, since the metals are bonded to each other without any gap by the atomic force, the plating stacking ring 12
And the ring-shaped land 14 has an air-tight structure, and the inside surrounded by the plating stacking ring 12 is kept in an inert gas or vacuum state to maintain the entire active circuit surface of the semiconductor bare chip 1, the bump electrode 10, the interface, and the like. All of the contact points between the electrode 2 and the bump electrode 10, the bump land 13, the junction between the bump electrode 10 and the bump land 13, and other parts where contamination or corrosion is likely to occur due to outside air are hermetically sealed. Although the expression of a metal capable of solid phase bonding is used,
Actually, there are dozens of combinations of metals that can be solid-phase joined.Each combination has strong joint strength at the beginning of joining, but depending on the combination of metals and the environment added after joining, that is, depending on the use environment, the joining part Since a vulnerable intermetallic compound may be generated, it is necessary to select a metal that enables initial bonding and that has reliability in a use environment.

The conditions under which the solid-phase bonding is possible are different depending on the metal to be solid-phase bonded and the method of performing the solid-phase bonding by the thermocompression bonding method and the case of performing the solid-phase bonding by the thermocompression bonding method to which ultrasonic waves are applied. In the case of the thermocompression bonding method, it is necessary to apply a pressing force according to the area to be joined at a temperature of 300 to 350 ° C, and when ultrasonic waves are applied, solid phase joining is possible at a temperature of 150 to 250 ° C But one such as wire bonding
Ultrasonic thermocompression bonding is easy if only one Au ball is bonded at a location. On the other hand, flip chip 11 has a plurality of bump electrodes 10 and plating stacking rings 12 are sequentially solid-phase bonded. , A plurality of bump electrodes 10
It is effective to apply ultrasonic waves at the time of bonding. However, when solid-state bonding of the plating stacking ring 12 is performed, since the bump electrodes 10 are already bonded and fixed to the bump lands 13, No effect.

Therefore, the thermocompression bonding method is used. However, ultrasonic waves are applied only at the time of bonding the bump electrodes 10 to improve the bonding property, and the bonding is switched to the thermocompression bonding method without adding ultrasonic waves at the time of bonding the plating stacking ring 12. It is possible. Alternatively, it is also possible to form the bump electrode 10 and the plating stacking ring 12 at the same height and to solid-phase join them to the substrate 5 completely at the same time. Although there is an effect of increasing the bonding property by adding ultrasonic waves, it may be difficult to set mounting conditions because ultrasonic transmission tends to be biased.

When a plurality of flip chips 11 are mounted side by side on the substrate 5, the flip chips 11 are usually solid-phase bonded individually. However, when all the flip chips 11 are uniform in height, When a collective pressing tool or the like that matches the height of the flip chip is prepared, a plurality of flip chips 11 can be mounted on the substrate 5 at a time.

Embodiment 2 FIG. 2 is a sectional view showing Embodiment 2 of the present invention.
1, 2, and 5 are the same as or correspond to those shown in the conventional example, and 10, 11, 13, and 14 are the first embodiment.
Are the same as or equivalent to those shown in FIG. Reference numeral 15 denotes Si formed on at least the surface of the semiconductor bare chip 1.
If the semiconductor bare chip 1 is a semiconductor layer and the entire semiconductor bare chip 1 is formed of a Si semiconductor, a new Si semiconductor layer 15
Although it is not necessary to newly form the semiconductor bare chip 1
Is a compound semiconductor, the Si semiconductor layer 15 is formed on the surface. Reference numeral 16 denotes a metal processing hermetic ring which is formed in the same size and the same shape as the plating stacking ring 12 shown in the first embodiment by processing the metal into a ring shape, and has a surface plated with Au, and the entire metal is made of Au. In that case, there is no need to apply Au plating to the surface.

The metal processing hermetic ring 16 and the semiconductor bare chip 1 are heated to about 380 to 420 ° C., and the metal processing hermetic ring 16 is pressed against the semiconductor bare chip 1 and slightly vibrated to apply the metal processing hermetic ring 16 to the semiconductor bare chip 1. The Au—Si eutectic alloy layer 17 is formed on the contact portion with the semiconductor bare chip 1.
Is formed, and the metal working airtight ring 16 and the semiconductor bare chip 1 are joined. This is a method called Au-Si eutectic bonding method, in which a eutectic alloy layer is formed at a contact point between Au and Si. Since the Au—Si eutectic alloy layer 17 formed by the Au—Si eutectic bonding method is an alloy, it has airtightness, and the flip chip 11 in which the metal bare airtight ring 16 having airtightness is attached to the semiconductor bare chip 1 is used. Be composed. The step of attaching the flip chip 11 to the substrate 5 is exactly the same as that of the first embodiment. In the case of the thermocompression bonding method, the flip chip 11 is heated to a temperature of 300 to 350 ° C., so that the 380 to 380 required for Au—Si eutectic bonding is required. Although it is exposed to a temperature very close to the temperature of 420 ° C., the once formed Au—Si eutectic alloy layer 17 is a characteristic of the eutectic alloy rather than required in the Au—Si eutectic bonding process. Since melting is not performed unless the temperature is much higher, even in the case of the thermocompression bonding method, the hermetically bonded structure between the metal working hermetic ring 16 and the semiconductor bare chip 1 is maintained without any change.

Third Embodiment FIG. 3 is a sectional view showing a third embodiment of the present invention.
Reference numerals 2 and 5 are the same or corresponding to those shown in the conventional example, and reference numerals 10, 11, 13 and 14 are the same or corresponding to those shown in the first embodiment. Reference numeral 18 has the same shape as the metal-worked airtight ring 16 shown in the second embodiment, but is provided with any metal coating capable of solid-phase bonding, not limited to Au plating. Reference numeral 19 denotes a ring pattern formed on the active circuit surface of the semiconductor bare chip 1 so as to enclose the plurality of interface electrodes 2 at a time. At least the surface is coated with a metal capable of solid-phase bonding, for example, Au. The metal working hermetic ring 18 is solid-phase bonded to this ring pattern 19 using a thermocompression bonding method or an ultrasonic thermocompression bonding method, and the flip chip 11 having the hermetically sealed metal working hermetic ring 18 attached to the semiconductor bare chip 1 is obtained. Be composed. This flip chip 11 is mounted on the substrate 5
Is the same as that in the first embodiment.

Fourth Embodiment FIG. 4 is a sectional view showing a fourth embodiment of the present invention.
Reference numerals 2 and 5 are the same or corresponding to those shown in the conventional example, and reference numerals 10, 11, 13 and 14 are the same or corresponding to those shown in the first embodiment.
Is the same as that shown in the third embodiment. 20
Is a solder layer formed of solder that melts at a temperature equal to or higher than the temperature required for solid-phase bonding, and is made of Au-Ge solder (melting point 382).
C.) and Zn-Al solder (melting point: 424 ° C.), etc.
A solder having a melting point in a range that does not adversely affect the above is used.
The ring pattern 19 and the metal processing airtight ring 18 are soldered to form the flip chip 11 in which the airtight metal processing airtight ring 18 is attached to the semiconductor bare chip 1. The step of attaching the flip chip 11 to the substrate 5 is exactly the same as in the first embodiment.

Fifth Embodiment FIG. 5 is a sectional view showing a fifth embodiment of the present invention.
Reference numerals 2 and 5 are the same or corresponding to those shown in the conventional example, and reference numerals 10, 11, 13 and 14 are the same or corresponding to those shown in the first embodiment. Reference numeral 21 denotes a protective glass layer covering the entire active circuit surface of the semiconductor bare chip 1 except for the interface electrode 2, and is generally formed for the purpose of protecting a circuit pattern constituting an active circuit of the semiconductor bare chip 1 from contamination and mechanical shock. Is what it is. Although the description of the protective glass layer has been omitted heretofore, even in the case of the conventional example, a protective glass layer is often formed on the surface of the semiconductor bare chip 1, and the first to third embodiments of the present invention are described. Even up to 4, a protective glass layer may be formed.

The pattern constituting the active circuit of the semiconductor bare chip 1 is formed of Au or Al, but is obtained by etching a metal film formed as an entire surface film into a required shape. For simplicity, the protective glass usually covers other than the interface electrode 2. This protective glass layer is applied in the semiconductor bare chip wafer manufacturing process, and the forming method differs depending on the type of semiconductor.
The surface of the Si semiconductor is oxidized to change it to SiO2, which is a type of glass, and the SiO2 film is partially removed by etching the SiO2 film, exposing the surface of the Si semiconductor and subjecting it to the next processing step. A method of thinning is adopted. In this case, the height of the bump electrode 10 was set to be slightly lower than that of the bump electrode 10, and the glass hermetic ring 22 was formed while leaving the protective glass so as to surround the entire active surface of the semiconductor bare chip 1.

As a sectional structure, it looks as if the same glass material is further thickly stacked on the protective glass layer 21 to form a glass hermetic ring 22, but the forming method is to remove unnecessary portions from the attached one. The opposite is the case. Reference numeral 23 denotes a metal plating formed on the end face of the glass hermetic ring 22 and capable of solid-phase bonding. In the case of a Si semiconductor, for example, the entire surface of a semiconductor wafer is converted to SiO2 and then solid-phase bonded to the entire surface of SiO2. A possible metal film is formed by vapor deposition or sputtering, and the metal film capable of solid-phase bonding and the SiO2 film are combined and etched into a desired shape to form a hermetic glass hermetic ring 22 on the semiconductor bare chip 1. The step of attaching the flip chip 11 on which the glass hermetic ring 22 is formed to the substrate 5 is exactly the same as that of the first embodiment.

Sixth Embodiment FIG. 6 is a sectional view showing a sixth embodiment of the present invention.
Reference numerals 2 and 5 are the same or corresponding to those shown in the conventional example, and reference numerals 10, 11, 12, 13, and 14 are the same or corresponding to those shown in the first embodiment. 24
Is a solder layer formed of a solder material that melts or becomes eutectic at a temperature equal to or lower than the temperature required for solid-phase bonding, and is a plating stacked airtight ring 12 provided on the flip chip 11.
And the ring-shaped land 14 of the substrate 5 are hermetically soldered. The configuration is exactly the same as that of the first embodiment except for the solder layer 24. However, the manufacturing conditions for mounting the flip chip 11 on the substrate 5 are quite different, and in the first embodiment, the bump electrodes 10 of the flip chip 11 Although the bonding of the bump land 13 of the substrate 5 and the bonding of the plated airtight ring 12 of the flip chip 11 and the ring land 14 of the substrate are simultaneously solid-phase bonded, here, the bump electrode 10 of the flip chip 11 and the substrate are bonded. 5 bump lands 1
3 is heated to a temperature of 300 to 350 ° C. as in the first embodiment, and then pressurized to perform solid-phase bonding, and between the plating stacked airtight ring 12 of the lip chip 11 and the ring-shaped land 14 of the substrate. Au having a melting or eutectic point at a temperature lower than 300 to 350 ° C., for example, an eutectic point of 280 ° C.
By sandwiching the 80 Sn20 solder, the bump electrodes 10 of the flip chip 11 and the bump lands 13 of the substrate 5 are formed.
The solder layer 24 is liquefied prior to the start of the solid phase bonding of the flip chip 11 and the bump electrode 10 of the flip chip 11 and the substrate 5.
When the bonding of the bump lands 13 is completed and the pressing force is eliminated and the temperature is lowered, the solder layer 24 is solidified and the plating stacked airtight ring 12 and the ring-shaped land 14 of the substrate are formed.
Are hermetically joined by the solder layer 24.

Although the case where the solder layer 24 is provided has been described by taking the first embodiment as an example, each of the second, fourth and fifth embodiments also has a different form of the hermetic ring. It is completely possible to hermetically join the hermetic ring and the ring-shaped land 14 of the substrate via the solder layer 24.

Seventh Embodiment FIG. 7 is a sectional view showing a seventh embodiment of the present invention.
Reference numerals 2 and 5 are the same or corresponding to those shown in the conventional example, and reference numerals 10, 11, and 13 are the same or corresponding to those shown in the first embodiment. Reference numeral 25 denotes a sintered glass hermetic ring, which is formed by shaping a glass powder sintered at a temperature of 400 ° C. or less into a ring shape and then sintering the solidified glass. The method of forming glass powder and then sintering it is well known as hermetic glass when providing an insulated through terminal on a metal plate or the like and when hermetically bonding a box-shaped case and a lid. The temperature ranges from about 280 ° C. to 600 ° C. depending on the material of the glass.
Glass powder that sinters at a temperature not exceeding 00 to 350 ° C. is used.

After the powdered glass is formed into a shape and size surrounding the plurality of interface electrodes 2 formed on the semiconductor bare chip 1 and the thickness is substantially equal to the height of the bump electrode 10, the gap between the semiconductor bare chip 1 and the substrate 5 is formed. The bump electrode 10 and the bump land 13 of the substrate 5 are solid-phase bonded as described in the first embodiment. At this time, the temperature of the flip chip 11 and the substrate 5 is 30.
Since the temperature has risen to 0 to 350 ° C., the molded powder glass is sintered, and the sintered glass hermetic ring 25 is formed.
The material of the semiconductor and the vitreous material generally have a high bonding property, and when the protective glass layer 21 is formed on the active circuit surface of the semiconductor bare chip 1 as described in the fifth embodiment, the vitreous material is bonded. Therefore, the airtightness of the joint is high. Further, in joining the substrate 5 and the sintered glass hermetic ring 25, when the substrate 5 is made of ceramic, the joint between ceramic and glass is high, so that the substrate 5 can be easily air-tightly joined. Even in the case of (1), if the glass fiber layer which is usually not used and which is not used is provided on the outermost surface, hermetic bonding between vitreous materials is possible.

Eighth Embodiment FIG. 8 is a sectional view showing an eighth embodiment of the present invention.
Reference numerals 2 and 5 are the same or corresponding to those shown in the conventional example, and reference numerals 10 to 14 are the same or corresponding to those shown in the first embodiment. Reference numeral 26 denotes a solder fillet formed of a solder material that melts or becomes eutectic at a temperature lower than the temperature required for solid-phase bonding, and solders the bump electrode 10 of the flip chip 11 and the bump land 13 of the substrate 5. Things. The composition is this solder fillet 2
6 except that the manufacturing conditions for mounting the flip chip 11 on the substrate 5 are considerably different. In the first embodiment, the bump electrode 10 of the flip chip 11 and the bump land of the substrate 5 are different. 13 and the bonding of the plated airtight ring 12 of the flip chip 11 and the ring-shaped land 14 of the substrate are simultaneously solid-phase bonded.
Here, the bonding between the plating stacked airtight ring 12 of the flip chip 11 and the ring-shaped land 14 of the substrate 5 is heated to a temperature of 300 to 350 ° C. and then pressurized to perform solid-phase bonding as in the first embodiment. 300 to 350 between the bump electrode 10 of FIG.
In a step of attaching the flip chip 11 to the substrate 5 by sandwiching Au80Sn20 solder having a melting or eutectic point at a temperature lower than 0 ° C., for example, having a eutectic point of 280 ° C., the plating stacked airtight ring 12 of the flip chip 11 and the substrate The solder layer 24 is liquefied before the joining of the ring-shaped land 14 is started.
1 when the bonding between the plating stacked airtight ring 12 and the ring-shaped land 14 of the substrate is completed and the pressing force is eliminated and the temperature is lowered, the solder layer 24 is solidified and the flip chip 1 is removed.
One bump electrode 10 and the bump land 13 of the substrate are soldered to form a solder fillet 26.

In the first embodiment, solder fillet 26
Has been described, but also in the second to seventh embodiments, the form of the hermetic ring is different, but the bump electrode 10 of the flip chip 11 and the bump land 13 of the substrate 5 are soldered. Forming the solder fillet 26 is just as possible. In the sixth embodiment, both the joining of the airtight ring of the flip chip 11 to the ring-shaped land 14 of the substrate 5 and the joining of the bump electrode 10 of the flip chip 11 to the bump land 13 of the substrate 5 are performed by soldering. Will be done.

Ninth Embodiment FIG. 9 is a sectional view showing an eighth embodiment of the present invention.
Reference numerals 2 and 5 are the same or corresponding to those shown in the conventional example, and reference numerals 10 to 14 are the same or corresponding to those shown in the first embodiment. In FIG. 9, the plating stacked airtight ring 12 is provided at three locations as a cross section, and two sets of bump electrode joints are arranged inside thereof.
This is to hermetically seal the inner part of the part separated by the two plating stacked airtight rings 12 as one block,
This shows that the whole area of the active circuit surface of the semiconductor bare chip is divided into a plurality of blocks, an airtight ring is provided for each block, and the blocks are hermetically sealed. The division of the blocks is arbitrary and not the division of the blocks, but the interface electrodes 2 of the semiconductor bare chip 1.
A plating stacked airtight ring 12 may be provided for each plating. Further, although the plating stacked airtight ring 12 in the first embodiment is used as an example of the description, the metal working airtight ring 16 in the second embodiment, the metal working airtight ring 18 in the third embodiment, and the glass airtight ring in the fifth embodiment are described. Even in the ring 22 and the sintered glass hermetic ring 25 of the seventh embodiment, an airtight ring is provided for each block or each interface electrode 2 in the same manner, and the block unit or the interface electrode 2 is provided.
It can be hermetically sealed every time.

[0051]

According to the first aspect of the present invention, each flip chip is hermetically sealed without performing resin sealing, and the area required for mounting on a substrate is equal to the body of the flip chip. Since the size is equal to the size of the semiconductor bare chip itself, the interval between adjacent flip chips can be minimized.

Further, because of the hermetically sealed structure, it is possible to prevent intrusion of moisture or active gas, and the entire active circuit surface of the semiconductor bare chip, bump electrodes, contacts between interface electrodes and bump electrodes, bump lands, and bump electrodes A portion which is vulnerable to contamination or corrosion, such as a joint portion between the bump land and the like, is protected.

Further, since there is no solid material that touches the entire active circuit surface of the semiconductor bare chip, the bump electrode, the contact between the interface electrode and the bump electrode, the bump land, and the junction between the bump electrode and the bump land, stress is applied to the bump joint. Without the addition, the reliability of the bump connection part is remarkably improved.

In addition, since there is no solid material that touches the entire active circuit surface of the semiconductor bare chip, the bump electrodes, the contact points between the interface electrodes and the bump electrodes, the bump lands, and the junctions between the bump electrodes and the bump lands, even if the circuit is a high-frequency circuit, All problems arising from the use of resin, such as a structure that does not affect properties, can be eliminated.

Further, in the case of resin sealing, a post-process of filling the resin and curing the resin after mounting the flip chip on the substrate was required. In the present invention, the hermetic sealing is performed only by the process of mounting the flip chip on the substrate. Therefore, the construction period can be shortened and the price can be reduced.

Further, since the hermetic ring is made of metal, the active circuit portion of the semiconductor bare chip is electromagnetically shielded. Particularly, in the case of a high-frequency circuit, each flip chip is electromagnetically shielded, so that a stable circuit function can be realized. There is.

According to the second aspect of the invention, in addition to the effect of the first aspect, the formation of the hermetic ring can be performed separately from the semiconductor wafer manufacturing process. Since an inexpensive metal material can be selected as a constituent material, the cost can be further reduced.

In addition to the semiconductor wafer manufacturing process, the process of attaching the metal working airtight ring to the semiconductor bare chip is possible even after the semiconductor bare chip is divided individually, and the range of application is widened.

When the Au—Si eutectic alloy layer is formed, a part of Au itself constituting the hermetic ring is melted and A
Since it becomes a u-Si eutectic alloy layer, it is necessary to control the melting amount so as not to melt too much. However, in the second invention, since this melting control is not necessary, the process management becomes more difficult. It has the effect of being simple

According to the third invention, in addition to the effects of the first invention and the effects of the second invention, a method of attaching a metal working airtight ring to a semiconductor bare chip, and a method of mounting a flip chip having an airtight ring on a substrate are provided. Since both of the mounting methods are the solid-phase bonding methods, the process of mounting the airtight ring on the semiconductor bare chip and the process of mounting the flip chip on the substrate can be performed at the same time, and the cost can be further reduced. .

According to the fourth invention, in addition to the effects of the first invention and the effects of the second invention, since the method for attaching the metal working airtight ring is soldering, the divided semiconductor bare chips are individually provided. When installing the metal working airtight ring, there is no need for a large pressure required for solid-state welding. Therefore, even in the case of a large semiconductor bare chip in which warpage is particularly likely to occur, the metal working airtight ring can be attached without applying mechanical pressure, and a slight warp is filled by the flow of the solder.

Further, when attaching the metal working hermetic ring in the wafer state, the solder is collectively mounted, the metal working hermetic ring is placed, and then the reflow process is performed. There is an effect that can be.

According to the fifth aspect, in addition to the effects of the first aspect other than the electromagnetic shielding effect, a new process is added to the process for forming a conventional semiconductor wafer without forming an airtight ring. Since the hermetic ring can be formed at once in the semiconductor wafer process without adding, the manufacturing cost does not largely change by attaching the hermetic ring.

Further, since the material forming the airtight ring is a glass material, there is an effect that the cost can be reduced most.

According to the sixth aspect of the present invention, since the bonding between the airtight ring provided on the flip chip and the substrate is performed by soldering, only the heat is required for bonding the airtight ring, and the pressing force is required. In addition, the pressure applied to the flip chip can be reduced to only the pressure required for solid phase bonding between the bump electrode and the substrate, so that the pressing condition of the flip chip mounting conditions can be reduced, and particularly large In a flip chip of a size, breakage of the flip chip itself, which is easily caused by warpage due to heating, can be suppressed.

In addition, even when the flip chip is warped, the liquefied solder fills uneven gaps caused by the warp, so that there is an effect of preventing air leak which is likely to occur at a junction between the airtight ring of the flip chip and the substrate.

According to the seventh aspect, the effects other than the electromagnetic shielding effect among the effects of the first aspect and the constituent material of the hermetic ring are glass, so that the hermetic ring is formed at a low cost following the fifth aspect. it can.

Further, since the hermetic ring is formed by molding powdered glass, the hermetic ring is formed independently of the semiconductor wafer manufacturing process. In the flip chip mounting process, the formation of the hermetic ring and the flip of each flip chip are performed. It is possible to perform hermetic sealing of the chip,
There is an effect that the application range to a wide variety of flip chips is wide.

According to the eighth aspect of the present invention, the bonding between the bump electrode of the flip chip and the bump electrode of the substrate is performed by soldering, so that only the heat is required for the bonding of the bump electrodes and the pressing force is not required. However, the pressure applied to the flip chip can be reduced to only the pressure required for solid-state bonding between the airtight ring of the flip chip and the substrate, so the pressing conditions of the flip chip mounting conditions can be reduced. ,
In particular, in a flip chip having a large number of bump electrodes, the pressure applied to the flip chip can be suppressed, and a pressure exceeding the proof stress of the semiconductor bare chip itself can be avoided.

When both the bonding of the flip-chip hermetic ring to the substrate and the bonding of the flip-chip bump electrode to the substrate are performed by soldering, no pressure is required in the step of attaching the flip chip to the substrate. Since there is no need to apply mechanical force to the flip chip,
In particular, even in the case of a large or thin semiconductor bare chip that is likely to be warped, the flip chip can be attached to the substrate without any trouble.

When both the bonding of the flip-chip airtight ring to the substrate and the bonding of the flip-chip bump electrodes to the substrate are performed by soldering, all the bonding points between the flip-chip and the substrate are soldered. Because of this, it is easy to remove the flip chip from the board, and it is possible to replace the flip chip as needed, especially in the case of a multi-chip mounting board equipped with multiple flip chips, replace only the failed flip chip This has the effect of minimizing losses.

According to the ninth aspect, the plurality of interface electrodes formed on the semiconductor bare chip can be hermetically sealed by forming a hermetic ring for each arbitrary block or for each interface electrode. When one hermetic ring is used for hermetic sealing, particularly when the size of the semiconductor bare chip is large and the sealing length is long, hermetic bonding between the hermetic ring and the substrate tends to be partially incomplete. The sealing length of each hermetic ring can be reduced by dividing the sealing portion into blocks or hermetically sealing each interface electrode, so that the airtightness of each hermetic ring can be secured. is there.

Also, by setting the size of the hermetic ring to several types, the hermetic sealing structure can be obtained irrespective of the size of the semiconductor bare chip by dividing into blocks using these types of hermetic rings. There is an effect that costs for designing work, jigs and the like necessary for forming the ring do not have to be generated for each type of semiconductor bare chip.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a flip chip mounting structure according to the present invention.

FIG. 2 is a sectional view showing a flip-chip mounting structure according to a second embodiment of the present invention;

FIG. 3 is a sectional view showing a flip-chip mounting structure according to a third embodiment of the present invention;

FIG. 4 is a sectional view showing a flip chip mounting structure according to a fourth embodiment of the present invention;

FIG. 5 is a sectional view showing a fifth embodiment of a flip chip mounting structure according to the present invention;

FIG. 6 is a sectional view showing a flip chip mounting structure according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a flip chip mounting structure according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view showing Embodiment 8 of a flip chip mounting structure according to the present invention.

FIG. 9 is a sectional view showing a ninth embodiment of a flip chip mounting structure according to the present invention;

FIG. 10 is a cross-sectional view showing a conventional flip chip mounting structure.

FIG. 11 is a cross-sectional view showing a conventional flip chip mounting structure.

[Explanation of symbols]

1 semiconductor bare chip, 2 interface electrodes, 3
Bump electrode, 4 flip chip, 5 substrate, 6
Bump land, 7 sealing resin, 8 needle, 9 void, 10 bump electrode, 11 flip chip, 12
Plating stacked airtight ring, 13 Bump land, 14
Ring-shaped land, 15 Si semiconductor layer, 16 metal working airtight ring, 17 Au-Si eutectic alloy layer, 18 metal working airtight ring, 19 ring pattern, 20 solder layer,
21 protective glass layer, 22 glass hermetic ring, 23
Metal plating, 24 solder layers, 25 sintered glass hermetic rings, 26 solder fillets.

Claims (9)

[Claims] 1. A flip chip in which a plurality of interface electrodes provided on an active circuit surface of a semiconductor bare chip are each provided with a bump electrode whose surface is coated with a metal capable of solid-phase bonding. A wall-shaped hermetic ring formed of a metal that can be solid-phase bonded using a plating stacking method and enclosing the periphery of the plurality of interface electrodes and the bump electrodes collectively; and a substrate on which the flip chip is mounted. A bump land having at least a surface coated with a solid phase bondable metal at a position corresponding to each of the bump electrodes; and a ring shape surrounding the bump land, corresponding to the hermetic ring, and at least a surface having a solid phase. A ring-shaped land coated with a bondable metal, and a bump electrode of the flip chip. The bump lands of the substrate are all bonded together using a solid-phase bonding method, and the hermetic ring and the ring-shaped lands of the substrate are hermetically bonded using a solid-state bonding method. Flip chip mounting structure. 2. A semiconductor ring wherein at least an active circuit surface of the semiconductor bare chip is formed of a Si semiconductor and is formed by processing a solid metal and at least a surface of which is coated with Au, a metal ring is directly formed on the Si semiconductor surface. 2. The flip chip mounting structure according to claim 1, wherein a wall-shaped airtight ring is formed on the flip chip by airtight bonding using a crystal bonding method. 3. An active circuit surface of the semiconductor bare chip, wherein at least a surface surrounding at least one of the plurality of interface electrodes collectively is covered with a solid phase bondable metal, and a ring pattern is formed. A metal ring formed by processing a solid metal and coated at least on the surface with a metal that can be solid-phase bonded is hermetically bonded using a solid-phase bonding method to form a wall-shaped air-tight ring on the flip chip. The flip chip mounting structure according to claim 1, wherein: 4. The method according to claim 1, wherein the metal ring is soldered using a solder that is melted at a temperature equal to or higher than a temperature applied in the solid-state bonding method, and the metal ring is air-tightly bonded. The flip-chip mounting structure according to claim 3, wherein: 5. A wall-shaped glass hermetic ring enclosing the plurality of electrode pads and bump electrodes collectively by using a protective glass used for protecting an active circuit surface of a semiconductor bare chip. 2. A metal coating capable of solid-phase bonding is applied to an end face of the ring.
Flip chip mounting structure described. 6. The airtight ring according to claim 1, wherein said airtight ring is soldered to a ring-shaped land of said substrate by using a solder which is melted at a temperature lower than a temperature applied in the solid-state bonding method. The flip chip mounting structure according to any one of 1, 2, 4, and 5. 7. A flip chip in which a plurality of interface electrodes provided on an active circuit surface of a semiconductor bare chip are each provided with a bump electrode having a metal coating capable of solid-phase bonding on at least a surface thereof; At least at a corresponding position, a substrate having a bump land coated with a metal capable of solid-phase bonding, and a powder glass ring formed by molding powder glass, wherein the glass ring is formed of the flip chip and the substrate. The bump electrodes of the flip chip and the bump lands of the substrate are all bonded together by using a solid-state bonding method, and a glass ring is solidified into a vitreous solid to surround the plurality of electrode pads and the bump electrodes. A wall-shaped hermetic ring is formed to enclose the semiconductor chip and the glass hermetic ring and the substrate together. A flip-chip mounting structure, wherein an enclosed portion is hermetically sealed. 8. The method according to claim 1, wherein the bump electrode and the bump land of the substrate are joined by soldering using a solder that is melted at a temperature equal to or lower than a temperature applied in a solid-state joining method. Flip chip mounting structure according to any of the above. 9. An airtight ring having the same number of electrode pads as individually enclosing a plurality of electrode pads of the semiconductor bare chip, or a plurality of interface electrodes divided into a plurality of blocks and enclosing the periphery of each block collectively. 9. An airtight ring is provided.
Flip chip mounting structure according to any of the above.