WO2019183983A1

WO2019183983A1 - Semiconductor package structure and packaging method therefor

Info

Publication number: WO2019183983A1
Application number: PCT/CN2018/081489
Authority: WO
Inventors: 韩梅; 李晓勇; 滕辉
Original assignee: 华为技术有限公司
Priority date: 2018-03-31
Filing date: 2018-03-31
Publication date: 2019-10-03
Also published as: CN111919297A

Abstract

A semiconductor package structure and a packaging method therefor, the semiconductor package structure comprises: a chip (20), including a bare chip, and a signal source is disposed on a first side of the bare chip; a first metal layer (26) is disposed on a second side opposite to the first side on the bare chip, the structures of the two sides of the bare chip are connected in a one-to-one correspondence by means of a via hole; a substrate (10), being disposed in a stacked manner with the chip (20), and the substrate (10) is provided with a signal base pin, the signal base pin being connected to the first metal layer (26) by means of a welding element. According to the described technical solution, the chip (20) is electrically connected to the substrate (10) by welding, which improves the connection strength between the substrate (10) and the chip (20). Furthermore, by using the welding manner, the precision is high, and the connection of components after miniaturization of the device is facilitated.

Description

Semiconductor package structure and packaging method thereof

Technical field

The present application relates to the field of communications technologies, and in particular, to a semiconductor package structure and a packaging method thereof.

Background technique

Conventional power amplifier chips, RF microwave millimeter wave chips, etc., in order to meet the heat dissipation and electrical performance requirements, usually adopt the package structure as shown in FIG. 1 or FIG. 2, wherein the front side of the chip is an active surface 107, including functional transistors and related The circuit; the back side is a full-face metal layer 104, as a reference ground for the circuit, or a heat dissipating surface; in the necessary scene, a metal via 105 may be used to connect the metal ground and the back metal layer 104 on the front side of the chip.

The material of the metal layer 104 includes Au, Ag or Cu, and the like. In order to achieve the purpose of conducting, dissipating, and protecting the chip, the following methods are generally used in the packaging: first, the chip is mounted on the package substrate 101 by using a material such as silver paste or solder paste, so that the back metal layer 104 and the package substrate 101 are placed on the package substrate 101. The pad 102 is in conductive communication, and then the metal wire 109 is connected to connect the chip front signal source 106 and the circuit trace on the package substrate 101, and finally the capping layer 108b or the molding compound 108a is applied to the substrate.

Among them, Epoxy chip technology is one of the existing semiconductor packaging technologies. The initial substrate is an array composed of a single substrate imposition, that is, a Strip. Place the Strip substrate on the carrier, place the liquid silver paste 103 on each of the pads of the substrate array through the dispensing head, and place the chips on the silver paste by using a Die Bond machine. The appropriate pressure is applied to bond the silver paste to the substrate pad 102 and the chip back 104. The chip was placed in an oven and cured according to the curing curve of the silver paste. After the silver paste of the chip is solidified, the gold wire 109 is completed by a wire bonding machine. The strip substrate is placed in the cavity of the molding machine, and is injection molded at a high temperature and high pressure. The entire substrate is covered with a molding compound 108a, and the plasticized substrate is taken out to complete post-cure curing of the molding compound. Finally, the packaged chip is cut into individual pieces by a microtome, that is, the chip package is completed.

However, when this method is used, the bonding force between the chip and the substrate or the frame depends on the Epoxy material. Due to the covalent bond bonding, the bonding force is weak, and it is easy to crack when subjected to stress, forming delamination, resulting in degradation or failure of the chip performance; The glue has strong fluidity before curing, and the dimensional control precision is poor, which is difficult to meet the welding requirements of small-sized solder joints.

Summary of the invention

The present application provides a semiconductor package structure and a package method thereof for improving the package effect of the semiconductor package structure and ensuring chip performance.

In a first aspect, a semiconductor package structure is provided. The semiconductor package structure includes: a substrate and a chip; wherein the chip includes a die, and the die has two opposite faces, a first surface and a second surface, respectively. And when assembled with the substrate, the second side faces the substrate. a signal source is disposed on the first surface, a first metal layer is disposed on the second surface, and a first via hole is disposed in the die, wherein the signal source passes through the first via and the first The metal layer is electrically connected; when the substrate is disposed, the substrate is stacked with the chip, and a signal pin is disposed on the substrate. When the substrate is connected to the chip, the signal pin is electrically connected to the first metal layer through the first soldering member, thereby achieving electrical connection between the substrate and the chip.

In the above technical solution, the device on the first side of the die is connected to the metal layer on the second side by using a via hole, and the metal layer is electrically connected to the substrate by soldering, thereby facilitating the connection between the chip and the substrate. The connection strength between the substrate and the chip is improved. In addition, by means of soldering, the precision is high, and the connection of components after miniaturization of the device is facilitated.

In a specific embodiment, the chip further includes a first end disposed on the first side of the die, and a second metal layer disposed on the second side of the die, and when disposed, the first metal The layer and the second metal layer are electrically insulated. In addition, a second via hole electrically connecting the first end and the second metal layer is further disposed in the die; a contact layer is disposed on the corresponding substrate, and the contact layer is electrically connected to the second metal layer. The first end may be a power supply end, the corresponding contact layer is a power supply layer, or the first end is a ground end, and the corresponding contact layer is a ground layer.

When the second metal layer is electrically connected to the contact layer, the electrical connection can be achieved by using a silver paste or a second soldering member between the second metal layer and the contact layer. When the second soldering member is used, the connection strength between the chip and the substrate can be effectively improved.

In a specific embodiment, further comprising a filling layer, a filling layer is disposed between the chip and the substrate, and when a filling layer is disposed, a filling layer is used to wrap the first welding When the second soldering member is further disposed between the chip and the substrate, the filling layer also wraps the second soldering member. By filling the adhesive layer as a buffer layer, the force on the soldering member during the drop is reduced, the reliability of the connection between the chip and the substrate is improved, and the reliability of the semiconductor package structure is improved.

In a particular embodiment, the other components are wrapped by a filler layer, specifically: the filler layer is also used to wrap the signal pins. When a contact layer is provided on the substrate, the filler layer also wraps the contact layer, thereby protecting the signal pins and the contact layer by the filler layer. In addition, the filler layer also wraps the first metal layer on the die. When the second metal layer is disposed on the die, the filler layer also wraps the second metal layer, thereby protecting the first metal layer and the second metal. Floor.

When the substrate and the chip are specifically connected, the first soldering member is a soldering member made of a conductive metal or a conductive alloy. Specifically, the first soldering member may be a soldering member made of gold, silver, copper, tin, lead, indium, nickel, tungsten or iron.

The first weldment may have a different configuration. As in a specific embodiment, the first weldment comprises two or more layers of metal balls. By providing at least two layers of metal balls, there is a certain gap between the substrate and the chip, thereby facilitating the setting of the filling layer. When the two metal ball layers are specifically disposed, the size of the metal balls gradually decreases from the direction in which the substrate is directed to the chip.

In another specific embodiment, the first weldment is a weld of a columnar structure. That is, the columnar structure of the soldering member is used to solder the substrate and the chip, so that there is a certain gap between the substrate and the chip, thereby facilitating the setting of the filling layer.

When the second soldering member is disposed between the substrate and the chip, the second soldering member has the same structure as the first soldering member.

When the chip is specifically set, the chip is a power amplifier chip.

When the security of the semiconductor package structure is improved, it can be implemented in different manners. Two different ways are specifically listed below: one way is to further include an encapsulation layer, the encapsulation layer wraps the chip to package the chip On the substrate. And when disposed, the material of the encapsulation layer is the same as the material of the filling layer. The chip is protected by the encapsulation layer. Moreover, when the package layer and the filler layer are made of the same material, the structure for protecting the chip and the connection portion between the chip and the substrate can be directly formed on the substrate. Another way is to provide a capping layer that is fixedly coupled to the substrate and that covers the chip to encapsulate the chip on the substrate. The chip is protected by covering the substrate with a capping layer.

In a second aspect, the present application further provides a method for packaging a semiconductor package structure, the package method comprising the steps of: preparing a signal source on a first side of the die; opening a first via in the die, and a first via is electrically connected to the signal source; a first metal layer is prepared on a second side of the die opposite to the first surface, and the first metal layer is electrically connected to the first via; Forming a signal pin thereon; electrically connecting the signal pin to the first metal layer by a first soldering member.

The method further includes: preparing a first end on a first side of the die; opening a second via in the die, and the second via is electrically connected to the first end; on the die and the first Forming a second metal layer on the opposite second side, and the second metal layer is electrically connected to the second via hole; forming a contact layer on the substrate; and the first layer is formed by silver glue or a second soldering member The terminal is electrically connected to the contact layer.

In the specific preparation, the signal pin is electrically connected to the first metal layer by the first soldering member in the above step; specifically: sputtering, spraying, electroplating, printing on the signal pin on the substrate The first weldment is prepared by spotting, planting or hot pressing. Thereby, the first weldment can be formed on the substrate by different preparation methods. When the second weldment is employed, the second weldment can also be prepared in the manner described above.

In addition, the packaging method further includes: filling a filling layer between the substrate and the chip, and wrapping the first and second welding members during filling. By filling the adhesive layer as a buffer layer, the force on the soldering member during the drop is reduced, the reliability of the connection between the chip and the substrate is improved, and the reliability of the semiconductor package structure is improved.

In order to protect the chip, the chip may be protected by preparing different structures, one of which is: providing an encapsulation layer on the substrate, the encapsulation layer wrapping the chip, and packaging the chip on the substrate; The material of the encapsulation layer is the same as the material of the filling layer. Thereby improving the security of the chip.

Another way is to provide a capping layer on the substrate, and the capping layer covers the chip and encapsulate the chip on the substrate. Thereby improving the security of the chip.

DRAWINGS

1 is a schematic structural view of a semiconductor package structure in the prior art;

2 is another schematic structural view of a semiconductor package structure in the prior art;

3 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present application;

4 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present application; FIG.

FIG. 6 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present application.

detailed description

In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings.

The semiconductor package structure provided in the embodiment of the present application provides a semiconductor package structure for solving the problem of low safety performance of the semiconductor package structure in the prior art. In order to facilitate the understanding of the chip semiconductor provided by the embodiment of the present application, the following is attached. The drawings and the specific embodiments are described in detail.

Referring first to FIG. 3, a semiconductor package structure provided by an embodiment of the present application includes a substrate 10 and a chip 20, wherein the substrate 10 serves as a carrier member for carrying the chip 20, and when the chip 20 is carried, the substrate 10 and the chip are soldered. 20 electrical connections. The chip 20 can be a chip having different functions. In a specific embodiment, the chip 20 is a power amplifier chip, or the chip 20 can also be a radio frequency microwave millimeter wave chip or the like.

In the specific arrangement, with reference to FIG. 3, for the substrate 10 provided by the embodiment of the present application, the material of the substrate 10 may be ceramic, organic resin, metal frame or the like. The substrate 10 provided in the embodiment of the present application may include three parts, a first part is a dielectric layer composed of an epoxy resin and a glass fiber woven cloth, a second part is a conductor part composed of a metal trace and a metal through hole, and the third part is a conductor part. The green paint on the metal surface is used for solder resist. In actual preparation, the dielectric layer and the solder resist material may be a layer structure prepared by ceramic or high temperature glass material. The metal trace includes a contact layer disposed on the substrate 10 and a signal pin 11 for electrically connecting to the first end of the chip 20, and the signal pin 11 is for electrically connecting to the signal source on the chip 20. connection. Wherein, when the first end of the chip 20 is a different connection end, the corresponding contact layer is a layer corresponding to the first end.

For the chip 20 provided, the chip 20 is disposed on the substrate 10 and laminated with the substrate 10. The chip 20 includes a die (the die refers to a chip produced by a processing factory, that is, a chip that has not been packaged after the wafer has been subjected to a dicing test, and the die has only a solder joint for packaging), the bare die The sheet has two opposing faces, a first face and a second face, respectively, and the second face faces the substrate 10 when assembled with the substrate 10. The first surface is provided with a signal source and a first end (the first end is a non-signal source, such as a power source, a ground), and the first surface is provided with a first metal layer 26 and a second metal layer 28, and When disposed, the first metal layer 26 and the second metal layer 28 are electrically insulated. A via hole as a connector is formed in the die, and is a first via hole 25 and a second via hole 27, respectively, and the first via hole 25 and the second via hole 27 are holes filled with a conductive material. The signal source is electrically connected to the first metal layer 26 through the first via 25, and the first end is electrically connected to the second metal layer 28 through the second via 27. When the chip 20 is specifically disposed, the substrate of the die may be Si, GaAs, SiN, or GeSi. The chip 20 comprises three parts, the first part is on the front side of the chip (the first side of the die), and the front side of the chip is provided with active circuits and various signal sources such as transistors, integrated resistors, inductors, capacitors, etc., as shown in FIG. Two signal sources and two first ends are shown in the structure. In the structure shown in FIG. 3, the first end is used as a grounding terminal as an example for description. The two signal sources are a first signal source 21 and a second signal source 22, respectively. The two ground terminals are a first ground terminal 23 and a second ground terminal 24, respectively. The second portion is the first metal layer 26 and the second metal layer 28 on the back side of the chip (the second side of the die), and the first metal layer 26 and the second metal layer 28 are electrically insulated. When disposed, the first metal layer 26 and the second metal layer 28 may each be a layer structure prepared from any conductive material such as gold, silver, copper, etc., and the first metal layer 26 and the second metal layer 28 may be presented as A plurality of metal patterns, which may be circular, rectangular, retro-shaped, and other polygonal shapes, or may be hollow shapes with circles, rectangles, and other polygons on the metal plane. The third part is the via connecting the signal source on the front of the chip and the metal layer on the back side of the chip. When set, the signal source on the front side of the chip needs to correspond to the metal layer on the back side of the chip. As in the structure shown in FIG. 3, the first signal source 21, the second signal source 22, and the first ground end 23 are disposed on the first surface. And a second ground end 24, a corresponding second metal layer 28 and two first metal layers 26 are disposed on the second surface, and the two first metal layers 26 and the second metal layer 28 are electrically connected between the two The insulation, that is, the first metal layer 26 and the second metal layer 28 are blocked. The number of the first via holes 25 correspondingly disposed in the third portion is two, and the two first via holes 25 respectively electrically connect the two first signal sources 21 and the two first metal layers 26 in one-to-one correspondence. The number of corresponding second via holes 27 is two, and the two second via holes 27 electrically connect the first ground terminal 23 and the second ground terminal 24 to the second metal layer 28.

When the substrate 10 is connected to the chip 20, the first metal layer 26 and the second metal layer 28 need to be connected to the pins of the substrate 10. The pins may be power layers, signal pins, digital pins, ground planes, and others. One or more of the function pins. In the structure shown in FIG. 3, when the first end is the ground end, the corresponding contact layer is the ground layer 12. Similarly, if the first end is the power supply end, When the corresponding contact layer is the power layer. The above pins are connected to the bottom of the substrate 10 through via holes on the substrate 10. In a specific setting, the bottom of the substrate 10 may be a metal pad, or a ball may be implanted on the pad to realize an electrical interconnection of the semiconductor package structure.

When the substrate 10 is specifically connected to the chip 20, the signal pin 11 is electrically connected to the first metal layer 26 through the first soldering member 40, and the ground layer 12 is electrically connected to the second metal layer 28 through the second soldering member 30. In the structure shown in FIG. 3, the number of the signal pins 11 is two, the number of the ground layers 12 is one, and the two signal pins 11 are respectively corresponding to the two by the first soldering member 40. The first metal layer 26 is soldered and the ground layer 12 is soldered to the second metal layer 28 by the second soldering member 30. When the second metal layer 28 is connected to the ground layer 12, the second metal layer 28 can be electrically connected to the ground layer 12 through the plurality of second soldering members 30, and when the plurality of second soldering members 30 are used, The physical connection strength between the two is increased, thereby increasing the connection strength between the chip 20 and the substrate 10.

In the above connection, the electrical connection between the chip 20 and the substrate 10 is achieved by using the first soldering member 40 and the second soldering member 30, and the first soldering member 40 and the second soldering member 30 simultaneously realize the chip 20 and the substrate 10. Physical connection. The plurality of first soldering members 40 and the second soldering members 30 can effectively improve the connection strength between the chip 20 and the substrate 10, and the soldering members can achieve high-precision connection, thereby facilitating the miniaturization of the semiconductor package structure between the components. The electrical connection ensures the connection strength between the components of the semiconductor package structure more effectively than connecting the chip and the substrate with the silver glue used in the prior art.

It should be understood that, in the embodiment shown in FIG. 3, it is only a specific embodiment. In the semiconductor package structure provided by the embodiment of the present application, the semiconductor package structure passes the signal source and the first metal layer 26 by adopting The first vias 25 are electrically connected, reducing external wiring, thereby reducing the size of the entire semiconductor package structure, and electrically connecting the first metal layer 26 and the signal pins 11 with the first soldering member 40, enhancing the chip 20 and the substrate The strength of the connection between 10. Therefore, regardless of whether the chip 20 of the semiconductor package structure has other components electrically connected, the connection strength between the chip 20 and the substrate 10 can be improved, for example, the chip 20 has a first end, and the first end passes through the second via 27 and the first The second metal layer 28 is electrically connected. When the second metal layer 28 is electrically connected to the contact layer disposed on the substrate 10, the second soldering member 30 as exemplified in the above embodiment may be used between the second metal layer 28 and the contact layer. Connected with silver glue. The semiconductor package structure provided by the embodiment of the present application can improve the connection strength between the chip 20 and the substrate 10 by using the first soldering member 40 provided when the silver solder or the second soldering member 30 is used. In a preferred embodiment, the second metal layer 28 is electrically connected to the contact layer by the second soldering member 30, so that the connection strength between the chip 20 and the substrate 10 can be further enhanced.

When the first welding member 40 is specifically disposed, the first welding member 40 may adopt different structures, and may refer to FIG. 3 to FIG. 5 together, wherein FIG. 3 to FIG. 5 show different first welding members 40 structures. . Referring first to Figure 3, in Figure 3 the first weldment 40 comprises two layers of metal balls. When the metal ball shown in FIG. 3 is specifically prepared, a metal ball melted at the front end of the gold wire is burned by a wire bonding machine, and the metal ball is planted on the surface of the substrate 10. One or more metal balls are planted on each metal pad that needs to be interconnected according to the size, electrical, reliability, etc. of the pad. And the metal balls are further stacked on the surface of the finished ball to achieve a higher solder ball height. When a plurality of metal balls are stacked, the direction in which the metal ball is gradually lowered is adopted in a direction in which the substrate 10 is directed to the chip 20. After the ball is finished, the chip faces up, the metal layer on the back of the chip is aligned with the signal pin 11 and the ground layer 12 on the surface of the substrate 10, and the appropriate pressure and temperature are applied, and the ultrasonic vibration can also be used to complete the metal ball and the chip 20 Welding. When adopting this method, the size of the bonding wire can be selected in a large range, and the position and dimensional accuracy of the metal ball which can be planted are high, and the welding between the chip and the substrate 10 with high precision can be realized. It should be understood that although the number of metal balls of each of the weldments shown in FIG. 3 is two, the weldment provided by the embodiment of the present application may further include two or more metal balls stacked. For example, three, four, etc., the first soldering members 40 provided in the embodiments of the present application may each be at least two layers of stacked metal balls. Of course, a metal ball can also be used as the welding member. Specifically, as shown in FIG. 4, when a metal ball is used, the size of the metal ball should ensure that the gap between the chip 20 and the substrate 10 can be filled into the filling glue. When a metal ball is used as the soldering member, in the preparation of the metal ball, the metal ball is prepared by reflowing on the substrate 10 after plating. As shown in FIG. 5, as shown in FIG. 5, the first weldment 40 is a welded structure of a columnar structure. In the preparation of the columnar soldering member, the metal pillar is formed by electroplating on the substrate 10, and when the metal pillar is used, there is a certain gap between the substrate 10 and the chip 20, thereby facilitating the setting of the filling adhesive layer 50.

When the second soldering member 30 is used for the second metal layer 28 to be electrically connected to the contact layer, the second soldering member 30 has the same structure and arrangement as the first soldering member 40, and details are not described herein again.

Although several kinds of soldering members are listed in the above-mentioned drawings, the soldering members provided in the embodiments of the present application may also adopt other methods, such as selecting a solder ball array package (BGA) package, and implanting tin-silver solder balls on the substrate 10; The shape of the welded member may be spherical, columnar, multi-faceted prismatic, elongated, stacked, or other irregular spherical shape. In the formation of the above-mentioned different shapes of the welded parts, it can be prepared by different processes, such as: preparing the spherical welded parts by means of planting, preparing the columnar or multi-faceted prism-shaped welded parts by electroplating, or forming by electroplating. A long strip of welded parts that is easy to dissipate heat. In the formation of the soldering member, the material of the soldering member may be a conductive metal or a conductive alloy, and specifically may be a metal such as gold, silver, copper, tin, lead, indium, nickel, tungsten, iron, or an alloy containing the metal. It is of course also possible to use a mixed conductive material comprising these metals and resins as listed, as well as other organic conductive materials. In a specific preparation method, the welded member may also be prepared by one or more processes of sputtering, spraying, electroplating, printing, spotting, planting, and hot pressing.

It can be seen from the above description that when the chip 20 and the substrate 10 provided in the embodiment of the present application are soldered, the first soldering member 26 and the second soldering member 28 are used to directly directly correspond the substrate 10 and the chip 20. The components are soldered without using a solder paste. Therefore, the components connected by the first soldering member 26 and the second soldering member 28 in the present application can avoid the "gold embrittlement effect" when used for a long time, thereby improving the substrate 10 The strength of the connection with the chip 20, wherein the "gold embrittlement effect" means that when the content of gold in the gold-tin alloy reaches 3 wt.% or more, a brittle gold-tin compound such as AuSn _{4 is formed} , and the ductility thereof is drastically lowered. The relative brittleness is obviously increased. Even if the Au content is much lower than 3wt.% for the solder joint interface, once it exceeds 0.1wt%, another alloy (Au _1-x Ni _x )Sn ₄ is induced to migrate. The resulting interface catalysis phenomenon, after long-term reliability, brittle alloy cracking leads to failure.

In order to improve the connection strength between the components, in the semiconductor package structure provided by the embodiment of the present application, a filling layer 50 is further disposed to be filled between the chip 20 and the substrate 10. In the specific preparation, a liquid filling glue is placed on the bottom of the chip 20. The filling glue may be a molding compound or a filler, and the main component is an epoxy resin. The liquid filling glue coats the first welding member 40 and the second welding member 30 by capillary effect, and then solidifies by heating to form the filling layer 50, so that the first welding member 40 and the second welding member 30 can be relieved by stress protection, and The force on the welded parts is increased. In addition, the filler layer 50 can also serve as a buffer layer. When the semiconductor package structure is dropped, the filler layer 50 can serve as a buffer layer to reduce the force transmitted to the soldering member, thereby improving the safety of the entire semiconductor package structure.

In addition, as shown in FIG. 3 to FIG. 5, in order to improve the safety performance of the semiconductor package structure when the filling layer 50 is provided, the filling layer 50 is also wrapped with other components, such as the filling layer 50 and the signal pin 11 is also wrapped. When the contact layer is disposed on the substrate 10, the corresponding filling layer 50 also wraps the contact layer, thereby protecting the contact layer and the signal pin 11 by the filling layer 50. The filler layer 50 also wraps the first metal layer 26, and when the chip 10 has the second metal layer 28, the filler layer 50 also wraps the second metal layer 28 to protect the first metal layer 26 and the second metal layer. 28.

In order to improve the protection of the entire chip, the semiconductor package structure provided by the embodiment of the present application further provides an encapsulation layer, which encapsulates the chip 20 to package the chip 20 on the substrate 10, thereby reducing the damage of the signal source and the chip 10. . When the filling layer 50 is provided in the semiconductor package structure, the material of the encapsulating layer may be the same as the material of the filling layer, such as molding with a molding compound, so that the filling layer 50 and the encapsulating layer have a monolithic structure, which can be prepared during preparation. The preparation is formed together, thereby integrally packaging the entire chip 20 and the connection structure between the chip 20 and the substrate 10, thereby improving the safety of the entire semiconductor package structure.

In addition, for the protection of the chip 20, in addition to the structure of the encapsulation layer described above, other methods, such as the capping layer 60, may be used. For details, refer to FIG. 6. In the structure shown in FIG. The other structures except the capping layer 60 and the filling layer 50 are the same as those shown in FIG. 3 and will not be described in detail herein. In the structure shown in FIG. 6, the cover layer 60 is fixedly connected to the substrate 10, and the capping layer 60 covers the chip 20, and the chip 20 is packaged on the substrate 10, thereby realizing protection of the chip 20. When the cap layer 60 is capped, the filler layer 50 is only filled between the substrate 10 and the chip 20, and a portion of the chip 20 is wrapped. When the structure is employed, the chip 20 is protected by the capping layer 60, and since the cavity is formed between the capping layer 60 and the chip 20, the capping layer 60 can protect the chip 20 well when dropped. The adhesive layer 50 can be used as a buffer layer to reduce the force transmitted to the weldment. The structural strength of the semiconductor package structure can be effectively improved, thereby improving the reliability of the chip in use. The material of the capping layer 60 may be ceramic, organic resin, glass, LCP, metal, etc., and the shape of the capping layer 60 may be a table shape supported by a hat shape, a cup shape, a column, or the like. Of course, in the semiconductor package structure provided by the embodiment of the present application, in addition to the capping layer 60, a plastic package may be used as the structure of the protection chip 20.

The package structure provided by the embodiment of the present application can be used for a microwave radio frequency front end power amplifier (PA), which can replace the traditional silver glue or gold soldering with a gold wire package form, and the structural structure and technology use fewer process steps. The substrate area is smaller, which can effectively save the chip cost. At the same time, the package form can effectively reduce the parasitic inductance introduced by the traditional gold wire, thereby effectively improving the radio frequency electrical performance of the microwave radio frequency chip, especially the signal bandwidth.

In addition, the embodiment of the present application further provides a packaging method of a semiconductor package structure, the package method comprising the following steps:

Preparing a signal source on the first side of the die;

Opening a first via in the die, and the first via is electrically connected to the signal source;

Forming a first metal layer on a second surface of the die opposite to the first surface, and the first metal layer is electrically connected to the first via hole;

Forming a signal pin on the substrate;

The signal pin is electrically connected to the first metal layer by a first soldering member.

In the above connection, the electrical connection between the chip and the substrate is achieved by using the first soldering member, and the first soldering member simultaneously realizes the physical connection of the chip to the substrate. The first soldering member can effectively improve the connection strength between the chip and the substrate, and the soldering member can realize high-precision connection, thereby facilitating electrical connection between components developed by miniaturization of the semiconductor package structure, compared with the prior art. The silver glue is used to connect the chip and the substrate, and the connection strength between the components of the semiconductor package structure is more effectively ensured.

Taking the structure shown in FIG. 3 and FIG. 6 as an example, the packaging method of the semiconductor package structure provided by the embodiment of the present application is described in detail:

Step 1: preparing a signal source and a first end on the first side of the die;

Step 2: opening a first via 25 and a second via 27 in the die, and the first via 25 is electrically connected to the signal source, and the second via 27 is electrically connected to the first end;

Step 3: preparing a first metal layer 26 and a second metal layer 28 on a second surface opposite to the first surface of the die, and the first metal layer 26 is electrically connected to the first via hole 25, and the second metal layer 28 is The second via 27 is electrically connected;

Step 4: forming a contact layer and a signal pin 11 on the substrate 10;

Step 5: electrically connecting the signal pin 11 to the first metal layer 26 through the first soldering member 40, and electrically connecting the contact layer and the second metal layer 28 through the second soldering member 30;

Specifically, the first soldering member 40 is prepared on the signal pin 11 on the substrate 10 by sputtering, spraying, electroplating, printing, spotting, planting or hot pressing; by sputtering on the contact layer of the substrate 10, The second weldment 30 is prepared by spraying, plating, printing, spotting, planting or hot pressing. Thus, the first soldering member 40 and the second soldering member 30 can be formed on the substrate 10 by different preparation methods. For a detailed description, reference may be made to the description in the above structure.

Step 6: filling the filling layer 50 between the substrate 10 and the chip 20, and wrapping the first welding member 26 and the second welding member 28 when filling.

Specifically, a liquid filling glue is placed on the bottom of the chip, and the liquid filling glue coats the first welding member 40 and the second welding member 30 by capillary effect, and then solidifies to form a filling layer 50 by heating, thereby alleviating stress protection. The first weldment 40 and the second weldment 30. Thereby, the force of the welding member is increased, and the filling layer 50 can also serve as a buffer layer. When the semiconductor package structure is dropped, the filling layer 50 can serve as a buffer layer to reduce the force transmitted to the welding member, thereby improving the whole. The security of the semiconductor package structure.

Step 7: An encapsulation layer is disposed on the substrate, the encapsulation layer wraps the chip, and the chip 20 is packaged on the substrate 10. Alternatively, when the filling layer 50 does not wrap the chip 20, a capping layer 60 is disposed on the substrate 10, and the capping layer 60 covers the chip 20, and the chip 20 is packaged on the substrate 10.

In the specific preparation, the package is directly on the chip 10 to cover the chip 10, the signal source and the first end. When the filling layer 50 is provided in the semiconductor package structure, the material of the encapsulating layer is the same as that of the filling layer, so that the filling layer 50 and the encapsulating layer have a monolithic structure, which can be prepared together during preparation, thereby forming the entire chip. 20 and the connection structure between the chip 20 and the substrate 10 are integrally packaged, thereby improving the security of the entire chip.

When the capping layer 60 is used, the chip 20 is protected by the capping layer 60. Since the capping layer 60 forms a cavity with the chip 20, the capping layer 60 can protect the chip 20 well when dropped. And by the provision of the filling layer 50 as a buffer layer, the force transmitted to the weldment is well reduced. By adopting the above structure, the structural strength of the semiconductor package structure can be effectively improved, thereby improving the reliability of the semiconductor package structure in use.

It should be understood that, in the above specific steps, the description is made by taking the connection between the chip and the substrate by using the first soldering member and the second soldering member as an example. Of course, the chip can also be connected to the substrate through the first soldering member and the silver paste. The silver paste is disposed in the same manner as in the prior art, and will not be described in detail herein.

When the above packaging method is adopted, the device on the first surface of the chip 20 and the metal layer on the first end and the second surface are connected by using via holes, and the metal layer is electrically connected to the substrate 10 by soldering, thereby facilitating the connection. The connection of the chip 20 to the substrate 10 and the filling layer 50 as a buffer layer reduces the force on the soldering member when falling, improves the reliability of the connection between the chip 20 and the substrate 10, and improves the reliability of the semiconductor package structure. . In addition, by means of soldering, the precision is high, and the connection of components after miniaturization of the device is facilitated.

It will be apparent to those skilled in the art that various modifications and changes can be made in the present application without departing from the scope of the application. Thus, it is intended that the present invention cover the modifications and variations of the present invention.

Claims

A semiconductor package structure, comprising:

a chip comprising: a die, a signal source disposed on a first side of the die, and a first metal layer disposed on a second side of the die opposite the first face, Wherein the first via hole electrically connecting the signal source and the first metal layer is disposed in the die;

a substrate, the substrate is stacked with the chip, and a signal pin is disposed on the substrate; and

a first soldering member for electrically connecting the signal pin and the first metal layer.
The semiconductor package structure of claim 1 further comprising: a first end disposed on the first side of the die, and a second side disposed on the second side of the die a second metal layer, wherein the second via is electrically connected to the first end and the second metal layer;

A contact layer is disposed on the substrate, and the contact layer is electrically connected to the second metal layer.
The semiconductor package structure according to claim 2, wherein the contact layer and the second metal layer are electrically connected by a silver paste or a second soldering member.
The semiconductor package structure according to claim 2 or 3, wherein the first end is a power supply end, and the contact layer is a power supply layer.
The semiconductor package structure according to claim 2 or 3, wherein the first end is a ground end, and the contact layer is a ground layer.
The semiconductor package structure according to any one of claims 1 to 4, further comprising a filling layer, the filling layer is filled between the chip and the substrate, and the filling layer is used for Wrap the first weldment.
The semiconductor package structure according to any one of claims 1 to 6, wherein the filler layer is further used to wrap the signal pins.
The semiconductor package structure according to any one of claims 1 to 7, wherein the first soldering member comprises two or more metal balls.
The semiconductor package structure according to any one of claims 1 to 7, wherein the first soldering member is a welded member of a columnar structure.
The semiconductor package structure according to claim 8 or 9, wherein the first soldering member is a soldering member made of a conductive metal or a conductive alloy.
The semiconductor package structure according to claim 10, wherein the first soldering member and the second soldering member are soldered by gold, silver, copper, tin, lead, indium, nickel, tungsten or iron. Pieces.
The semiconductor package structure according to any one of claims 1 to 11, wherein the chip is a power amplifier chip.
The semiconductor package structure according to any one of claims 6 to 12, further comprising: an encapsulation layer for encapsulating the chip to package the chip on the substrate, wherein The material of the encapsulation layer is the same as the material of the filling layer.
The semiconductor package structure according to any one of claims 1 to 12, further comprising a capping layer, the capping layer being fixedly connected to the substrate, and covering the chip to package the chip On the substrate.
A packaging method for a semiconductor package structure, comprising the steps of:

Preparing a signal source on the first side of the die;

Opening a first via in the die, and the first via is electrically connected to the signal source;

Forming a first metal layer on a second surface of the die opposite to the first surface, and the first metal layer is electrically connected to the first via hole;

Forming a signal pin on the substrate;

The signal pin is electrically connected to the first metal layer by a first soldering member.
The packaging method according to claim 15, further comprising:

Preparing a first end on the first side of the die;

Opening a second via hole in the die, and the second via hole is electrically connected to the first end;

Forming a second metal layer on a second side of the die opposite the first side, and the second metal layer is electrically connected to the second via;

Forming a contact layer on the substrate;

The first end is electrically connected to the contact layer by a silver paste or a second solder joint.
The packaging method according to claim 15, wherein the signal pin is electrically connected to the first metal layer by a first soldering member; specifically:

The first weldment is prepared by sputtering, spraying, electroplating, printing, spotting, planting or hot pressing on signal pins on the substrate.
The packaging method according to any one of claims 15 to 17, further comprising:

A filler layer is filled between the substrate and the chip, and the first soldering member is wrapped while filling.
The packaging method of claim 18, further comprising:

An encapsulation layer is disposed on the substrate, the encapsulation layer encloses the chip, and the chip is packaged on the substrate; and the encapsulation layer is made of the same material as the filler layer.
The packaging method according to any one of claims 15 to 18, further comprising:

A capping layer is disposed on the substrate, and the capping layer covers the chip, and the chip is packaged on the substrate.