JP4034135B2 - Ｗｏｒｍ記憶装置のパルス列書き込み - Google Patents

Ｗｏｒｍ記憶装置のパルス列書き込み Download PDF

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Publication number
JP4034135B2
JP4034135B2 JP2002200114A JP2002200114A JP4034135B2 JP 4034135 B2 JP4034135 B2 JP 4034135B2 JP 2002200114 A JP2002200114 A JP 2002200114A JP 2002200114 A JP2002200114 A JP 2002200114A JP 4034135 B2 JP4034135 B2 JP 4034135B2
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Japan
Prior art keywords
pulse train
output
comparator
write line
input
Prior art date
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Expired - Fee Related
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JP2002200114A
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English (en)
Japanese (ja)
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JP2003109393A5 (cg-RX-API-DMAC7.html
JP2003109393A (ja
Inventor
ルン・ティー・トラン
マニシュ・シャーマ
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HP Inc
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Hewlett Packard Co
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Publication date
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Publication of JP2003109393A publication Critical patent/JP2003109393A/ja
Publication of JP2003109393A5 publication Critical patent/JP2003109393A5/ja
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Publication of JP4034135B2 publication Critical patent/JP4034135B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

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  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
JP2002200114A 2001-07-20 2002-07-09 Ｗｏｒｍ記憶装置のパルス列書き込み Expired - Fee Related JP4034135B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/908,901 US6434048B1 (en) 2001-07-20 2001-07-20 Pulse train writing of worm storage device
US09/908901 2001-07-20

Publications (3)

Publication Number Publication Date
JP2003109393A JP2003109393A (ja) 2003-04-11
JP2003109393A5 JP2003109393A5 (cg-RX-API-DMAC7.html) 2005-04-21
JP4034135B2 true JP4034135B2 (ja) 2008-01-16

Family

ID=25426385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002200114A Expired - Fee Related JP4034135B2 (ja) 2001-07-20 2002-07-09 Ｗｏｒｍ記憶装置のパルス列書き込み

Country Status (7)

Country Link
US (1) US6434048B1 (cg-RX-API-DMAC7.html)
EP (1) EP1278203B1 (cg-RX-API-DMAC7.html)
JP (1) JP4034135B2 (cg-RX-API-DMAC7.html)
KR (1) KR20030009211A (cg-RX-API-DMAC7.html)
CN (1) CN100392756C (cg-RX-API-DMAC7.html)
DE (1) DE60206223T2 (cg-RX-API-DMAC7.html)
TW (1) TWI277097B (cg-RX-API-DMAC7.html)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6434060B1 (en) * 2001-07-31 2002-08-13 Hewlett-Packard Company Write pulse limiting for worm storage device
US7085154B2 (en) * 2003-06-03 2006-08-01 Samsung Electronics Co., Ltd. Device and method for pulse width control in a phase change memory device
US7132350B2 (en) * 2003-07-21 2006-11-07 Macronix International Co., Ltd. Method for manufacturing a programmable eraseless memory
US20050035429A1 (en) * 2003-08-15 2005-02-17 Yeh Chih Chieh Programmable eraseless memory
JP5015420B2 (ja) * 2003-08-15 2012-08-29 旺宏電子股▲ふん▼有限公司 プログラマブル消去不要メモリに対するプログラミング方法
KR100634384B1 (ko) * 2004-07-16 2006-10-16 삼성전자주식회사 액세스 데이터를 저장하는 회로를 구비한 반도체 메모리 장치
JP4735948B2 (ja) * 2005-03-29 2011-07-27 日本電気株式会社 磁気ランダムアクセスメモリ及びその動作方法
JP5191628B2 (ja) * 2005-03-31 2013-05-08 ヤマハ株式会社 半導体装置構造および半導体装置の製造方法
JP2006286723A (ja) * 2005-03-31 2006-10-19 Yamaha Corp 半導体装置および同装置におけるヒューズ素子の切断方法
US7292466B2 (en) * 2006-01-03 2007-11-06 Infineon Technologies Ag Integrated circuit having a resistive memory
JP4893050B2 (ja) * 2006-03-23 2012-03-07 ヤマハ株式会社 ヒューズ素子の切断ないし高抵抗化方法
TWI430275B (zh) * 2008-04-16 2014-03-11 Magnachip Semiconductor Ltd 用於程式化非揮發性記憶體裝置之方法
KR101114061B1 (ko) * 2009-02-23 2012-02-21 주식회사 포스포 형광체 및 발광소자
JP4774109B2 (ja) * 2009-03-13 2011-09-14 シャープ株式会社 不揮発性可変抵抗素子のフォーミング処理の制御回路、並びにフォーミング処理の制御方法
US8023307B1 (en) * 2010-04-30 2011-09-20 Hewlett-Packard Development Company, L.P. Peripheral signal handling in extensible three dimensional circuits
US8427857B2 (en) * 2010-05-06 2013-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Electrical fuse programming time control scheme

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
US500855A (en) * 1893-07-04 Boiler
US4631701A (en) 1983-10-31 1986-12-23 Ncr Corporation Dynamic random access memory refresh control system
US4740924A (en) * 1985-02-25 1988-04-26 Siemens Aktiengesellschaft Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable time delay of digital signals
EP0206743A3 (en) * 1985-06-20 1990-04-25 Texas Instruments Incorporated Zero fall-through time asynchronous fifo buffer with nonambiguous empty/full resolution
US5008855A (en) * 1989-07-18 1991-04-16 Actel Corporation Method of programming anti-fuse element
US5075571A (en) 1991-01-02 1991-12-24 International Business Machines Corp. PMOS wordline boost cricuit for DRAM
US5257225A (en) * 1992-03-12 1993-10-26 Micron Technology, Inc. Method for programming programmable devices by utilizing single or multiple pulses varying in pulse width and amplitude
JPH05283708A (ja) 1992-04-02 1993-10-29 Mitsubishi Electric Corp 不揮発性半導体記憶装置，その製造方法および試験方法
US5469559A (en) 1993-07-06 1995-11-21 Dell Usa, L.P. Method and apparatus for refreshing a selected portion of a dynamic random access memory
JPH0778484A (ja) 1993-07-13 1995-03-20 Nkk Corp 記憶素子、不揮発性メモリ、不揮発性記憶装置及びそれを用いた情報記憶方法
US5471040A (en) 1993-11-15 1995-11-28 May; George Capacitive data card system
US5502395A (en) * 1994-05-25 1996-03-26 Allen; William J. Method for programming antifuses for reliable programmed links
US5684732A (en) * 1995-03-24 1997-11-04 Kawasaki Steel Corporation Semiconductor devices
US5684741A (en) 1995-12-26 1997-11-04 Intel Corporation Auto-verification of programming flash memory cells
KR100363108B1 (ko) * 1998-12-30 2003-02-20 주식회사 하이닉스반도체 반도체 메모리장치와 그 장치의 리프레쉬주기 조절방법
KR100322470B1 (ko) 1999-07-22 2002-02-07 윤종용 고밀도 노어형 플래시 메모리 장치 및 그것의 프로그램 방법

Also Published As

Publication number Publication date
EP1278203B1 (en) 2005-09-21
US6434048B1 (en) 2002-08-13
JP2003109393A (ja) 2003-04-11
CN1399274A (zh) 2003-02-26
DE60206223D1 (de) 2006-02-02
DE60206223T2 (de) 2006-08-03
EP1278203A1 (en) 2003-01-22
TWI277097B (en) 2007-03-21
CN100392756C (zh) 2008-06-04
KR20030009211A (ko) 2003-01-29

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