JP4264432B2 - プログラム可能な抵抗メモリ素子のプログラミング - Google Patents
プログラム可能な抵抗メモリ素子のプログラミング Download PDFInfo
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- JP4264432B2 JP4264432B2 JP2005255038A JP2005255038A JP4264432B2 JP 4264432 B2 JP4264432 B2 JP 4264432B2 JP 2005255038 A JP2005255038 A JP 2005255038A JP 2005255038 A JP2005255038 A JP 2005255038A JP 4264432 B2 JP4264432 B2 JP 4264432B2
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Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
- G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
- G11C2013/0066—Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/009—Write using potential difference applied between cell electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
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- Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
410 データ記憶装置
412 グループ
418 回路
Claims (9)
- プログラム可能な抵抗メモリ素子のグループと、
前記グループの選択されたメモリ素子にプログラミング電力を供給し、前記選択されたメモリ素子の実測パラメータが前記選択されたメモリ素子が既にプログラミングされていることを示すときに、前記プログラミング電力を断つことにより前記選択されたメモリ素子のプログラミング中において上書きの保護を提供する回路と、
を備え、
前記メモリ素子が抵抗クロスポイントアレイとして配列され、前記回路が選択されていないメモリ素子にアレイ電位を印加している間に選択されたメモリ素子にプログラミング電位を印加する前置増幅器を備え、前記アレイ電位と前記プログラミング電位とがほぼ等しく、それにより前記選択されたメモリ素子の等電位分離が達成されるデータ記憶装置。 - 前記実測パラメータが抵抗であり、前記選択されたメモリ素子が既にプログラムされていることを前記実測の抵抗が示すときに前記回路がプログラミング電力を断つ請求項1に記載のデータ記憶装置。
- プログラミング電圧が前記選択されたメモリ素子に印加され、前記選択されたメモリ素子の前記実測パラメータが監視され、当該実測パラメータがしきい値に達したときに前記プログラミング電力が除去される請求項1に記載のデータ記憶装置。
- 前記プログラミング電圧が時間により変化する請求項3に記載のデータ記憶装置。
- オフセット調整機能を前記前置増幅器が有し、前記アレイ電位と前記プログラミング電位とがほぼ等しくなるまで前記前置増幅器の前記オフセットを調整するテストセットアップ電流源を前記回路がさらに備える請求項1に記載のデータ記憶装置。
- 前記オフセットを調整することが、前記選択されたメモリ素子に前記テストセットアップ電流を供給し、前記選択されたメモリ素子に電圧を印加することを含み、それにより前記選択されたメモリ素子に検知電流が流れ、前記セットアップ電流が前記検知電流と等しくなるまで前記オフセットを調整することを含む請求項5に記載のデータ記憶装置。
- 前記回路がさらにテストプログラミング電流を提供する電流源と、
前記テストプログラミング電流と、前記プログラミング中に選択されたメモリ素子に流れる電流との関係を検知する電圧センサと
を備え、前記関係が前記選択されたメモリ素子が既にプログラムされていることを示す請求項1に記載のデータ記憶装置。 - 前記回路はFETと定電流源とを更に備え、
前記前置増幅器は調整可能な電圧オフセットを有し、
前記前置増幅器の出力が前記FETのゲートに結合され、前記定電流源が前記FETのドレインソース経路の第1の側に結合され、前記前置増幅器の入力が前記ドレインソース経路の第2の側に結合される請求項1に記載のデータ記憶装置。 - 前記FETの前記ドレインにおける固有キャパシタンスを、選択されたメモリ素子抵抗の線形関数として放電する手段と、
前記固有キャパシタンスを検知する検知回路と
をさらに備える請求項8に記載のデータ記憶装置。
Applications Claiming Priority (1)
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---|---|---|---|
US10/933,039 US7224598B2 (en) | 2004-09-02 | 2004-09-02 | Programming of programmable resistive memory devices |
Publications (2)
Publication Number | Publication Date |
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JP2006073010A JP2006073010A (ja) | 2006-03-16 |
JP4264432B2 true JP4264432B2 (ja) | 2009-05-20 |
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JP2005255038A Active JP4264432B2 (ja) | 2004-09-02 | 2005-09-02 | プログラム可能な抵抗メモリ素子のプログラミング |
Country Status (3)
Country | Link |
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US (1) | US7224598B2 (ja) |
JP (1) | JP4264432B2 (ja) |
DE (1) | DE102005036555B4 (ja) |
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2004
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2005
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- 2005-09-02 JP JP2005255038A patent/JP4264432B2/ja active Active
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JP2006073010A (ja) | 2006-03-16 |
US7224598B2 (en) | 2007-05-29 |
DE102005036555B4 (de) | 2010-07-01 |
US20060044878A1 (en) | 2006-03-02 |
DE102005036555A1 (de) | 2006-03-23 |
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