JP4033634B2 - 集積回路のクロック回路 - Google Patents

集積回路のクロック回路 Download PDF

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Publication number
JP4033634B2
JP4033634B2 JP2001006242A JP2001006242A JP4033634B2 JP 4033634 B2 JP4033634 B2 JP 4033634B2 JP 2001006242 A JP2001006242 A JP 2001006242A JP 2001006242 A JP2001006242 A JP 2001006242A JP 4033634 B2 JP4033634 B2 JP 4033634B2
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JP
Japan
Prior art keywords
clock
node
circuit
wave
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001006242A
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English (en)
Japanese (ja)
Other versions
JP2001255959A5 (enExample
JP2001255959A (ja
Inventor
リ・チン・ツァイ
ダニエル・クルーガー
ジョニー・キュー・ツァン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2001255959A publication Critical patent/JP2001255959A/ja
Publication of JP2001255959A5 publication Critical patent/JP2001255959A5/ja
Application granted granted Critical
Publication of JP4033634B2 publication Critical patent/JP4033634B2/ja
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Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Pulse Circuits (AREA)
JP2001006242A 2000-01-14 2001-01-15 集積回路のクロック回路 Expired - Fee Related JP4033634B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/483,283 US6594772B1 (en) 2000-01-14 2000-01-14 Clock distribution circuitry to different nodes on integrated circuit with clock coupling circuitry to maintain predetermined phase relation between output and input of adjacent nodes
US09/483283 2000-01-14

Publications (3)

Publication Number Publication Date
JP2001255959A JP2001255959A (ja) 2001-09-21
JP2001255959A5 JP2001255959A5 (enExample) 2005-07-07
JP4033634B2 true JP4033634B2 (ja) 2008-01-16

Family

ID=23919460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001006242A Expired - Fee Related JP4033634B2 (ja) 2000-01-14 2001-01-15 集積回路のクロック回路

Country Status (3)

Country Link
US (1) US6594772B1 (enExample)
JP (1) JP4033634B2 (enExample)
DE (1) DE10100278C2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6819726B2 (en) * 2000-12-07 2004-11-16 International Business Machines Corporation Dynamic phase alignment circuit
US20040260962A1 (en) * 2003-06-23 2004-12-23 Victor Suen Systems and methods for latching data
US7403640B2 (en) * 2003-10-27 2008-07-22 Hewlett-Packard Development Company, L.P. System and method for employing an object-oriented motion detector to capture images
US7117472B2 (en) * 2004-07-09 2006-10-03 Lsi Logic Corporation Placement of a clock signal supply network during design of integrated circuits
EP1891497B1 (en) * 2005-06-01 2017-04-19 Teklatech A/S A method and an apparatus for providing timing signals to a number of circuits, an integrated circuit and a node
US8205182B1 (en) 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks
US7995618B1 (en) 2007-10-01 2011-08-09 Teklatech A/S System and a method of transmitting data from a first device to a second device
WO2013124713A1 (en) * 2012-02-24 2013-08-29 Freescale Semiconductor, Inc. Clock distribution module, synchronous digital system and method therefor

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5133064A (en) * 1987-04-27 1992-07-21 Hitachi, Ltd. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
US5043596A (en) * 1988-09-14 1991-08-27 Hitachi, Ltd. Clock signal supplying device having a phase compensation circuit
JPH04373009A (ja) * 1991-06-21 1992-12-25 Hitachi Ltd クロック信号の位相調整方法及び電子装置
US5317601A (en) * 1992-08-21 1994-05-31 Silicon Graphics Clock distribution system for an integrated circuit device
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
US5815016A (en) * 1994-09-02 1998-09-29 Xilinx, Inc. Phase-locked delay loop for clock correction
DE19510038C1 (de) * 1995-03-20 1996-08-14 Siemens Nixdorf Inf Syst Anordnung zum Autokalibrieren der Taktverteilung bei synchronen digitalen Schaltungen
JP3403551B2 (ja) * 1995-07-14 2003-05-06 沖電気工業株式会社 クロック分配回路
US5744991A (en) * 1995-10-16 1998-04-28 Altera Corporation System for distributing clocks using a delay lock loop in a programmable logic circuit
JP3619352B2 (ja) * 1997-08-28 2005-02-09 株式会社ルネサステクノロジ 半導体集積回路装置
JP3085258B2 (ja) * 1997-09-10 2000-09-04 日本電気株式会社 クロック信号分配回路
JP3753355B2 (ja) * 1998-11-10 2006-03-08 株式会社ルネサステクノロジ 半導体装置

Also Published As

Publication number Publication date
DE10100278C2 (de) 2003-08-14
JP2001255959A (ja) 2001-09-21
US6594772B1 (en) 2003-07-15
DE10100278A1 (de) 2001-07-19

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