DE10100278C2 - Taktschaltungsanordnung für eine integrierte Schaltung - Google Patents

Taktschaltungsanordnung für eine integrierte Schaltung

Info

Publication number
DE10100278C2
DE10100278C2 DE10100278A DE10100278A DE10100278C2 DE 10100278 C2 DE10100278 C2 DE 10100278C2 DE 10100278 A DE10100278 A DE 10100278A DE 10100278 A DE10100278 A DE 10100278A DE 10100278 C2 DE10100278 C2 DE 10100278C2
Authority
DE
Germany
Prior art keywords
clock
node
wave
waves
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10100278A
Other languages
German (de)
English (en)
Other versions
DE10100278A1 (de
Inventor
Li C Tsai
Daniel Krueger
Johnny Q Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE10100278A1 publication Critical patent/DE10100278A1/de
Application granted granted Critical
Publication of DE10100278C2 publication Critical patent/DE10100278C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pulse Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE10100278A 2000-01-14 2001-01-04 Taktschaltungsanordnung für eine integrierte Schaltung Expired - Fee Related DE10100278C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/483,283 US6594772B1 (en) 2000-01-14 2000-01-14 Clock distribution circuitry to different nodes on integrated circuit with clock coupling circuitry to maintain predetermined phase relation between output and input of adjacent nodes

Publications (2)

Publication Number Publication Date
DE10100278A1 DE10100278A1 (de) 2001-07-19
DE10100278C2 true DE10100278C2 (de) 2003-08-14

Family

ID=23919460

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10100278A Expired - Fee Related DE10100278C2 (de) 2000-01-14 2001-01-04 Taktschaltungsanordnung für eine integrierte Schaltung

Country Status (3)

Country Link
US (1) US6594772B1 (enExample)
JP (1) JP4033634B2 (enExample)
DE (1) DE10100278C2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6819726B2 (en) * 2000-12-07 2004-11-16 International Business Machines Corporation Dynamic phase alignment circuit
US20040260962A1 (en) * 2003-06-23 2004-12-23 Victor Suen Systems and methods for latching data
US7403640B2 (en) * 2003-10-27 2008-07-22 Hewlett-Packard Development Company, L.P. System and method for employing an object-oriented motion detector to capture images
US7117472B2 (en) * 2004-07-09 2006-10-03 Lsi Logic Corporation Placement of a clock signal supply network during design of integrated circuits
WO2006128459A1 (en) * 2005-06-01 2006-12-07 Teklatech A/S A method and an apparatus for providing timing signals to a number of circuits, an integrated circuit and a node
US8205182B1 (en) 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks
US7995618B1 (en) 2007-10-01 2011-08-09 Teklatech A/S System and a method of transmitting data from a first device to a second device
US9178730B2 (en) 2012-02-24 2015-11-03 Freescale Semiconductor, Inc. Clock distribution module, synchronous digital system and method therefor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19510038C1 (de) * 1995-03-20 1996-08-14 Siemens Nixdorf Inf Syst Anordnung zum Autokalibrieren der Taktverteilung bei synchronen digitalen Schaltungen
US5751665A (en) * 1995-07-14 1998-05-12 Oki Electric Industry Co., Ltd. Clock distributing circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5133064A (en) * 1987-04-27 1992-07-21 Hitachi, Ltd. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
US5043596A (en) * 1988-09-14 1991-08-27 Hitachi, Ltd. Clock signal supplying device having a phase compensation circuit
JPH04373009A (ja) * 1991-06-21 1992-12-25 Hitachi Ltd クロック信号の位相調整方法及び電子装置
US5317601A (en) * 1992-08-21 1994-05-31 Silicon Graphics Clock distribution system for an integrated circuit device
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
US5815016A (en) * 1994-09-02 1998-09-29 Xilinx, Inc. Phase-locked delay loop for clock correction
US5744991A (en) * 1995-10-16 1998-04-28 Altera Corporation System for distributing clocks using a delay lock loop in a programmable logic circuit
JP3619352B2 (ja) * 1997-08-28 2005-02-09 株式会社ルネサステクノロジ 半導体集積回路装置
JP3085258B2 (ja) * 1997-09-10 2000-09-04 日本電気株式会社 クロック信号分配回路
JP3753355B2 (ja) * 1998-11-10 2006-03-08 株式会社ルネサステクノロジ 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19510038C1 (de) * 1995-03-20 1996-08-14 Siemens Nixdorf Inf Syst Anordnung zum Autokalibrieren der Taktverteilung bei synchronen digitalen Schaltungen
US5751665A (en) * 1995-07-14 1998-05-12 Oki Electric Industry Co., Ltd. Clock distributing circuit

Also Published As

Publication number Publication date
DE10100278A1 (de) 2001-07-19
US6594772B1 (en) 2003-07-15
JP4033634B2 (ja) 2008-01-16
JP2001255959A (ja) 2001-09-21

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8304 Grant after examination procedure
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20130801