JP3991230B2 - 強誘電体キャパシタ及びその形成方法、ならびに強誘電体メモリ - Google Patents

強誘電体キャパシタ及びその形成方法、ならびに強誘電体メモリ Download PDF

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Publication number
JP3991230B2
JP3991230B2 JP2004034597A JP2004034597A JP3991230B2 JP 3991230 B2 JP3991230 B2 JP 3991230B2 JP 2004034597 A JP2004034597 A JP 2004034597A JP 2004034597 A JP2004034597 A JP 2004034597A JP 3991230 B2 JP3991230 B2 JP 3991230B2
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Japan
Prior art keywords
ferroelectric
film
forming
lower electrode
capacitor
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Expired - Fee Related
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JP2004034597A
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English (en)
Japanese (ja)
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JP2005228852A (ja
JP2005228852A5 (enExample
Inventor
健 木島
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2004034597A priority Critical patent/JP3991230B2/ja
Priority to US11/056,033 priority patent/US20050181523A1/en
Publication of JP2005228852A publication Critical patent/JP2005228852A/ja
Publication of JP2005228852A5 publication Critical patent/JP2005228852A5/ja
Application granted granted Critical
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Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2004034597A 2004-02-12 2004-02-12 強誘電体キャパシタ及びその形成方法、ならびに強誘電体メモリ Expired - Fee Related JP3991230B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004034597A JP3991230B2 (ja) 2004-02-12 2004-02-12 強誘電体キャパシタ及びその形成方法、ならびに強誘電体メモリ
US11/056,033 US20050181523A1 (en) 2004-02-12 2005-02-11 Ferroelectric capacitor, method of manufacturing the same, and ferroelectric memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004034597A JP3991230B2 (ja) 2004-02-12 2004-02-12 強誘電体キャパシタ及びその形成方法、ならびに強誘電体メモリ

Publications (3)

Publication Number Publication Date
JP2005228852A JP2005228852A (ja) 2005-08-25
JP2005228852A5 JP2005228852A5 (enExample) 2005-10-06
JP3991230B2 true JP3991230B2 (ja) 2007-10-17

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Family Applications (1)

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JP2004034597A Expired - Fee Related JP3991230B2 (ja) 2004-02-12 2004-02-12 強誘電体キャパシタ及びその形成方法、ならびに強誘電体メモリ

Country Status (2)

Country Link
US (1) US20050181523A1 (enExample)
JP (1) JP3991230B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2899377B1 (fr) * 2006-03-30 2008-08-08 Centre Nat Rech Scient Procede de realisation de structures en multicouches a proprietes controlees
CN106030800A (zh) * 2014-02-24 2016-10-12 株式会社爱发科 电阻可变元件及其制造方法
JP6684488B2 (ja) * 2016-09-30 2020-04-22 株式会社長町サイエンスラボ 導電性ｄｌｃ膜の製造方法
CN115188591A (zh) 2016-12-02 2022-10-14 卡弗科学有限公司 存储设备和电容储能设备
JP6699827B2 (ja) * 2016-12-27 2020-05-27 Ｎｅｘｔ Ｉｎｎｏｖａｔｉｏｎ合同会社 ダイヤモンド系通電構造の製造方法
WO2018123762A1 (ja) * 2016-12-27 2018-07-05 Ｎｅｘｔ Ｉｎｎｏｖａｔｉｏｎ合同会社 ダイヤモンド系通電構造、ダイヤモンド系電子部品、及びダイヤモンド系通電構造の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5643804A (en) * 1993-05-21 1997-07-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a hybrid integrated circuit component having a laminated body
US5583359A (en) * 1995-03-03 1996-12-10 Northern Telecom Limited Capacitor structure for an integrated circuit
US5808335A (en) * 1996-06-13 1998-09-15 Vanguard International Semiconductor Corporation Reduced mask DRAM process
JP3104660B2 (ja) * 1997-11-21 2000-10-30 日本電気株式会社 半導体装置およびその製造方法

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US20050181523A1 (en) 2005-08-18

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