JP3989781B2 - ダイオードベースの固体メモリ用のプログラム可能なアドレス論理回路 - Google Patents

ダイオードベースの固体メモリ用のプログラム可能なアドレス論理回路 Download PDF

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Publication number
JP3989781B2
JP3989781B2 JP2002202568A JP2002202568A JP3989781B2 JP 3989781 B2 JP3989781 B2 JP 3989781B2 JP 2002202568 A JP2002202568 A JP 2002202568A JP 2002202568 A JP2002202568 A JP 2002202568A JP 3989781 B2 JP3989781 B2 JP 3989781B2
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Japan
Prior art keywords
address
group
elements
solid state
state memory
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JP2002202568A
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Japanese (ja)
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JP2003109394A5 (https=
JP2003109394A (ja
Inventor
ジョシュ・エヌ・ホーガン
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
JP2002202568A 2001-07-24 2002-07-11 ダイオードベースの固体メモリ用のプログラム可能なアドレス論理回路 Expired - Fee Related JP3989781B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/911919 2001-07-24
US09/911,919 US6587394B2 (en) 2001-07-24 2001-07-24 Programmable address logic for solid state diode-based memory

Publications (3)

Publication Number Publication Date
JP2003109394A JP2003109394A (ja) 2003-04-11
JP2003109394A5 JP2003109394A5 (https=) 2005-04-28
JP3989781B2 true JP3989781B2 (ja) 2007-10-10

Family

ID=25431099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002202568A Expired - Fee Related JP3989781B2 (ja) 2001-07-24 2002-07-11 ダイオードベースの固体メモリ用のプログラム可能なアドレス論理回路

Country Status (7)

Country Link
US (1) US6587394B2 (https=)
EP (1) EP1288957B1 (https=)
JP (1) JP3989781B2 (https=)
KR (1) KR20030014572A (https=)
CN (1) CN1327451C (https=)
DE (1) DE60206230T2 (https=)
TW (1) TWI223270B (https=)

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* Cited by examiner, † Cited by third party
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US5673218A (en) 1996-03-05 1997-09-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US6956757B2 (en) * 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
US7219271B2 (en) 2001-12-14 2007-05-15 Sandisk 3D Llc Memory device and method for redundancy/self-repair
KR100574961B1 (ko) * 2003-12-20 2006-05-02 삼성전자주식회사 입력버퍼 및 이를 구비하는 반도체 장치
US7151709B2 (en) * 2004-08-16 2006-12-19 Micron Technology, Inc. Memory device and method having programmable address configurations
US7277336B2 (en) * 2004-12-28 2007-10-02 Sandisk 3D Llc Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
US7212454B2 (en) * 2005-06-22 2007-05-01 Sandisk 3D Llc Method and apparatus for programming a memory array
US7304888B2 (en) * 2005-07-01 2007-12-04 Sandisk 3D Llc Reverse-bias method for writing memory cells in a memory array
KR100655078B1 (ko) * 2005-09-16 2006-12-08 삼성전자주식회사 비트 레지스터링 레이어를 갖는 반도체 메모리 장치 및그의 구동 방법
US7593256B2 (en) * 2006-03-28 2009-09-22 Contour Semiconductor, Inc. Memory array with readout isolation
KR100791341B1 (ko) * 2006-09-04 2008-01-03 삼성전자주식회사 비휘발성 메모리 장치의 기입 방법 및 그 방법을 사용하는비휘발성 메모리 장치
US7958390B2 (en) * 2007-05-15 2011-06-07 Sandisk Corporation Memory device for repairing a neighborhood of rows in a memory array using a patch table
US7966518B2 (en) * 2007-05-15 2011-06-21 Sandisk Corporation Method for repairing a neighborhood of rows in a memory array using a patch table
US7630246B2 (en) * 2007-06-18 2009-12-08 Micron Technology, Inc. Programming rate identification and control in a solid state memory
US20090086521A1 (en) * 2007-09-28 2009-04-02 Herner S Brad Multiple antifuse memory cells and methods to form, program, and sense the same
US7813157B2 (en) * 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory
US7933133B2 (en) 2007-11-05 2011-04-26 Contour Semiconductor, Inc. Low cost, high-density rectifier matrix memory
US7995368B2 (en) * 2008-02-20 2011-08-09 Toshiba America Research, Inc. Memory cell architecture
US20090225621A1 (en) * 2008-03-05 2009-09-10 Shepard Daniel R Split decoder storage array and methods of forming the same
WO2009149061A2 (en) * 2008-06-02 2009-12-10 Contour Semiconductor, Inc. Diode decoder array with non-sequential layout and methods of forming the same
US8325556B2 (en) * 2008-10-07 2012-12-04 Contour Semiconductor, Inc. Sequencing decoder circuit
US8907718B2 (en) * 2009-03-04 2014-12-09 Sensortechnics GmbH Passive resistive-heater addressing network
US8866121B2 (en) 2011-07-29 2014-10-21 Sandisk 3D Llc Current-limiting layer and a current-reducing layer in a memory device
US8659001B2 (en) 2011-09-01 2014-02-25 Sandisk 3D Llc Defect gradient to boost nonvolatile memory performance
US8637413B2 (en) 2011-12-02 2014-01-28 Sandisk 3D Llc Nonvolatile resistive memory element with a passivated switching layer
US8698119B2 (en) 2012-01-19 2014-04-15 Sandisk 3D Llc Nonvolatile memory device using a tunnel oxide as a current limiter element
US8686386B2 (en) 2012-02-17 2014-04-01 Sandisk 3D Llc Nonvolatile memory device using a varistor as a current limiter element
US20140241031A1 (en) 2013-02-28 2014-08-28 Sandisk 3D Llc Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same
CN111312321A (zh) * 2020-03-02 2020-06-19 电子科技大学 一种存储器装置及其故障修复方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1266353B (de) * 1964-03-13 1968-04-18 Bbc Brown Boveri & Cie Matrixfoermige Anordnung von Oxydschichtdioden zur Verwendung als manipulierbarer Festwertspeicher oder Informationsumsetzer
US3656120A (en) * 1969-06-05 1972-04-11 Optical Memory Systems Read only memory
JPS607388B2 (ja) * 1978-09-08 1985-02-23 富士通株式会社 半導体記憶装置
US4795657A (en) * 1984-04-13 1989-01-03 Energy Conversion Devices, Inc. Method of fabricating a programmable array
US5140189A (en) * 1991-08-26 1992-08-18 Westinghouse Electric Corp. WSI decoder and patch circuit
US5889694A (en) * 1996-03-05 1999-03-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US6087689A (en) * 1997-06-16 2000-07-11 Micron Technology, Inc. Memory cell having a reduced active area and a memory array incorporating the same
US5991225A (en) * 1998-02-27 1999-11-23 Micron Technology, Inc. Programmable memory address decode array with vertical transistors
US6373742B1 (en) * 2000-10-12 2002-04-16 Advanced Micro Device, Inc. Two side decoding of a memory array

Also Published As

Publication number Publication date
CN1327451C (zh) 2007-07-18
DE60206230D1 (de) 2006-02-02
KR20030014572A (ko) 2003-02-19
TWI223270B (en) 2004-11-01
US6587394B2 (en) 2003-07-01
US20030021176A1 (en) 2003-01-30
EP1288957B1 (en) 2005-09-21
DE60206230T2 (de) 2006-07-20
EP1288957A2 (en) 2003-03-05
JP2003109394A (ja) 2003-04-11
CN1399282A (zh) 2003-02-26
EP1288957A3 (en) 2003-10-01

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