JP2003109394A5 - - Google Patents

Download PDF

Info

Publication number
JP2003109394A5
JP2003109394A5 JP2002202568A JP2002202568A JP2003109394A5 JP 2003109394 A5 JP2003109394 A5 JP 2003109394A5 JP 2002202568 A JP2002202568 A JP 2002202568A JP 2002202568 A JP2002202568 A JP 2002202568A JP 2003109394 A5 JP2003109394 A5 JP 2003109394A5
Authority
JP
Japan
Prior art keywords
address
group
memory device
elements
solid state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002202568A
Other languages
English (en)
Japanese (ja)
Other versions
JP3989781B2 (ja
JP2003109394A (ja
Filing date
Publication date
Priority claimed from US09/911,919 external-priority patent/US6587394B2/en
Application filed filed Critical
Publication of JP2003109394A publication Critical patent/JP2003109394A/ja
Publication of JP2003109394A5 publication Critical patent/JP2003109394A5/ja
Application granted granted Critical
Publication of JP3989781B2 publication Critical patent/JP3989781B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2002202568A 2001-07-24 2002-07-11 ダイオードベースの固体メモリ用のプログラム可能なアドレス論理回路 Expired - Fee Related JP3989781B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/911919 2001-07-24
US09/911,919 US6587394B2 (en) 2001-07-24 2001-07-24 Programmable address logic for solid state diode-based memory

Publications (3)

Publication Number Publication Date
JP2003109394A JP2003109394A (ja) 2003-04-11
JP2003109394A5 true JP2003109394A5 (https=) 2005-04-28
JP3989781B2 JP3989781B2 (ja) 2007-10-10

Family

ID=25431099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002202568A Expired - Fee Related JP3989781B2 (ja) 2001-07-24 2002-07-11 ダイオードベースの固体メモリ用のプログラム可能なアドレス論理回路

Country Status (7)

Country Link
US (1) US6587394B2 (https=)
EP (1) EP1288957B1 (https=)
JP (1) JP3989781B2 (https=)
KR (1) KR20030014572A (https=)
CN (1) CN1327451C (https=)
DE (1) DE60206230T2 (https=)
TW (1) TWI223270B (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673218A (en) 1996-03-05 1997-09-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US6956757B2 (en) * 2000-06-22 2005-10-18 Contour Semiconductor, Inc. Low cost high density rectifier matrix memory
US7219271B2 (en) 2001-12-14 2007-05-15 Sandisk 3D Llc Memory device and method for redundancy/self-repair
KR100574961B1 (ko) * 2003-12-20 2006-05-02 삼성전자주식회사 입력버퍼 및 이를 구비하는 반도체 장치
US7151709B2 (en) * 2004-08-16 2006-12-19 Micron Technology, Inc. Memory device and method having programmable address configurations
US7277336B2 (en) * 2004-12-28 2007-10-02 Sandisk 3D Llc Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information
US7212454B2 (en) * 2005-06-22 2007-05-01 Sandisk 3D Llc Method and apparatus for programming a memory array
US7304888B2 (en) * 2005-07-01 2007-12-04 Sandisk 3D Llc Reverse-bias method for writing memory cells in a memory array
KR100655078B1 (ko) * 2005-09-16 2006-12-08 삼성전자주식회사 비트 레지스터링 레이어를 갖는 반도체 메모리 장치 및그의 구동 방법
US7593256B2 (en) * 2006-03-28 2009-09-22 Contour Semiconductor, Inc. Memory array with readout isolation
KR100791341B1 (ko) * 2006-09-04 2008-01-03 삼성전자주식회사 비휘발성 메모리 장치의 기입 방법 및 그 방법을 사용하는비휘발성 메모리 장치
US7958390B2 (en) * 2007-05-15 2011-06-07 Sandisk Corporation Memory device for repairing a neighborhood of rows in a memory array using a patch table
US7966518B2 (en) * 2007-05-15 2011-06-21 Sandisk Corporation Method for repairing a neighborhood of rows in a memory array using a patch table
US7630246B2 (en) * 2007-06-18 2009-12-08 Micron Technology, Inc. Programming rate identification and control in a solid state memory
US20090086521A1 (en) * 2007-09-28 2009-04-02 Herner S Brad Multiple antifuse memory cells and methods to form, program, and sense the same
US7813157B2 (en) * 2007-10-29 2010-10-12 Contour Semiconductor, Inc. Non-linear conductor memory
US7933133B2 (en) 2007-11-05 2011-04-26 Contour Semiconductor, Inc. Low cost, high-density rectifier matrix memory
US7995368B2 (en) * 2008-02-20 2011-08-09 Toshiba America Research, Inc. Memory cell architecture
US20090225621A1 (en) * 2008-03-05 2009-09-10 Shepard Daniel R Split decoder storage array and methods of forming the same
WO2009149061A2 (en) * 2008-06-02 2009-12-10 Contour Semiconductor, Inc. Diode decoder array with non-sequential layout and methods of forming the same
US8325556B2 (en) * 2008-10-07 2012-12-04 Contour Semiconductor, Inc. Sequencing decoder circuit
US8907718B2 (en) * 2009-03-04 2014-12-09 Sensortechnics GmbH Passive resistive-heater addressing network
US8866121B2 (en) 2011-07-29 2014-10-21 Sandisk 3D Llc Current-limiting layer and a current-reducing layer in a memory device
US8659001B2 (en) 2011-09-01 2014-02-25 Sandisk 3D Llc Defect gradient to boost nonvolatile memory performance
US8637413B2 (en) 2011-12-02 2014-01-28 Sandisk 3D Llc Nonvolatile resistive memory element with a passivated switching layer
US8698119B2 (en) 2012-01-19 2014-04-15 Sandisk 3D Llc Nonvolatile memory device using a tunnel oxide as a current limiter element
US8686386B2 (en) 2012-02-17 2014-04-01 Sandisk 3D Llc Nonvolatile memory device using a varistor as a current limiter element
US20140241031A1 (en) 2013-02-28 2014-08-28 Sandisk 3D Llc Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same
CN111312321A (zh) * 2020-03-02 2020-06-19 电子科技大学 一种存储器装置及其故障修复方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1266353B (de) * 1964-03-13 1968-04-18 Bbc Brown Boveri & Cie Matrixfoermige Anordnung von Oxydschichtdioden zur Verwendung als manipulierbarer Festwertspeicher oder Informationsumsetzer
US3656120A (en) * 1969-06-05 1972-04-11 Optical Memory Systems Read only memory
JPS607388B2 (ja) * 1978-09-08 1985-02-23 富士通株式会社 半導体記憶装置
US4795657A (en) * 1984-04-13 1989-01-03 Energy Conversion Devices, Inc. Method of fabricating a programmable array
US5140189A (en) * 1991-08-26 1992-08-18 Westinghouse Electric Corp. WSI decoder and patch circuit
US5889694A (en) * 1996-03-05 1999-03-30 Shepard; Daniel R. Dual-addressed rectifier storage device
US6087689A (en) * 1997-06-16 2000-07-11 Micron Technology, Inc. Memory cell having a reduced active area and a memory array incorporating the same
US5991225A (en) * 1998-02-27 1999-11-23 Micron Technology, Inc. Programmable memory address decode array with vertical transistors
US6373742B1 (en) * 2000-10-12 2002-04-16 Advanced Micro Device, Inc. Two side decoding of a memory array

Similar Documents

Publication Publication Date Title
JP2003109394A5 (https=)
US6661730B1 (en) Partial selection of passive element memory cell sub-arrays for write operation
CN1697082B (zh) 编程相变型存储器阵列到置位状态的方法及存储器件电路
US6584006B2 (en) MRAM bit line word line architecture
US20040041584A1 (en) Field programmable gate array
US8351291B2 (en) Electrically programmable fuse module in semiconductor device
US7307451B2 (en) Field programmable gate array device
JPS59500117A (ja) 冗長回路を利用した半導体メモリ
JP2010515285A (ja) スケーラブルな２端子ナノチューブスイッチを有する、不揮発性抵抗変化メモリ、ラッチ回路、および動作回路
JPH05266682A (ja) トランジスター・スナップ・バックによるアンチ・ヒューズ・プログラミング
KR970076893A (ko) 비휘발성 집적회로용 리던던시 방법 및 장치
IT201800000555A1 (it) Architettura di decodifica di riga per un dispositivo di memoria non volatile a cambiamento di fase e relativo metodo di decodifica di riga
KR102482147B1 (ko) 이퓨즈 otp 메모리
JP2015144246A (ja) ナノ電気機械ベースのメモリ
JP2006510152A (ja) 相変化型メモリ用の金属酸化膜半導体型選択ゲートの使用
US5608685A (en) Adjacent row shift redundancy circuit having signal restorer coupled to programmable links and a method thereof
JP2001210092A (ja) 半導体記憶装置
CN100568390C (zh) 含有包括可编程电阻器的存储单元的集成电路以及用于寻址包括可编程电阻器的存储单元的方法
CN117874841A (zh) 一种抗机器学习攻击的可重构仲裁器puf
JP2005243922A (ja) 半導体装置
CN106601300B (zh) 一种电熔丝存储单元、电熔丝存储阵列及其使用方法
JP3961392B2 (ja) ダイオードベースのマルチプレクサ
US7292498B2 (en) Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale and sub-microscale electronic devices
US7995368B2 (en) Memory cell architecture
EP1441442A1 (en) A low power logic gate