JP3944764B2 - 集積回路及び集積回路の製造方法 - Google Patents

集積回路及び集積回路の製造方法 Download PDF

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Publication number
JP3944764B2
JP3944764B2 JP2001193836A JP2001193836A JP3944764B2 JP 3944764 B2 JP3944764 B2 JP 3944764B2 JP 2001193836 A JP2001193836 A JP 2001193836A JP 2001193836 A JP2001193836 A JP 2001193836A JP 3944764 B2 JP3944764 B2 JP 3944764B2
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JP
Japan
Prior art keywords
conductive
integrated circuit
conductive runners
bonding pads
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001193836A
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English (en)
Japanese (ja)
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JP2002093918A5 (https=
JP2002093918A (ja
Inventor
ラヤン ヴィヴィアン
ハーバート シリング トーマス
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Agere Systems LLC
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Agere Systems LLC
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Publication date
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Publication of JP2002093918A publication Critical patent/JP2002093918A/ja
Publication of JP2002093918A5 publication Critical patent/JP2002093918A5/ja
Application granted granted Critical
Publication of JP3944764B2 publication Critical patent/JP3944764B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2001193836A 2000-06-27 2001-06-27 集積回路及び集積回路の製造方法 Expired - Fee Related JP3944764B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/604519 2000-06-27
US09/604,519 US6833557B1 (en) 2000-06-27 2000-06-27 Integrated circuit and a method of manufacturing an integrated circuit

Publications (3)

Publication Number Publication Date
JP2002093918A JP2002093918A (ja) 2002-03-29
JP2002093918A5 JP2002093918A5 (https=) 2004-07-22
JP3944764B2 true JP3944764B2 (ja) 2007-07-18

Family

ID=24419923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001193836A Expired - Fee Related JP3944764B2 (ja) 2000-06-27 2001-06-27 集積回路及び集積回路の製造方法

Country Status (5)

Country Link
US (1) US6833557B1 (https=)
JP (1) JP3944764B2 (https=)
KR (1) KR100823043B1 (https=)
GB (1) GB2368973A (https=)
TW (1) TW512511B (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888672B2 (en) 2002-11-23 2011-02-15 Infineon Technologies Ag Device for detecting stress migration properties
DE10254756B4 (de) * 2002-11-23 2011-07-07 Infineon Technologies AG, 81669 Vorrichtung und Verfahren zur Erfassung von Stressmigrations-Eigenschaften
JP4949733B2 (ja) * 2006-05-11 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置
KR100764660B1 (ko) * 2006-11-01 2007-10-08 삼성전기주식회사 주파수 종속 특성을 가지는 다중 배선의 신호 천이시뮬레이션 방법
DE102014222203B3 (de) * 2014-10-30 2016-03-10 Infineon Technologies Ag Überprüfung von Randschäden
US20190250208A1 (en) * 2018-02-09 2019-08-15 Qualcomm Incorporated Apparatus and method for detecting damage to an integrated circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6387736A (ja) * 1986-09-30 1988-04-19 Nec Corp 半導体装置
JP2842598B2 (ja) * 1988-12-01 1999-01-06 日本電気株式会社 半導体集積回路
JPH04199651A (ja) * 1990-11-29 1992-07-20 Fujitsu Ltd 半導体装置およびその製造方法
JPH06177221A (ja) * 1992-12-07 1994-06-24 Fujitsu Ltd 信頼性評価用半導体装置及び信頼性評価用の評価パターンを内蔵した製品ｌｓｉ、ウエハー
JP3269171B2 (ja) * 1993-04-08 2002-03-25 セイコーエプソン株式会社 半導体装置およびそれを有した時計
JPH07201855A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 半導体装置
JP3270807B2 (ja) * 1995-06-29 2002-04-02 シャープ株式会社 テープキャリアパッケージ
KR100190927B1 (ko) * 1996-07-18 1999-06-01 윤종용 슬릿이 형성된 금속막을 구비한 반도체 칩 장치
JP3111938B2 (ja) * 1997-09-16 2000-11-27 日本電気株式会社 半導体装置

Also Published As

Publication number Publication date
KR100823043B1 (ko) 2008-04-17
TW512511B (en) 2002-12-01
US6833557B1 (en) 2004-12-21
JP2002093918A (ja) 2002-03-29
KR20020001632A (ko) 2002-01-09
GB0115078D0 (en) 2001-08-15
GB2368973A (en) 2002-05-15

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