JP3912937B2 - 非導電性のチャージトラップゲートを利用した多ビット不揮発性メモリ - Google Patents

非導電性のチャージトラップゲートを利用した多ビット不揮発性メモリ Download PDF

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Publication number
JP3912937B2
JP3912937B2 JP22691399A JP22691399A JP3912937B2 JP 3912937 B2 JP3912937 B2 JP 3912937B2 JP 22691399 A JP22691399 A JP 22691399A JP 22691399 A JP22691399 A JP 22691399A JP 3912937 B2 JP3912937 B2 JP 3912937B2
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Japan
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state
gate
read
voltage
source
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Expired - Fee Related
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JP22691399A
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English (en)
Japanese (ja)
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JP2001057093A (ja
JP2001057093A5 (enExample
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祥一 河村
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スパンション インク
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Priority to JP22691399A priority Critical patent/JP3912937B2/ja
Priority to KR1020027001620A priority patent/KR100633752B1/ko
Priority to PCT/JP2000/001158 priority patent/WO2001013378A1/ja
Priority to US10/030,117 priority patent/US6670669B1/en
Publication of JP2001057093A publication Critical patent/JP2001057093A/ja
Publication of JP2001057093A5 publication Critical patent/JP2001057093A5/ja
Application granted granted Critical
Publication of JP3912937B2 publication Critical patent/JP3912937B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/687—Floating-gate IGFETs having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
JP22691399A 1999-08-10 1999-08-10 非導電性のチャージトラップゲートを利用した多ビット不揮発性メモリ Expired - Fee Related JP3912937B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP22691399A JP3912937B2 (ja) 1999-08-10 1999-08-10 非導電性のチャージトラップゲートを利用した多ビット不揮発性メモリ
KR1020027001620A KR100633752B1 (ko) 1999-08-10 2000-02-28 비도전성 차지 트랩 게이트를 이용한 다중 비트 비휘발성메모리
PCT/JP2000/001158 WO2001013378A1 (en) 1999-08-10 2000-02-28 Multiple-bit nonvolatile memory using non-conductive charge trap gate
US10/030,117 US6670669B1 (en) 1999-08-10 2000-02-28 Multiple-bit non-volatile memory utilizing non-conductive charge trapping gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22691399A JP3912937B2 (ja) 1999-08-10 1999-08-10 非導電性のチャージトラップゲートを利用した多ビット不揮発性メモリ

Publications (3)

Publication Number Publication Date
JP2001057093A JP2001057093A (ja) 2001-02-27
JP2001057093A5 JP2001057093A5 (enExample) 2005-06-16
JP3912937B2 true JP3912937B2 (ja) 2007-05-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP22691399A Expired - Fee Related JP3912937B2 (ja) 1999-08-10 1999-08-10 非導電性のチャージトラップゲートを利用した多ビット不揮発性メモリ

Country Status (4)

Country Link
US (1) US6670669B1 (enExample)
JP (1) JP3912937B2 (enExample)
KR (1) KR100633752B1 (enExample)
WO (1) WO2001013378A1 (enExample)

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US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
JP4674042B2 (ja) * 2001-05-25 2011-04-20 スパンション エルエルシー 不揮発性半導体記憶装置
DE10140758A1 (de) 2001-08-20 2003-04-24 Infineon Technologies Ag Speicherelement für eine Halbleiterspeichereinrichtung
US6897522B2 (en) * 2001-10-31 2005-05-24 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6925007B2 (en) 2001-10-31 2005-08-02 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
JP2003346484A (ja) * 2002-05-23 2003-12-05 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6992932B2 (en) 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US6963505B2 (en) 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US6778442B1 (en) * 2003-04-24 2004-08-17 Advanced Micro Devices, Inc. Method of dual cell memory device operation for improved end-of-life read margin
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
KR100973282B1 (ko) * 2003-05-20 2010-07-30 삼성전자주식회사 나노 결정층을 구비하는 소노스 메모리 장치
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US6998317B2 (en) 2003-12-18 2006-02-14 Sharp Laboratories Of America, Inc. Method of making a non-volatile memory using a plasma oxidized high-k charge-trapping layer
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1686592A3 (en) 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Partial erase verify
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
KR100630746B1 (ko) * 2005-05-06 2006-10-02 삼성전자주식회사 멀티-비트 및 멀티-레벨 비휘발성 메모리 소자 및 그 동작및 제조 방법
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
KR100704033B1 (ko) * 2005-08-05 2007-04-04 삼성전자주식회사 전하 트랩 형의 3-레벨 불휘발성 반도체 메모리 장치 및이에 대한 구동방법
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
KR100729357B1 (ko) 2005-08-25 2007-06-15 삼성전자주식회사 읽기 속도를 향상시킬 수 있는 플래시 메모리 장치
JP2007087441A (ja) * 2005-09-20 2007-04-05 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7593264B2 (en) * 2006-01-09 2009-09-22 Macronix International Co., Ltd. Method and apparatus for programming nonvolatile memory
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US7619919B2 (en) * 2007-01-12 2009-11-17 Marvell World Trade Ltd. Multi-level memory
US7492636B2 (en) * 2007-04-27 2009-02-17 Macronix International Co., Ltd. Methods for conducting double-side-biasing operations of NAND memory arrays
CN102169724B (zh) * 2010-02-26 2014-09-24 宏碁股份有限公司 存储器元件的操作方法
CN115942752A (zh) 2015-09-21 2023-04-07 莫诺利特斯3D有限公司 3d半导体器件和结构
USD1039225S1 (en) * 2022-07-27 2024-08-13 Jack Kassin Litter box

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3233998B2 (ja) 1992-08-28 2001-12-04 株式会社東芝 不揮発性半導体記憶装置の製造方法
JPH118325A (ja) * 1997-04-25 1999-01-12 Nippon Steel Corp 不揮発性半導体記憶装置、その製造方法、その書き込み方法、その読み出し方法、記録媒体並びに半導体記憶装置
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array

Also Published As

Publication number Publication date
JP2001057093A (ja) 2001-02-27
US6670669B1 (en) 2003-12-30
KR20030009281A (ko) 2003-01-29
WO2001013378A1 (en) 2001-02-22
KR100633752B1 (ko) 2006-10-16

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