JP3892078B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP3892078B2
JP3892078B2 JP11359296A JP11359296A JP3892078B2 JP 3892078 B2 JP3892078 B2 JP 3892078B2 JP 11359296 A JP11359296 A JP 11359296A JP 11359296 A JP11359296 A JP 11359296A JP 3892078 B2 JP3892078 B2 JP 3892078B2
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JP
Japan
Prior art keywords
signal
port
write
bit line
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11359296A
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English (en)
Japanese (ja)
Other versions
JPH09297994A5 (enExample
JPH09297994A (ja
Inventor
泰伸 中瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP11359296A priority Critical patent/JP3892078B2/ja
Priority to TW085113973A priority patent/TW311278B/zh
Priority to DE19651340A priority patent/DE19651340C2/de
Priority to CN97102207A priority patent/CN1128449C/zh
Priority to KR1019970001504A priority patent/KR100236886B1/ko
Priority to US08/916,010 priority patent/US5774410A/en
Publication of JPH09297994A publication Critical patent/JPH09297994A/ja
Publication of JPH09297994A5 publication Critical patent/JPH09297994A5/ja
Application granted granted Critical
Publication of JP3892078B2 publication Critical patent/JP3892078B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
JP11359296A 1996-05-08 1996-05-08 半導体記憶装置 Expired - Fee Related JP3892078B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP11359296A JP3892078B2 (ja) 1996-05-08 1996-05-08 半導体記憶装置
TW085113973A TW311278B (en) 1996-05-08 1996-11-14 Semiconductor memory device
DE19651340A DE19651340C2 (de) 1996-05-08 1996-12-10 Halbleiterspeichervorrichtung
CN97102207A CN1128449C (zh) 1996-05-08 1997-01-10 半导体存储装置
KR1019970001504A KR100236886B1 (ko) 1996-05-08 1997-01-20 반도체 기억장치
US08/916,010 US5774410A (en) 1996-05-08 1997-08-21 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11359296A JP3892078B2 (ja) 1996-05-08 1996-05-08 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPH09297994A JPH09297994A (ja) 1997-11-18
JPH09297994A5 JPH09297994A5 (enExample) 2005-01-13
JP3892078B2 true JP3892078B2 (ja) 2007-03-14

Family

ID=14616125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11359296A Expired - Fee Related JP3892078B2 (ja) 1996-05-08 1996-05-08 半導体記憶装置

Country Status (6)

Country Link
US (1) US5774410A (enExample)
JP (1) JP3892078B2 (enExample)
KR (1) KR100236886B1 (enExample)
CN (1) CN1128449C (enExample)
DE (1) DE19651340C2 (enExample)
TW (1) TW311278B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1153886A (ja) * 1997-08-05 1999-02-26 Oki Micro Design Miyazaki:Kk 半導体記憶装置
FR2839830A1 (fr) * 2002-05-17 2003-11-21 Koninkl Philips Electronics Nv Memoire pour decodeur turbo
DE10345549B3 (de) * 2003-09-30 2005-04-28 Infineon Technologies Ag Integrierte Speicherschaltung
JP5038657B2 (ja) * 2006-06-26 2012-10-03 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8638276B2 (en) * 2008-07-10 2014-01-28 Samsung Display Co., Ltd. Organic light emitting display and method for driving the same
JP5310439B2 (ja) * 2009-09-18 2013-10-09 ソニー株式会社 半導体メモリデバイスおよびチップ積層型の半導体デバイス
US11361819B2 (en) * 2017-12-14 2022-06-14 Advanced Micro Devices, Inc. Staged bitline precharge
US10867641B2 (en) 2018-09-14 2020-12-15 Toshiba Memory Corporation Data latch circuit and semiconductor memory device
TWI820090B (zh) * 2018-09-14 2023-11-01 日商鎧俠股份有限公司 半導體記憶裝置
US11615837B2 (en) 2020-09-22 2023-03-28 Qualcomm Incorporated Pseudo-triple-port SRAM datapaths
FR3146542A1 (fr) * 2023-03-07 2024-09-13 Stmicroelectronics International N.V. Dispositif mémoire

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4030961A (en) * 1974-08-14 1977-06-21 Saint-Gobain Industries Device for assembling glass sheets and layers of plastic material
JPS60111394A (ja) * 1983-11-22 1985-06-17 Toshiba Corp メモリセル
EP0473819A1 (en) * 1990-09-05 1992-03-11 International Business Machines Corporation Multiport memory cell
US5289432A (en) * 1991-04-24 1994-02-22 International Business Machines Corporation Dual-port static random access memory cell
JP3606951B2 (ja) * 1995-06-26 2005-01-05 株式会社ルネサステクノロジ 半導体記憶装置

Also Published As

Publication number Publication date
DE19651340C2 (de) 2000-02-03
CN1128449C (zh) 2003-11-19
TW311278B (en) 1997-07-21
KR100236886B1 (ko) 2000-01-15
KR970076807A (ko) 1997-12-12
DE19651340A1 (de) 1997-11-13
JPH09297994A (ja) 1997-11-18
US5774410A (en) 1998-06-30
CN1164742A (zh) 1997-11-12

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