JP3798569B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP3798569B2
JP3798569B2 JP04521499A JP4521499A JP3798569B2 JP 3798569 B2 JP3798569 B2 JP 3798569B2 JP 04521499 A JP04521499 A JP 04521499A JP 4521499 A JP4521499 A JP 4521499A JP 3798569 B2 JP3798569 B2 JP 3798569B2
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JP
Japan
Prior art keywords
electrode
transfer substrate
metal electrode
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04521499A
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English (en)
Japanese (ja)
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JP2000243773A5 (enExample
JP2000243773A (ja
Inventor
純一 疋田
和孝 柴田
茂幸 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP04521499A priority Critical patent/JP3798569B2/ja
Priority to US09/511,800 priority patent/US6696347B1/en
Publication of JP2000243773A publication Critical patent/JP2000243773A/ja
Priority to US10/748,327 priority patent/US7009294B2/en
Publication of JP2000243773A5 publication Critical patent/JP2000243773A5/ja
Application granted granted Critical
Publication of JP3798569B2 publication Critical patent/JP3798569B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
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    • H01L2924/1901—Structure
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP04521499A 1999-02-23 1999-02-23 半導体装置の製造方法 Expired - Fee Related JP3798569B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP04521499A JP3798569B2 (ja) 1999-02-23 1999-02-23 半導体装置の製造方法
US09/511,800 US6696347B1 (en) 1999-02-23 2000-02-23 Production process for semiconductor device
US10/748,327 US7009294B2 (en) 1999-02-23 2003-12-31 Production process for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04521499A JP3798569B2 (ja) 1999-02-23 1999-02-23 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2000243773A JP2000243773A (ja) 2000-09-08
JP2000243773A5 JP2000243773A5 (enExample) 2005-08-25
JP3798569B2 true JP3798569B2 (ja) 2006-07-19

Family

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JP04521499A Expired - Fee Related JP3798569B2 (ja) 1999-02-23 1999-02-23 半導体装置の製造方法

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US (2) US6696347B1 (enExample)
JP (1) JP3798569B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005229041A (ja) * 2004-02-16 2005-08-25 Alps Electric Co Ltd 高周波配線構造および高周波配線構造の製造方法
CN100553847C (zh) * 2004-03-31 2009-10-28 应用材料公司 用于在半导体器件制造期间转移导电零件的方法及设备
US7259581B2 (en) * 2005-02-14 2007-08-21 Micron Technology, Inc. Method for testing semiconductor components
KR100695518B1 (ko) * 2005-11-08 2007-03-14 삼성전자주식회사 범프의 형성 방법, 이를 이용한 이미지 센서의 제조 방법및 이에 의해 형성된 반도체 칩 및 이미지 센서
DE102006025960B4 (de) * 2006-06-02 2011-04-07 Infineon Technologies Ag Verfahren zur Herstellung einer integrierten Halbleitereinrichtung
US20080029686A1 (en) * 2006-08-04 2008-02-07 International Business Machines Corporation Precision fabricated silicon mold
US8361840B2 (en) * 2008-09-24 2013-01-29 Eastman Kodak Company Thermal barrier layer for integrated circuit manufacture
US11479860B2 (en) * 2019-01-10 2022-10-25 Panasonic Intellectual Property Management Co., Ltd. Pattern plate for plating and method for manufacturing wiring board
WO2020144959A1 (ja) * 2019-01-10 2020-07-16 パナソニックＩｐマネジメント株式会社 メッキ用パターン版及び配線基板の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5310699A (en) * 1984-08-28 1994-05-10 Sharp Kabushiki Kaisha Method of manufacturing a bump electrode
JPS636850A (ja) * 1986-06-26 1988-01-12 Toshiba Corp 電子部品の製造方法
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
JP2730357B2 (ja) * 1991-11-18 1998-03-25 松下電器産業株式会社 電子部品実装接続体およびその製造方法
US5492863A (en) * 1994-10-19 1996-02-20 Motorola, Inc. Method for forming conductive bumps on a semiconductor device
US5646068A (en) * 1995-02-03 1997-07-08 Texas Instruments Incorporated Solder bump transfer for microelectronics packaging and assembly
US5607099A (en) * 1995-04-24 1997-03-04 Delco Electronics Corporation Solder bump transfer device for flip chip integrated circuit devices
US6008071A (en) * 1995-09-20 1999-12-28 Fujitsu Limited Method of forming solder bumps onto an integrated circuit device
US5808360A (en) * 1996-05-15 1998-09-15 Micron Technology, Inc. Microbump interconnect for bore semiconductor dice
US6117759A (en) * 1997-01-03 2000-09-12 Motorola Inc. Method for multiplexed joining of solder bumps to various substrates during assembly of an integrated circuit package
US5984164A (en) * 1997-10-31 1999-11-16 Micron Technology, Inc. Method of using an electrically conductive elevation shaping tool
JPH11297735A (ja) * 1998-04-10 1999-10-29 Fujitsu Ltd バンプの製造方法及び半導体装置
EP1099247B1 (en) * 1998-07-15 2004-03-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method for transferring solder to a device and/or testing the device

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Publication number Publication date
JP2000243773A (ja) 2000-09-08
US20040152236A1 (en) 2004-08-05
US7009294B2 (en) 2006-03-07
US6696347B1 (en) 2004-02-24

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