JP3701781B2 - 論理回路とその作成方法 - Google Patents

論理回路とその作成方法 Download PDF

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Publication number
JP3701781B2
JP3701781B2 JP32753697A JP32753697A JP3701781B2 JP 3701781 B2 JP3701781 B2 JP 3701781B2 JP 32753697 A JP32753697 A JP 32753697A JP 32753697 A JP32753697 A JP 32753697A JP 3701781 B2 JP3701781 B2 JP 3701781B2
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JP
Japan
Prior art keywords
circuit
logic circuit
selector
delay time
node
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Expired - Fee Related
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JP32753697A
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English (en)
Japanese (ja)
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JPH11161470A5 (enExample
JPH11161470A (ja
Inventor
春造 山下
和男 矢野
靖彦 佐々木
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Renesas Technology Corp
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Renesas Technology Corp
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Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP32753697A priority Critical patent/JP3701781B2/ja
Priority to TW087119189A priority patent/TW461181B/zh
Priority to US09/197,465 priority patent/US6124736A/en
Priority to KR1019980051132A priority patent/KR100592051B1/ko
Publication of JPH11161470A publication Critical patent/JPH11161470A/ja
Priority to US09/610,697 priority patent/US6323690B1/en
Priority to US09/906,264 priority patent/US6400183B2/en
Priority to US10/122,385 priority patent/US6486708B2/en
Priority to US10/266,773 priority patent/US6696864B2/en
Publication of JPH11161470A5 publication Critical patent/JPH11161470A5/ja
Application granted granted Critical
Publication of JP3701781B2 publication Critical patent/JP3701781B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
JP32753697A 1997-11-28 1997-11-28 論理回路とその作成方法 Expired - Fee Related JP3701781B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP32753697A JP3701781B2 (ja) 1997-11-28 1997-11-28 論理回路とその作成方法
TW087119189A TW461181B (en) 1997-11-28 1998-11-19 Logic circuit and its manufacturing method
US09/197,465 US6124736A (en) 1997-11-28 1998-11-23 Logic circuit and its forming method
KR1019980051132A KR100592051B1 (ko) 1997-11-28 1998-11-27 논리회로와그작성방법
US09/610,697 US6323690B1 (en) 1997-11-28 2000-07-05 Logic circuit and its forming method
US09/906,264 US6400183B2 (en) 1997-11-28 2001-07-17 Logic circuit and its forming method
US10/122,385 US6486708B2 (en) 1997-11-28 2002-04-16 Logic circuit and its forming method
US10/266,773 US6696864B2 (en) 1997-11-28 2002-10-09 Logic circuit and its forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32753697A JP3701781B2 (ja) 1997-11-28 1997-11-28 論理回路とその作成方法

Publications (3)

Publication Number Publication Date
JPH11161470A JPH11161470A (ja) 1999-06-18
JPH11161470A5 JPH11161470A5 (enExample) 2004-11-25
JP3701781B2 true JP3701781B2 (ja) 2005-10-05

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JP32753697A Expired - Fee Related JP3701781B2 (ja) 1997-11-28 1997-11-28 論理回路とその作成方法

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US (5) US6124736A (enExample)
JP (1) JP3701781B2 (enExample)
KR (1) KR100592051B1 (enExample)
TW (1) TW461181B (enExample)

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US6546539B1 (en) * 2000-12-14 2003-04-08 Lsi Logic Corporation Netlist resynthesis program using structure co-factoring
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US6792589B2 (en) * 2001-06-15 2004-09-14 Science & Technology Corporation @ Unm Digital design using selection operations
US6489830B1 (en) * 2001-09-05 2002-12-03 Hewlett-Packard Company Apparatus and method for implementing a multiplexer
US7047175B1 (en) * 2001-11-16 2006-05-16 Synopsys, Inc. System and method for enhancing the speed of dynamic timing simulation using delay assessment at compile time
US7345511B2 (en) * 2002-08-29 2008-03-18 Technion Research & Development Foundation Ltd. Logic circuit and method of logic circuit design
US7103868B2 (en) * 2002-11-12 2006-09-05 Lsi Logic Corporation Optimizing depths of circuits for Boolean functions
US6831481B1 (en) * 2003-03-14 2004-12-14 Xilinx, Inc. Power-up and enable control circuits for interconnection arrays in programmable logic devices
US7129755B2 (en) * 2004-04-09 2006-10-31 Broadcom Corporation High-fanin static multiplexer
US7350177B2 (en) * 2004-04-29 2008-03-25 Taiwan Semiconductor Manufacturing Co., Ltd. Configurable logic and memory devices
US8004316B2 (en) * 2005-02-16 2011-08-23 Technion Research & Development Foundation Ltd. Logic circuit and method of logic circuit design
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7741879B2 (en) * 2007-02-22 2010-06-22 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Apparatus and method for generating a constant logical value in an integrated circuit
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR100933668B1 (ko) * 2008-04-30 2009-12-23 주식회사 하이닉스반도체 출력회로
KR101761530B1 (ko) 2008-07-16 2017-07-25 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8461902B2 (en) * 2011-01-27 2013-06-11 Advanced Micro Devices, Inc. Multiplexer circuit with load balanced fanout characteristics
US10151182B2 (en) 2013-02-22 2018-12-11 Samson Pump Company, Llc Modular top loading downhole pump with sealable exit valve and valve rod forming aperture
US8904322B2 (en) * 2013-03-26 2014-12-02 International Business Machines Corporation Structure for stacked CMOS circuits
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Also Published As

Publication number Publication date
TW461181B (en) 2001-10-21
US6323690B1 (en) 2001-11-27
KR19990045623A (ko) 1999-06-25
KR100592051B1 (ko) 2006-12-01
JPH11161470A (ja) 1999-06-18
US6486708B2 (en) 2002-11-26
US6696864B2 (en) 2004-02-24
US20020149394A1 (en) 2002-10-17
US6124736A (en) 2000-09-26
US6400183B2 (en) 2002-06-04
US20030071658A1 (en) 2003-04-17
US20010054916A1 (en) 2001-12-27

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