JP3692039B2 - 電界効果制御型トランジスタの製造方法 - Google Patents

電界効果制御型トランジスタの製造方法 Download PDF

Info

Publication number
JP3692039B2
JP3692039B2 JP2000583092A JP2000583092A JP3692039B2 JP 3692039 B2 JP3692039 B2 JP 3692039B2 JP 2000583092 A JP2000583092 A JP 2000583092A JP 2000583092 A JP2000583092 A JP 2000583092A JP 3692039 B2 JP3692039 B2 JP 3692039B2
Authority
JP
Japan
Prior art keywords
active region
forming
region
semiconductor substrate
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000583092A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002530872A (ja
Inventor
ヴィートマン ディートリヒ
ヴィーダー アルミン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of JP2002530872A publication Critical patent/JP2002530872A/ja
Application granted granted Critical
Publication of JP3692039B2 publication Critical patent/JP3692039B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66439Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2000583092A 1998-11-18 1999-11-18 電界効果制御型トランジスタの製造方法 Expired - Fee Related JP3692039B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19853268A DE19853268C2 (de) 1998-11-18 1998-11-18 Feldeffektgesteuerter Transistor und Verfahren zu dessen Herstellung
DE19853268.7 1998-11-18
PCT/DE1999/003674 WO2000030181A2 (de) 1998-11-18 1999-11-18 Feldeffektgesteuerter transistor und verfahren zu dessen herstellung

Publications (2)

Publication Number Publication Date
JP2002530872A JP2002530872A (ja) 2002-09-17
JP3692039B2 true JP3692039B2 (ja) 2005-09-07

Family

ID=7888269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000583092A Expired - Fee Related JP3692039B2 (ja) 1998-11-18 1999-11-18 電界効果制御型トランジスタの製造方法

Country Status (8)

Country Link
US (1) US6515319B2 (de)
EP (1) EP1138085B1 (de)
JP (1) JP3692039B2 (de)
KR (1) KR100415975B1 (de)
CN (1) CN1252829C (de)
DE (2) DE19853268C2 (de)
TW (1) TW457722B (de)
WO (1) WO2000030181A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7163864B1 (en) * 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
DE10131276B4 (de) 2001-06-28 2007-08-02 Infineon Technologies Ag Feldeffekttransistor und Verfahren zu seiner Herstellung
EP1454354B1 (de) * 2001-12-13 2015-04-15 ams AG Siliziumsubstrat mit einer isolierschicht mit teilgebieten und entsprechende anordnung
KR100458288B1 (ko) * 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 FinFET 소자 및 그 제조방법
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
KR100505712B1 (ko) * 2003-10-22 2005-08-02 삼성전자주식회사 리세스 채널 어레이 트랜지스터의 제조 방법
KR100521384B1 (ko) * 2003-11-17 2005-10-12 삼성전자주식회사 반도체 소자 및 그 제조 방법
SE527487C2 (sv) * 2004-03-02 2006-03-21 Infineon Technologies Ag En metod för framställning av en kondensator och en monolitiskt integrerad krets innefattande en sådan kondensator
WO2006006438A1 (ja) * 2004-07-12 2006-01-19 Nec Corporation 半導体装置及びその製造方法
US7271453B2 (en) * 2004-09-20 2007-09-18 International Business Machines Corporation Buried biasing wells in FETS
US7256464B2 (en) * 2005-08-29 2007-08-14 United Microelectronics Corp. Metal oxide semiconductor transistor and fabrication method thereof
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
JP2008159972A (ja) * 2006-12-26 2008-07-10 Elpida Memory Inc 半導体装置及びその製造方法
JP5605975B2 (ja) * 2007-06-04 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法、並びに、データ処理システム
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
IT1394649B1 (it) * 2009-06-01 2012-07-05 St Microelectronics Srl Fotodiodo con contatto schottky sulle pareti di trincee parallele e relativo metodo di fabbricazione
CN103779196B (zh) 2012-10-19 2016-07-06 中国科学院微电子研究所 半导体器件及其制造方法
US9831306B2 (en) 2013-12-19 2017-11-28 Intel Corporation Self-aligned gate edge and local interconnect and method to fabricate same
JP6973813B2 (ja) * 2018-04-12 2021-12-01 インテル・コーポレーション 集積回路構造、及びコンピューティングデバイス

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582794B2 (ja) * 1987-08-10 1997-02-19 株式会社東芝 半導体装置及びその製造方法
DE69213539T2 (de) * 1991-04-26 1997-02-20 Canon Kk Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
US5264716A (en) * 1992-01-09 1993-11-23 International Business Machines Corporation Diffused buried plate trench dram cell array
JP3252578B2 (ja) * 1993-12-27 2002-02-04 ソニー株式会社 平面型絶縁ゲート電界効果トランジスタの製法
JP3378414B2 (ja) * 1994-09-14 2003-02-17 株式会社東芝 半導体装置
US5539229A (en) * 1994-12-28 1996-07-23 International Business Machines Corporation MOSFET with raised STI isolation self-aligned to the gate stack
US5753947A (en) * 1995-01-20 1998-05-19 Micron Technology, Inc. Very high-density DRAM cell structure and method for fabricating it
US5692281A (en) * 1995-10-19 1997-12-02 International Business Machines Corporation Method for making a dual trench capacitor structure
US6222254B1 (en) * 1997-03-31 2001-04-24 Intel Corporation Thermal conducting trench in a semiconductor structure and method for forming the same
US6433371B1 (en) * 2000-01-29 2002-08-13 Advanced Micro Devices, Inc. Controlled gate length and gate profile semiconductor device
US6433372B1 (en) * 2000-03-17 2002-08-13 International Business Machines Corporation Dense multi-gated device design

Also Published As

Publication number Publication date
CN1252829C (zh) 2006-04-19
DE19853268A1 (de) 2000-05-31
WO2000030181A2 (de) 2000-05-25
EP1138085A2 (de) 2001-10-04
DE19853268C2 (de) 2002-04-11
JP2002530872A (ja) 2002-09-17
TW457722B (en) 2001-10-01
EP1138085B1 (de) 2009-01-14
CN1333923A (zh) 2002-01-30
DE59914950D1 (de) 2009-03-05
WO2000030181A3 (de) 2001-03-29
KR100415975B1 (ko) 2004-01-24
US6515319B2 (en) 2003-02-04
US20020014669A1 (en) 2002-02-07
KR20010080503A (ko) 2001-08-22

Similar Documents

Publication Publication Date Title
US9793373B2 (en) Field effect transistor structure with abrupt source/drain junctions
JP3692039B2 (ja) 電界効果制御型トランジスタの製造方法
US7154118B2 (en) Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
KR100781580B1 (ko) 이중 구조 핀 전계 효과 트랜지스터 및 그 제조 방법
TW526564B (en) Method of fabricating semiconductor side wall fin
KR101066975B1 (ko) 3중 게이트 및 게이트 어라운드 mosfet 디바이스, 및그 제조 방법
US9093466B2 (en) Epitaxial extension CMOS transistor
JPH10178180A (ja) 単ゲート及び双ゲート電界効果トランジスタ及び作製方法
US20070102756A1 (en) FinFET transistor fabricated in bulk semiconducting material
US20050260818A1 (en) Semiconductor device and method for fabricating the same
US20010017392A1 (en) Vertical transport MOSFETs and method for making the same
EP1147552A1 (de) Feldeffekttransistorstruktur mit abrupten source/drain-übergangen
JP2006507684A (ja) 2トランジスタnorデバイス
US7187022B2 (en) Semiconductor device having a multi-bridge-channel and method for fabricating the same
US6864129B2 (en) Double gate MOSFET transistor and method for the production thereof
US6812522B2 (en) Lateral type power MOS transistor having trench gate formed on silicon-on-insulator (SOI) substrate
JPH0766404A (ja) 半導体装置及びその製造方法
KR100597459B1 (ko) 반도체 소자의 게이트 전극형성방법
JPS63211762A (ja) 絶縁ゲ−ト型半導体装置とその製法

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040924

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041217

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050420

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050525

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050617

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080624

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090624

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100624

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110624

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110624

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120624

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120624

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130624

Year of fee payment: 8

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees