JP3623840B2 - データ処理装置及びマイクロプロセッサ - Google Patents
データ処理装置及びマイクロプロセッサ Download PDFInfo
- Publication number
- JP3623840B2 JP3623840B2 JP01501696A JP1501696A JP3623840B2 JP 3623840 B2 JP3623840 B2 JP 3623840B2 JP 01501696 A JP01501696 A JP 01501696A JP 1501696 A JP1501696 A JP 1501696A JP 3623840 B2 JP3623840 B2 JP 3623840B2
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- vliw
- instructions
- risc
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01501696A JP3623840B2 (ja) | 1996-01-31 | 1996-01-31 | データ処理装置及びマイクロプロセッサ |
| TW086100225A TW334544B (en) | 1996-01-31 | 1997-01-10 | Data processor |
| KR1019970001570A KR100535852B1 (ko) | 1996-01-31 | 1997-01-21 | 데이타처리장치 |
| US08/791,811 US6023757A (en) | 1996-01-31 | 1997-01-30 | Data processor |
| US09/382,598 US6496919B1 (en) | 1996-01-31 | 1999-08-25 | Data processor |
| US10/281,148 US6760832B2 (en) | 1996-01-31 | 2002-10-28 | Data processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01501696A JP3623840B2 (ja) | 1996-01-31 | 1996-01-31 | データ処理装置及びマイクロプロセッサ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH09212358A JPH09212358A (ja) | 1997-08-15 |
| JPH09212358A5 JPH09212358A5 (enExample) | 2004-12-24 |
| JP3623840B2 true JP3623840B2 (ja) | 2005-02-23 |
Family
ID=11877080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01501696A Expired - Fee Related JP3623840B2 (ja) | 1996-01-31 | 1996-01-31 | データ処理装置及びマイクロプロセッサ |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US6023757A (enExample) |
| JP (1) | JP3623840B2 (enExample) |
| KR (1) | KR100535852B1 (enExample) |
| TW (1) | TW334544B (enExample) |
Families Citing this family (119)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN118093017A (zh) * | 2022-11-22 | 2024-05-28 | 上海兆芯集成电路股份有限公司 | 高效指令转译方法、以及处理器 |
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| US5448746A (en) * | 1990-05-04 | 1995-09-05 | International Business Machines Corporation | System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution |
| US5778423A (en) * | 1990-06-29 | 1998-07-07 | Digital Equipment Corporation | Prefetch instruction for improving performance in reduced instruction set processor |
| EP0551090B1 (en) * | 1992-01-06 | 1999-08-04 | Hitachi, Ltd. | Computer having a parallel operating capability |
| US5309564A (en) * | 1992-03-19 | 1994-05-03 | Bradley Graham C | Apparatus for networking computers for multimedia applications |
| JPH06250847A (ja) * | 1993-02-25 | 1994-09-09 | Fujitsu Ltd | 並列論理型言語の命令をvliw方式の命令に変換する変換方式 |
| JPH07110769A (ja) * | 1993-10-13 | 1995-04-25 | Oki Electric Ind Co Ltd | Vliw型計算機 |
| US5542059A (en) * | 1994-01-11 | 1996-07-30 | Exponential Technology, Inc. | Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order |
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| US6496922B1 (en) * | 1994-10-31 | 2002-12-17 | Sun Microsystems, Inc. | Method and apparatus for multiplatform stateless instruction set architecture (ISA) using ISA tags on-the-fly instruction translation |
| US5638525A (en) * | 1995-02-10 | 1997-06-10 | Intel Corporation | Processor capable of executing programs that contain RISC and CISC instructions |
| US5752035A (en) * | 1995-04-05 | 1998-05-12 | Xilinx, Inc. | Method for compiling and executing programs for reprogrammable instruction set accelerator |
| US5699536A (en) * | 1995-04-13 | 1997-12-16 | International Business Machines Corporation | Computer processing system employing dynamic instruction formatting |
| US5794062A (en) * | 1995-04-17 | 1998-08-11 | Ricoh Company Ltd. | System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization |
| US5774686A (en) * | 1995-06-07 | 1998-06-30 | Intel Corporation | Method and apparatus for providing two system architectures in a processor |
| JP3451595B2 (ja) * | 1995-06-07 | 2003-09-29 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 二つの別個の命令セット・アーキテクチャへの拡張をサポートすることができるアーキテクチャ・モード制御を備えたマイクロプロセッサ |
| US5826089A (en) * | 1996-01-04 | 1998-10-20 | Advanced Micro Devices, Inc. | Instruction translation unit configured to translate from a first instruction set to a second instruction set |
| JP3623840B2 (ja) | 1996-01-31 | 2005-02-23 | 株式会社ルネサステクノロジ | データ処理装置及びマイクロプロセッサ |
| US5784636A (en) * | 1996-05-28 | 1998-07-21 | National Semiconductor Corporation | Reconfigurable computer architecture for use in signal processing applications |
| US5828897A (en) * | 1996-12-19 | 1998-10-27 | Raytheon Company | Hybrid processor and method for executing incrementally upgraded software |
| US6202143B1 (en) * | 1997-08-21 | 2001-03-13 | Samsung Electronics Co., Ltd. | System for fetching unit instructions and multi instructions from memories of different bit widths and converting unit instructions to multi instructions by adding NOP instructions |
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1996
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1997
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- 1997-01-21 KR KR1019970001570A patent/KR100535852B1/ko not_active Expired - Fee Related
- 1997-01-30 US US08/791,811 patent/US6023757A/en not_active Expired - Lifetime
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|---|---|
| US6023757A (en) | 2000-02-08 |
| TW334544B (en) | 1998-06-21 |
| KR100535852B1 (ko) | 2006-05-10 |
| US6496919B1 (en) | 2002-12-17 |
| KR970059916A (ko) | 1997-08-12 |
| US6760832B2 (en) | 2004-07-06 |
| US20030065911A1 (en) | 2003-04-03 |
| JPH09212358A (ja) | 1997-08-15 |
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