JP3424344B2 - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JP3424344B2 JP3424344B2 JP23241494A JP23241494A JP3424344B2 JP 3424344 B2 JP3424344 B2 JP 3424344B2 JP 23241494 A JP23241494 A JP 23241494A JP 23241494 A JP23241494 A JP 23241494A JP 3424344 B2 JP3424344 B2 JP 3424344B2
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- sealing resin
- board
- side sealing
- lsi chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/4805—Shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
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- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06579—TAB carriers; beam leads
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09072—Hole or recess under component or special relationship between hole and component
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
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- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Description
ード上にLSIチップを搭載して樹脂封止して構成され
る半導体装置に関する。
好適なチップキャリアパッケージがある。例えば、内部
配線が形成され、裏面に半田ボールが形成されたボード
を用いて、これにLSIチップを搭載して樹脂封止する
ようにしたものが、BGA(Ball Glid Array)パッケ
ージとして提案されている(米国特許第5,241,1
33号参照)。
GAパッケージには次のような問題があった。第1に、
封止樹脂の成形圧縮によってボードに反りが生じるた
め、ボードがある大きさ以上になると多数の半田ボール
相互の平坦度が悪くなり、実装不良が発生し易い。第2
に、ボード(特にプラスチックボード)のLSIチップ
搭載部の下部周辺のボード自体やボードに設けられたス
ルーホール部から水分が侵入し、耐湿性不良が発生しや
すい。第3に、上述した水分の侵入があると、実装時に
高温でのパッケージの乾燥処理等が必要になるが、この
高温処理を行うとボードと封止樹脂層間の剥離が生じ易
い。
で、信頼性向上を図った樹脂封止構造の半導体装置を提
供することを目的としている。
置は、第1に、内部配線を有し、裏面に半田ボールが形
成されたボードと、このボード上に搭載されたLSIチ
ップと、このLSIチップ搭載部を封止する表面側封止
樹脂層と、前記ボードの前記LSIチップ搭載部と対向
する裏面部を封止する前記表面側封止樹脂層と同等の大
きさと厚みを有する裏面側封止樹脂層とを有することを
特徴としている。この発明において好ましくは、前記ボ
ードの前記LSIチップ搭載部周囲に貫通孔が設けら
れ、この貫通孔を介して表面側封止樹脂層と前記裏面側
封止樹脂層とを連通させる。
部配線を有し且つチップ格納用孔が開けられたボード
と、このボートの裏面に前記チップ格納用孔を塞ぐよう
に添設された放熱板と、前記ボードのチップ格納用孔を
介して前記放熱板上に搭載されたLSIチップと、この
LSIチップ搭載部を封止する表面側封止樹脂層と、前
記ボード裏面の前記放熱板が添設された部分を封止する
裏面側封止樹脂層とを有することを特徴としている。こ
の発明において好ましくは、前記放熱板の前記LSIチ
ップ搭載部周囲に貫通孔が設けられ、この貫通孔を介し
て前記表面側封止樹脂層と前記裏面側封止樹脂層とを連
通させる。
ードの表裏に同じように封止樹脂層が設けられるため、
樹脂の圧縮等によるボードの反りが発生しにくい。ま
た、LSIチップ搭載部を表裏から樹脂層で保護してい
るため、水分の侵入に対しても強い。従って実装時の乾
燥処理も短縮、場合によって省略でき、ボードと封止樹
脂層間の剥離が防止できる。更にこの発明によると、L
SIチップ搭載部の裏面に封止樹脂層が設けられるか
ら、パッケージを平置きしたときにも、半田ボールが浮
いた状態が得られる。従って、半田ボール下部の傷や汚
れ、静電破壊等の心配が少なくなり、積み重ね置きやラ
フな取扱いも可能になる。
説明する。図1は、この発明の実施例による半導体装置
の断面図であり、図2はLSIチップ搭載前の斜視図で
ある。マザーボード1には予め、表面に内部配線11が
プリントされ、裏面には半田ボール14が形成されてい
る。マザーボード1にはまた、LSIチップ搭載部12
の周囲を取り囲むように、スリット状の貫通孔13a〜
13dが形成されている。
載され、例えばボンディングワイヤ3によりLSIチッ
プ2上の端子とマザーボード1上の配線11の端子との
間が接続される。搭載されたLSIチップ2は、表面側
封止樹脂層4により封止される。この表面封止樹脂層4
に対向して、マザーボード1の裏面にも、裏面封止樹脂
層5が設けられる。表面側封止樹脂層4と裏面側封止樹
脂層5とは、その大きさ及び厚みがほぼ同等になるよう
にする。表面側封止樹脂層4と裏面側封止樹脂層5と
は、マザーボード1に開けられた貫通孔13a〜13d
を介して一体的に成形されて連通する。
脂層4と裏面側封止樹脂層5を設けることによって、マ
ザーボード1の反りが確実に防止される。またLSIチ
ップ搭載部への水分の侵入も防止される。この水分侵入
抑制の効果と、表面側樹脂層4と裏面側封止樹脂層5と
が貫通孔13a〜13dを介して強固に一体化される効
果とが相まって、樹脂の剥離等も確実に防止される。
の実施例と対応する部分には先の実施例と同一符号を付
して詳細な説明は省く。この実施例では、マザーボード
1とは別に放熱板5が用いられる。放熱板5は例えば、
熱伝導率の高いセラミックや金属とする。マザーボード
1にはまた、予めLSIチップ格納用孔15が開けられ
ている。放熱板6は、マザーボード1の裏面にLSIチ
ップ格納用孔15を塞ぐように添設される。そしてこの
放熱板6の表面にLSIチップ2が搭載される。
部の周囲に貫通孔61a〜61d(61c,61dは図
面の垂直方向に設けられて、図3では見えない)が設け
られている。そして先の実施例と同様に、搭載されたL
SIチップ2を封止する表面側封止樹脂層4とこれに対
向する裏面側封止樹脂層5とが設けられて、これらは貫
通孔61a〜61dを介して互いに連通する。表面側封
止樹脂層4と裏面側封止樹脂層5とはほぼ同じ大きさと
厚みをもって形成することが好ましい。
効果が得られる。またこの実施例によると、搭載される
LSIチップ2がマザーボード1上に突出することがな
くなる。従って、表面側封止樹脂層4を先の実施例に比
べて薄くすることができ、これに応じて裏面封止樹脂層
5も薄くすることができる。以上により、全体が薄型化
できる。
る。この実施例では、マザーボード1を両面プリント基
板として、その表面にLSIチップ2を搭載すると共
に、これに対向する裏面にもLSIチップ7を搭載して
いる。これらLSIチップ2,7を封止するように、表
面側封止樹脂層4と裏面側封止樹脂層5とが設けられ
る。この実施例によると、表裏の対称性がより向上する
ため、一層高い信頼性が期待できる。
る。この実施例は、マザーボード1に、先の実施例で示
した貫通孔を設けていない他、図1の実施例と同様であ
る。表面側封止樹脂層4と裏面側封止樹脂層5とが直接
接しないため、ここまでの実施例に比べて若干強度的に
弱いが、ボードの反り防止や水分侵入防止の効果は充分
得られる。
半田実装の応用例を、図6〜図8に示す。図6は、実装
ボード8に予め孔9を開けておき、裏面側封止樹脂層5
が実装の妨げにならないようにして実装した例である。
図7は、実装ボード8に孔を設けることなく、代わりに
中間ボード10を用いて、 これを介して実装した例で
ある。図8は、実装ボード8に孔を開けることなく、ま
た図7のような中間ボードも用いることなく実装した例
である。裏面封止樹脂層5が半田ボール14より薄い場
合、例えば先の図5の実施例により裏面封止樹脂層5を
充分薄く形成した場合には、この様な実装が可能にな
る。
部配線を有するボードにLSIチップを搭載して、その
LSIチップ搭載部を樹脂封止すると共に、その表面側
封止樹脂層に対向して裏面部を封止する裏面側封止樹脂
層を設けることにより、ボードの反りや水分侵入等を防
止して信頼性の高い半導体装置を得ることができる。
である。
である。
である。
面図である。
面図である。
である。
装例である。
装例である。
プ搭載部、13a〜13d…貫通孔、14…半田ボー
ル、15…チップ格納用孔、2…LSIチップ、3…ボ
ンディングワイヤ、4…表面側封止樹脂層、5…裏面側
封止樹脂層、6…放熱板、61a,61b…貫通孔。
Claims (5)
- 【請求項1】 内部配線を有し、裏面に半田ボールが形
成されたボードと、 このボード上に搭載されたLSIチップと、 このLSIチップ搭載部を封止する表面側封止樹脂層
と、 前記ボードの前記LSIチップ搭載部と対向する裏面部
を封止する前記表面側封止樹脂層と同等の大きさと厚み
を有する裏面側封止樹脂層とを有することを特徴とする
半導体装置。 - 【請求項2】 前記ボードの前記LSIチップ搭載部周
囲に貫通孔が設けられ、この貫通孔を介して表面側封止
樹脂層と前記裏面側封止樹脂層とが連通することを特徴
とする請求項1に記載の半導体装置。 - 【請求項3】 前記ボードの前記LSIチップ搭載部の
裏面に別のLSIチップが搭載されて、前記裏面側封止
樹脂層で封止されていることを特徴とする請求項1又は
2に記載の半導体装置。 - 【請求項4】 内部配線を有し且つチップ格納用孔が開
けられたボードと、 このボートの裏面に前記チップ格納用孔を塞ぐように添
設された放熱板と、 前記ボードのチップ格納用孔を介して前記放熱板上に搭
載されたLSIチップと、 このLSIチップ搭載部を封止する表面側封止樹脂層
と、 前記ボード裏面の前記放熱板が添設された部分を封止す
る裏面側封止樹脂層とを有することを特徴とする半導体
装置。 - 【請求項5】 前記放熱板の前記LSIチップ搭載部周
囲に貫通孔が設けられ、この貫通孔を介して前記表面側
封止樹脂層と前記裏面側封止樹脂層とが連通することを
特徴とする請求項4に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23241494A JP3424344B2 (ja) | 1994-09-01 | 1994-09-01 | 半導体装置 |
US08/522,550 US5596227A (en) | 1994-09-01 | 1995-09-01 | Ball grid array type semiconductor device |
KR1019950028620A KR0185607B1 (ko) | 1994-09-01 | 1995-09-01 | 볼 그리드 어레이 타입의 반도체 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23241494A JP3424344B2 (ja) | 1994-09-01 | 1994-09-01 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0878565A JPH0878565A (ja) | 1996-03-22 |
JP3424344B2 true JP3424344B2 (ja) | 2003-07-07 |
Family
ID=16938885
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23241494A Expired - Fee Related JP3424344B2 (ja) | 1994-09-01 | 1994-09-01 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5596227A (ja) |
JP (1) | JP3424344B2 (ja) |
KR (1) | KR0185607B1 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5760465A (en) * | 1996-02-01 | 1998-06-02 | International Business Machines Corporation | Electronic package with strain relief means |
US6472252B2 (en) | 1997-07-23 | 2002-10-29 | Micron Technology, Inc. | Methods for ball grid array (BGA) encapsulation mold |
US5923959A (en) * | 1997-07-23 | 1999-07-13 | Micron Technology, Inc. | Ball grid array (BGA) encapsulation mold |
US6297078B1 (en) * | 1997-12-31 | 2001-10-02 | Intel Corporation | Integrated circuit package with bond wires at the corners of an integrated circuit |
US6084297A (en) * | 1998-09-03 | 2000-07-04 | Micron Technology, Inc. | Cavity ball grid array apparatus |
EP1990831A3 (en) * | 2000-02-25 | 2010-09-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
US7247932B1 (en) | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
US7855342B2 (en) * | 2000-09-25 | 2010-12-21 | Ibiden Co., Ltd. | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
US6613606B1 (en) * | 2001-09-17 | 2003-09-02 | Magic Corporation | Structure of high performance combo chip and processing method |
JP2003229443A (ja) * | 2002-02-01 | 2003-08-15 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6734039B2 (en) | 2002-09-06 | 2004-05-11 | Advanpack Solutions Pte Ltd. | Semiconductor chip grid array package design and method of manufacture |
JP4031748B2 (ja) * | 2003-10-06 | 2008-01-09 | ローム株式会社 | 半導体レーザ |
JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
DE102008011187A1 (de) * | 2007-04-18 | 2008-10-30 | Korea Advanced Institute Of Science & Technology | Textile Halbleiter-Baugruppe und Verfahren zur Montage und zur Fertigung der Baugruppe |
JP6610460B2 (ja) * | 2016-07-26 | 2019-11-27 | 株式会社デンソー | 電子装置、及び、電子装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0476945A (ja) * | 1990-07-19 | 1992-03-11 | Ibiden Co Ltd | 電子部品搭載用基板 |
JP2723195B2 (ja) * | 1990-12-14 | 1998-03-09 | 松下電工株式会社 | 半導体パッケージ |
US5285352A (en) * | 1992-07-15 | 1994-02-08 | Motorola, Inc. | Pad array semiconductor device with thermal conductor and process for making the same |
JPH06283650A (ja) * | 1993-03-26 | 1994-10-07 | Ibiden Co Ltd | 半導体装置 |
-
1994
- 1994-09-01 JP JP23241494A patent/JP3424344B2/ja not_active Expired - Fee Related
-
1995
- 1995-09-01 KR KR1019950028620A patent/KR0185607B1/ko not_active IP Right Cessation
- 1995-09-01 US US08/522,550 patent/US5596227A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR960012441A (ko) | 1996-04-20 |
KR0185607B1 (ko) | 1999-03-20 |
US5596227A (en) | 1997-01-21 |
JPH0878565A (ja) | 1996-03-22 |
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